JPS6129534B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to apparatus and methods for forming electrical connections through insulating layers to conductive regions, and more particularly to preventing charge accumulation during exposure by a charged beam. , relates to a semiconductor wafer processing method and processing apparatus.

The use of charged beams, such as electron beams, in semiconductor manufacturing processes has been known for many years. For example, in the manufacture of various types of semiconductor devices, electron beams are scanned to accurately expose patterns. Electron beam processes are generally more accurate than other forms of patterning. In one example using electron beam technology, a semiconductor wafer to be processed is coated with an electron beam resist. The wafer is typically formed from a semiconductor material such as doped silicon;
Covered by silicon dioxide or other insulating layer. A semiconductor wafer coated with a silicon dioxide layer and a resist layer is placed in a metal holder before being exposed by an electron beam. The wafer placed in the holder is then placed in an electron beam exposure apparatus. Electron beam equipment typically includes automatic means for controlling the deflection of the electron beam and thus the position of the electron beam as it impinges on the resist-coated wafer.
By deflecting (or scanning) the electron beam, a pattern is exposed in the electron beam resist applied on the surface of the wafer.

In a typical example, the electron beam is halved
The electron beam spot is incident on the resist with a micron diameter spot that can be deflected with an accuracy better than 0.02 microns. The above accuracy on electron beam equipment can be readily achieved with conventional electron beam systems currently available from manufacturers. Although the inherent high precision of electron beam equipment has enabled semiconductor processing processes to obtain similarly precise semiconductor device patterns, certain Various problems have arisen.

The wafer to be exposed contains a conductive region (such as a semiconductor region, i.e. a substrate made of doped silicon), is covered with an insulating layer (such as silicon dioxide), and is coated with an electron beam resist. A layer is formed thereon. When the wafer is exposed to an electron beam, charge buildup occurs in the conductive regions. This charge accumulation occurs as electrons from the incident electron beam pass through the electron beam resist layer, penetrate the insulating layer, and impinge on the conductive region. Since the conductive region is covered with an insulating layer, charge will accumulate in the conductive region if the conductive region is not connected to a discharge sink via a conductive channel. The magnitude of this charge is generally determined by, among other things, the current of the incident electron beam,
It is a function of the charge storage period and the conductivity between the conductive region and the discharge sink. Charge accumulation naturally creates unwanted electrostatic fields. Although the charge distribution within the conductive region may be generally uniform, the pattern of the electrostatic field outside the semiconductor wafer, through which the electron beam must pass, is not. The magnitude of the electrostatic field varies as a function of the position of the wafer relative to the incident electron beam in a plane perpendicular to the incident electron beam. It has been observed that in some cases the charge build-up is hundreds of volts or more, resulting in electron beam deflection errors relative to the wafer of more than 15 microns. A position error of 15 microns due to accumulated charge is of course unacceptable if it is necessary to obtain a positional accuracy of better than 0.1 micron.

In order to avoid or reduce the problem of position errors due to accumulated charge, attempts have been made to drain the charge from the conductive regions. One technique to circumvent this problem is to etch away the insulating layer to expose the conductive areas, so that during the electron beam exposure the conductive areas can be electrically contacted to ground, such as via leads. We have adopted a method that allows In the process, the edges of the insulating wafer are immersed in an etchant to remove the insulation, thereby allowing electrical contact, such as leads, to the conductive areas. The above process is laborious and generally unsuitable in that it often results in contaminants on the wafer surface. Special etching has been employed on the backside of the wafer to help avoid contamination on the wafer surface. Etching of the backside is performed by suspending the wafer on an etching solution and dissolving the insulating layer formed on the backside of the wafer. The float etching process described above is laborious and even if employed, it remains difficult to keep the top surface free of contamination.

In addition to etching steps, mechanical polishing or drilling steps have been attempted to make electrical contact through the insulating layer to the conductive regions. This mechanical process, however, tends to form dust from the abrasive material, thereby contaminating the wafer surface.

Other mechanical and chemical methods for making electrical contact to conductive regions are not yet sufficient and therefore improvements are needed to make electrical contact to conductive regions covered by an insulating layer. There is a need for a method and apparatus. It is desirable that the improved method and apparatus be easily integrated into conventional semiconductor processing steps.

It is an object of the present invention to form an electrical connection path through an insulating layer between a conductive region of a semiconductor wafer and a metallic wafer holder to eliminate unnecessary charges accumulated in the conductive region during electron beam exposure. An object of the present invention is to provide a method and apparatus for processing a semiconductor wafer, which allows the exposure electron beam to flow into a holder, thereby preventing undesired deflection of an exposure electron beam.

Processing steps for semiconductor wafers according to the present invention include, in conjunction with a wafer having conductive regions, forming an insulating layer covering the conductive regions; forming a resist covering the insulating layer; maintaining the wafer conductive; applying a high energy discharge between the wafer and the holder to form an electrical connection between the wafer and the conductive region; exposing the wafer placed in the holder so that electrons injected into the conductive region are caused to flow out through the electrical connection between the conductive region and the holder. After this, the exposed wafer is removed from the holder and processed to develop the pattern scanned by the electron beam. If additional electron beam patterns are similarly formed on the wafer, the coated wafer is again placed in the wafer holder and a high energy discharge is applied to increase the electrical conductivity within the placed wafer. Electrical connections are made again between the region and the wafer holder. After this, the newly applied resist is exposed by an electron beam device and the electrons injected into the conductive areas are forced out through the electrical connection between the holder and the wafer.

The foregoing objects and other objects, features and advantages of the invention will become apparent from the following more detailed description of the preferred embodiments of the invention, which are illustrated in the accompanying drawings.

In FIG. 1, an apparatus embodying the invention is shown. The discharge device 7 is connected to the surface of the semiconductor wafer 3 by a first lead wire 8 .
The discharge device 7 is connected to an electrically conductive holder 10 by a second lead wire 9. Retainer 10 is typically formed of any non-magnetic metal, such as non-magnetic stainless steel. Non-magnetic metals are preferred to avoid the presence of magnetic fields that adversely affect the electron beam. The holder 10 has an inner wall 29 defining an opening 2. On the upper surface 28 of the retainer 10, a flange extends from the surface 28 past the wall 29 and into a portion of the opening 2. The flange 21 serves to mechanically stop the wafer 3 that is inserted from the bottom of the opening and raised to face the bottom of the flange 21 . Flange 21 is also preferably made of a non-magnetic metal such as phosphor bronze. The wafer 3 rests on a bottom plate 6, which is typically a non-magnetic metal such as aluminum. The bottom plate 6 has a leaf spring 2 which is rigidly attached to the retainer 10 through a wall 29.
5, the wafer 3 is raised to face the bottom of the flange 21. The wafer 3 is further held in position by the action of the plunger 22 against a mechanical stop (not shown). The plunger 22 is provided with a spring, which allows the wafer 3 to be fixed to mechanical stops 23, 24.
(Figure 3).

In FIG. 1, a wafer 3 includes an inner conductive region 5 and an insulating layer 4. In FIG. Conductive region 5
includes any material that makes the carrier conductive. For purposes of the present invention, the term "conducting" is intended to apply to both good conductors, such as metals, and semiconductors, such as doped silicon.

In semiconductor engineering, the conductive region 5 is typically P-type silicon or N-type silicon. Insulating layer 4 is any non-conductive material. In semiconductor technology, the insulating layer 4 is typically silicon dioxide.

In FIG. 1, a discharge device 7 is configured to pass a current through an insulating layer to a conductive region 5 through the insulating layer.
any electrical device with sufficient voltage and energy to form an electrical connection to For typical silicon dioxide layers used in conventional semiconductor processing, voltages in the range of 2,000 volts to 20,000 volts are required to form electrical connections. Formation of the desired electrical connection is made from line 9 to line 8.
This is confirmed by measuring the resistance between the holder 10 and the surface of the wafer 3 at . Before the discharge takes place, the resistance measured between the lines 8, 9 due to the holder 10 and the wafer 3 is greater than 100×10 ⁶ ohms. After the discharge from the discharge device 7,
Electrical resistance is less than 1 x 10 ⁶ ohms, usually
It is on the order of between 10000 ohms and 50000 ohms.
Formation of an electrical connection, confirmed by a substantial reduction in resistance, is dependent on passing sufficient current through the insulating layer.

Although the exact nature of the phenomenon is not completely understood, the discharge from the discharge device 7 causes a conductive region 5 to flow from the conductive line 8 across the insulating layer 4 on the one hand.
An arc is created which leads to conductive region 5 on the other hand.
An arc is created across the insulation layer 4 to the metal retainer 10 which is in electrical contact with the insulation layer 4 or through a resist (not shown in FIG. 1). If the discharge device 7 supplies sufficient energy, the insulation layer will be destroyed by an arc across the insulation layer at at least two points.
This breakdown in the insulating layer provides an electrical connection. When viewed under a powerful microscope, electrical connections through the insulating layer appear as charred channels. This charred path is apparently caused by localized heating and high current density through the insulating layer, along which an arc discharge occurs across the insulating layer.

Whatever the phenomenon, the substantial reduction in resistance between the conductive region 5 and the holder 10 causes the electrons injected into the conductive region 5 by the electron beam to be removed in a manner described in more detail below. The retainer allows it to flow out.

In FIGS. 2 and 3, the retainer 1 in FIG.
A more detailed view of 0 is shown. Wafer 3 typically has a diameter D ₂ of 7.5 cm;
This diameter D ₂ is smaller than the diameter D ₃ of the opening defined by the annular wall 29 . The holder 10 supports an annular flange 21 defining an opening with a diameter D ₁ that is smaller than the wafer diameter D ₂ . The diameter D ₄ of the flange 21 is larger than the diameter D ₃ of the opening;
The flange 21 is thus partially supported by the surface of the cage 10. Cage 10 in FIG.
has a cutout on one side, which cutout is designed to be pressed against a post 18, which post 18 acts as a mechanical stop against one edge of the retainer 10. work. Two additional posts 18', 18'' are designed to act as mechanical stops to the other edge of the retainer 10.
The columns 18, 18' and 18'' in the figure represent the cage 10.
Rather, it is shown in dashed lines because it forms part of the retainer engagement means in the mechanism which will be described in more detail in connection with FIG.

In FIG. 3, a bottom view of the wafer and cage of FIG. 2 is shown. The wafer 3 has been edge milled along a crystal plane with direction 100 to define the edge 35 of the wafer. The edge 35 of the wafer 3 is positioned opposite a mechanical stop 23 which is rigidly connected to the flange 21 of the holder 10. The additional stop 24 is
It is also connected to the flange 21, and the stopper 2
It is located approximately 90 degrees from 3. A spring loaded plunger 22 holds the wafer in the stop 2.
3, 24 and are generally placed in the holder 10 in contact with the wafer to firmly hold the wafer in place.
The wafer 3 is further held in place by a spring 25. The spring 25 is pivotally connected to the retainer 10 by a bolt 26. The spring 25 can rotate around the bolt 26 towards the notch 12 and enter the recess 27, so that the wafer 3 and the bottom plate 6 can be easily inserted into and removed from the opening 2. be able to. 1st
The cage 10 and wafer 3 shown in the figure are cross-sectional views taken along the line -- in FIG. Similarly,
As will be described later, FIG. 6 is a partial sectional view of the semiconductor wafer and the holder taken along the line -- in FIG. 3.

In FIG. 4, one preferred embodiment of the discharge device of FIG. 1 is shown in more detail. The discharge device 7 is connected via a power switch 15 to a 60 Hz power supply at a terminal 50, and at the output of a conventional rectifier circuit 51 a positive rectified voltage of 6 volts and -
Both form a negative rectified voltage of 6 volts. The positive output at connection point 52 is connected to a 5 ohm current limiting resistor 31, a primary coil 32 and a momentary contact switch 1.
6, this momentary contact switch 16
is connected to the collector of switching transistor 34. switching transistor 3
4 is operated by an operational amplifier 38 to be switched between a conductive state and a cut-off state. Operational amplifier 38 switches its output at 60Hz +
Forms a V or -V step signal. The output from operational amplifier 38 is connected to the base of transistor 34 and switches transistor 34 into a conducting or blocking state at a rate of 60 Hz.

One pair from the primary coil 32 to the secondary coil 33
To achieve a voltage increase of 4000, the secondary coil 33 has more turns than the primary coil 32. The output of the secondary coil 33 is typically
More than 20,000 volts. The secondary loop connects switch 36, which is shown normally in the closed position, and the retainer and wafer mechanism, which is connected between wires 8 and 9 in the manner shown in FIG. Contains series connections.

In FIG. 4, line 9 from the wafer holder is connected to common ground. Discharge device 7 in Fig. 4
The primary and secondary loops are of the conventional type typically employed in automobile ignition systems as spark coils. Additionally, switch 36 can be switched to the dotted position to open the secondary loop and instead connect an ohmmeter across wires 8,9. switch 36
is thus switched and connects the ohmmeter,
The resistance between the holder 10 shown in FIG. 1 and the contacts on the surface of the semiconductor 3 can be easily measured.

Although the circuit of FIG. 4 is one preferred embodiment of a discharge device, it will be appreciated that any equivalent electrical circuit may be employed. An important characteristic is that the discharge device is capable of producing an output voltage of more than 20,000 volts and a driving current sufficient to cause dielectric breakdown.

In FIG. 5, the mechanism for holding the discharge device 7, wafer holder 10 and other components is shown. The mechanism includes a basic unit 11 which mechanically supports an ohmmeter 19, a momentary contact switch 16 and a power switch 15. Retainer 10
is a positioning post 18 that acts as a mechanical stop.
is placed opposite. The retainer 10 rests on the bottom plate 39 due to gravity and therefore
The electrical contact between 9 and retainer 10 is good.
Bottom plate 39 is electrically connected to a common ground shown in FIG. 4, which common ground is equal to lead 9 in FIG. Electrical and physical contact to the wafer 3 (not clearly shown in FIG. 5) is made by contact needles 13. The contact needle 13 is electrically connected via an insulating sleeve 14 and a wire 8 to the discharge device shown in FIGS. 1 and 4. The insulating sleeve 14 is firmly fixed to the lid 17. The lid 17 is typically a rigid plastic and is rotatable about the hinge 37 relative to the base unit 11 and retainer 10. When the lid 17 is closed in the down position as shown, the contact needle 13 is brought into firm contact with the surface of the wafer. When the lid 17 is rotated up around the hinge 37, the contact needle 13 is removed from contact with the wafer.

In FIG. 6, a more detailed view of a portion of a partially processed semiconductor wafer 3 mounted on a wafer 10, taken along the line ``--'' in FIG. 3, is shown. In FIG. 6, the wafer 3 is in firm mechanical contact with the flange 21 and the mechanical stops on the base plate 39 in the base unit 11. Furthermore, the contact needles 13 are in firm mechanical contact with the resist 49 on the upper surface of the wafer 3.

Wafer 3 of FIG. 6 includes numerous regions and layers typical of semiconductor devices formed using standard metal oxide semiconductor (NOS) processing techniques.

Briefly, MOS technology is a technology for forming active devices on the surface of a semiconductor substrate, such as conductive region 5 in FIG. The conductive region (substrate) 5 is typically about 7.5 cm in diameter and about 500 microns thick.
It is a shaped silicon wafer. The method of forming a MOS semiconductor is well known and is as follows. First, a silicon nitride layer with a thickness of about 1500 angstroms is formed on the surface of the substrate 5 by a well-known gas phase reaction method in which a mixed gas of monosilane and ammonia is passed through a reaction tube. The silicon nitride layer is then selectively etched using well known plasma etching techniques using a photoresist as a mask. After this selective etching, the photoresist is removed. The silicon nitride remaining on the surface of the substrate 5 is then used as a mask for the formation of the silicon dioxide layer 4. Silicon dioxide layer 4 is grown by thermal oxidation to a thickness of about 6000 angstroms. silicon dioxide layer 4
After formation, the silicon nitride is removed and the wafer substrate is placed in an oxidation furnace to re-grow approximately 500 Angstroms of oxide layer 45 on the substrate surface where silicon dioxide layer 4 is not present. A polycrystalline silicon layer is then formed to a thickness of about 400 angstroms by introducing monosilane into a conventional reaction tube.

To increase the conductivity of the polycrystalline silicon layer, the wafer is placed in an ion implantation system and phosphorus atoms are implanted.

After ion implantation, the polysilicon layer is etched by plasma etching to leave a polysilicon gate pattern 44. The wafer is then implanted with phosphorous ions using polysilicon gate 44 as an implantation mask to form N ⁺ source region 42 and N ⁺ drain region 43.
form.

After traditional ion implantation,
In order to distribute the implanted ions, it is necessary to anneal the implanted wafer. During annealing, polysilicon gate 44 is covered with a new oxide layer 46 due to annealing in an oxidizing atmosphere.

Etching is then performed to remove the oxide layer over the source and drain regions 42, 43 to form the electrode window 48. An aluminum layer 47 is formed by vacuum deposition over the entire exposed surface of the wafer, including contacts through electrode windows 48 to source and drain regions 42,43.

At this point, electron beam resist 49 is applied over aluminum layer 47 to a thickness of about 1 micron by conventional spin coating. The resist 49 is typically a negative resist in the sense that the portions of the resist that are struck by the electron beam remain and the portions that are not struck by the electron beam are sequentially removed. A typical negative resist is a Copolymer (COP) resist, which is commercially available under license from Bell Laboratories. Of course,
Positive resists such as polymethyl methacrylate (PMMA) may also be employed in accordance with the present invention.

In FIG. 6, a cross-sectional view of only one active device region of the wafer is shown as representative of many other active device regions. A typical wafer, of course, contains many active device areas similar to those shown in FIG. In FIG. 6, the semiconductor wafer 3 has a P-type silicon region (conductive region).
5 is partially processed to the point where it is covered with a field oxide layer 41. ions were implanted
N ⁺ regions 42, 43 face each other in region 5 and form source and drain regions, respectively. The polysilicon gate layer 44 is a relatively thin thermally grown silicon dioxide layer 45.
and is covered by an overlying oxide layer 46. Aluminum layer 47 covers the entire surface of wafer 3 and is in contact with source region 42 and drain region 43 via electrode window 48 .

According to the invention, a wafer 3 partially processed in the above-described or similar process is shown in FIGS. 1 and 2.
It is disposed within wafer holder 10 of FIG. 6 in contact with metal flange 21 and metal post 23, as previously described and shown in connection with the figures. The wafer holder 10 and the partially processed wafer 3 are then placed on the discharge device 11 as described in connection with FIG. For a wafer holder located on the top surface of the discharge device, the holder 10
It rests on a bottom plate 39 placed opposite to 8. The lid 17 is closed and the contact needle 13 of FIG. 5 is brought into contact with the resist layer 49 as shown in FIG. In this state, the discharge device 7
(Figs. 1 and 4), and the contact needle 1
3 makes electrical contact to the wafer on the other side of the discharge device. With the wafer and wafer holder thus positioned in the apparatus of FIG. 5, switches 15, 16 are closed and a high voltage discharge is produced from discharge device 7 of FIGS. 1 and 4.

The electrical discharge applied to the wafer and holder of FIG. 6 forms an electrical connection 61 between contact needle 13 and aluminum layer 47. Additionally, one or more electrical connections 62 , 63 or 64 connect conductive region 5 , aluminum layer 47 , post 23 and flange 21 to retainer 10 . In the embodiment of FIG.
Electrical connection 6 between aluminum layer 47 and flange 21 through resist layer 49 which is an insulating layer
4 is shown. Furthermore, an electrical connection 62 between the aluminum layer 47 and the conductive region 5 through the silicon dioxide layer 41 is shown. Additionally, electrical connections 63 are shown extending through the silicon dioxide insulating layer 4 and a portion of the resist layer 49 to the metal pillars 23. Although the location of the electrical connections to the aluminum layer 47 can be easily verified, the electrical connections 6
The positions of 2, 63 and 64 are not easy to visually ascertain without considerable difficulty. The presence of electrical connections 62, 63 and 64 is readily verified by use of ohmmeter 19 as described above in connection with FIG. Furthermore, the presence of an electrical connection is also confirmed by the absence of unwanted deflections of the electron beam due to electrostatic fields.

In many cases, an electrical connection 63 in the form of a conductive channel between the conductive region 5 and the post 23 is easily formed as a result of the output from the discharge device. As a result of the foregoing processing steps, electrical connections 6
As a result of pressing the wafer hard against the pillars 23 in the area indicated by 3, the oxide layer on the wall is formed irregularly, so that conductive channels forming electrical connections 63 often occur. Since the phenomenon that gives rise to conductive channels is believed to be the result of the electrical current and heat formed after arcing between conductive regions on either side of the insulator,
It is believed that the actual location of the conductive channel formed will occur where the electrical impedance is lowest (often where the insulation is thinnest).

To create an electrical connection with a series resistance of less than 1×10 ⁶ ohms, one or more discharges caused by momentarily activating switch 16 are required. To confirm low resistance, switch 36 is turned on to connect to meter 19, as shown in FIG. 4, and the series resistance is measured to confirm that this resistance is sufficiently low. As used herein and in the drawings, the terms "electrical connection" and "conductive channel" each refer to any connection through an insulator that has a series resistance of substantially less than 100 x 10 ⁶ ohms. Of course, the lower the resistance of the electrical connection in the conductive channel, the more electrons injected during electron beam processing will escape. The greater the resistance of the electrical connection in the conductive channel, the more charge will be retained and therefore the greater the electron beam deflection error caused by the charge.

In a typical example, the electron beam current is
10 ^-7 amperes. In semiconductor processing of the type described herein, if the series resistance of the electrical connection is about 1×10 ⁶ ohms, the residual voltage created by the stored charge is about 0.1 volt. This 0.1
The voltage in volts is approximately 0.015 in the incident electron beam
This resulted in micron positional deviation errors. If such small deviation errors, such as 0.015 microns, are tolerated, a voltage of 0.1 volt is tolerated, and therefore an electrical connection of 1×10 ⁶ ohms is tolerated.

After applying a discharge to the wafer 3 of FIG. 6 to form an electrical connection, the holder 10 and the electrically connected wafer 3 are placed in an electron beam apparatus and exposed using any desired electron beam pattern. be done. Because electrical connections are present from the conductive regions (ie, aluminum layer 47 and semiconductor substrate 5), excessive charge accumulation does not occur and the electron beam exposure is performed with a positional accuracy of better than 0.1 micron.
After exposure, the wafer of FIG. 6 is removed from holder 10 for subsequent conventional semiconductor processing. The unexposed areas of the e-beam resist are dissolved and removed in a conventional solvent. The thus exposed aluminum layer is then etched away by conventional etching to form electrodes and other interconnections that correspond to the unremoved portions of the aluminum layer 47. If additional steps are then utilized, including electron beam resist application, the method and apparatus of the present invention is employed to create a discharge across the wafer and wafer holder after the resist has been applied. Thus, an electrical connection between the wafer and the holder having a conductive channel with a resistance of less than 1×10 ⁶ ohms is formed before each exposure of the electron beam.

In FIG. 7, the wafer holder 10 and the electrically connected wafer 3 are placed in an electron beam apparatus, as seen along the line -- in FIG. The electron beam apparatus has an electron beam source 65 located above the surfaces of the wafer 3 and the holder 10.
The wafer 3 and the holder 10 are placed on a table 66, and this table 66 emits an electron beam 60.
is movable in a plane perpendicular to the direction of incidence. After the wafer 3 has been processed and electrical contact has been made according to the invention, an electron beam 6 from an electron beam source 65 is emitted.
0 is incident on point 67 on the surface of wafer 3. When the wafer and holder are processed according to the present invention, the position of point 67 is within a position error of less than 0.1 micron. The electrons colliding onto the surface of the wafer 3 are caused by the energy of the electron beam.
The insulating layer 4 is crossed into the implanted conductive region 5 . However, the electrons accumulated in the conductive region 5 escape, for example through a conductive channel 64, into the metal flange 21, the rest of the holder 10 and the metal table 66 of the electron beam device. The charge from the conductive region 5 is thus discharged to a very large ground plane.

In the absence of an electrical connection according to the invention, charge is accumulated in the conductive region 5. This charge is generally evenly distributed within the conductive region 5. The uniformly distributed charges in the conductive region 5 form equipotential lines 69 according to well-known principles. This accumulated charge causes the incident electron beam 60 to pass through an equipotential field and cause the incident electron beam 60 to pass through a point 68 on the surface of the wafer 3.
tends to be deflected so that it is incident on the The displacement d1 of point 68 from desired point 67 is greater than 15 microns, thereby substantially not achieving the desired accuracy when exposing the wafer with the electron beam.

In FIG. 7, table 66 is movable relative to electron beam source 65. In FIG. A second relative position relative to the electron beam source 65' is shown in which the table 66 has been moved to move the holder 10 and wafer 3. The electron beam source 65' forms an electron beam 60' which, according to the invention, is incident on the surface of the wafer 3 at a point 67'. In the absence of electrical connections according to the invention, electron beam 60' tends to be deflected from the approximate center of wafer 3 to point 68'. Point 68' is deflected from desired point 67' by a displacement d2, and this displacement d
2 reaches 15 microns or more. In Figure 7,
It should be noted that electron beam source 65 is relatively farther from the center of wafer 3 than electron beam source 65'. Therefore, displacement d1 for electron beams farther from the center tends to be larger than displacement d2 for electron beams closer to the center of the wafer. Beam displacement as a function of the position of table 66 in a plane perpendicular to the incident electron beam tends to be a nonlinear function that is a function of the strength of the electric field created by the accumulated charge. Since the wafer 3 is surrounded by the metal of the flange 21 and the remaining metal of the holder 10, the equipotential lines tend to be somewhat distorted. For this reason, it is preferable to eliminate or substantially reduce the accumulated charge, rather than attempting to compensate for the deformation by appropriately adjusting the position of the table. Furthermore,
The displacements d1 and d are such that the charge accumulated in the conductive region 5 becomes very large and causes arcing, for example, on the flange 21.
2 may be repeated unnecessarily. Since the discharge caused by such accumulated charge does not form a suitable conductive channel, the charge would otherwise accumulate again. Therefore, unless charge is drained by the method and apparatus of the present invention, charge accumulation tends to occur in a somewhat random and unpredictable manner.

Although the invention has been described in connection with one MOS processing technology, many other semiconductor and other processing technologies may be advantageous with the invention. For example, lift-off electron beam semiconductor technology may also be readily useful in accordance with the present invention. In lift-off electron beam technology, an electron beam resist is applied to the surface of a silicon wafer. The electron beam resist is applied over thermally grown silicon dioxide and silicon nitride layers formed in a conventional manner, such as by the process steps described above. Unlike the example discussed in connection with FIG. 6, the above structure does not have an aluminum layer (such as layer 47 in FIG. 6). After the electron beam resist has been applied, the wafer is placed in a holder 10, and both the holder and wafer are placed in the base unit 11 of FIG. A discharge is applied to form an electrical connection through the silicon nitride in a conductive channel between the silicon substrate and the silicon dioxide layer. The apparatus of FIG. 5 is again employed to test the wafer and holder to ensure that the electrical connections in the conductive channels have a series resistance of less than ^{1.times.10.sup.6} ohms. After this, the wafer and holder are both placed in an electron beam apparatus of the type shown in connection with FIG. 7 for the purpose of performing electron beam exposure of the electron beam resist. The electron beam can again be positioned on the surface of the wafer with an accuracy of better than 0.1 micron. After exposure, the wafer is removed from the holder and the e-beam resist is developed in a conventional manner. After this, the partially processed wafer is exposed to an electron beam.
A suitable metal is deposited over the entire surface of the resist layer. Lift-off is then accomplished by dissolving or etching the electron beam resist to leave the desired metal pattern on the surface of the silicon nitride layer.

From the foregoing, it can be seen that the discharge method and apparatus of the present invention are applicable to all types of discharges in which a charged particle beam is utilized to expose a wafer or other substrate containing a conductive region covered by an insulating layer. It is clear that the invention is relatively easy and well suited for use in processing processes.

Although the invention has been particularly described and shown with respect to preferred embodiments thereof, it will be understood by those skilled in the art that changes may be made in form and detail without departing from the spirit and scope of the invention. Dew.

[Brief explanation of the drawing]

1 is a partial electrical and mechanical schematic diagram of an apparatus according to the invention; FIG. 2 is a reduced plan view of a wafer holder and a wafer of the type used in the apparatus of FIG. 1; and FIG. 2 is a reduced bottom view of a wafer holder and a wafer, FIG. 4 is a schematic electrical circuit diagram of a discharge device according to the invention, and FIG. 5 is a diagram showing a discharge device, a wafer holder and other elements according to the invention A front view of the mechanism according to the present invention, FIG.
FIG. 7 is a schematic diagram of a wafer holder being exposed in an electron beam apparatus according to the present invention; FIG. 2... Opening, 3... Surface of semiconductor wafer, 4... Insulating layer, 5... Conductive region, 6... Bottom plate, 7... Discharge device, 8, 9... Lead wire, 10... Holder, 11... Basic unit, 12... Notch, 13...Contact needle, 1
5...Power switch, 16...Momentary contact switch, 1
7... Lid, 18, 18', 18''... Pillar, 19... Ohmmeter, 21... Flange, 22... Plunger, 2
3, 24... Mechanical stopper, 25... Leaf spring, 26...
Bolt, 27... recess, 28... upper surface of retainer, 29
...Inner wall, 31... Current limiting resistor, 32... Primary side coil, 33... Secondary side coil, 34... Switching transistor, 35... Edge of wafer, 37... Chiyo-pair, 38... Operational amplifier, 39... Bottom plate, 41...
Field oxide layer, 42...N ⁺ source region, 43
...N ⁺ drain region, 44 ... polycrystalline silicon gate, 46 ... oxide layer, 47 ... aluminum layer, 48
...electrode window, 49...resist, 51...rectifier circuit, 6
0,60'... Electron beam, 65,65'... Electron beam source, 66... Table, 67, 68... Point on the surface of the wafer, 69... Equipotential line.

Claims (1)

Claims: 1. A semiconductor wafer comprising the steps of: 1 coating a conductive region of the semiconductor wafer with an insulating layer, forming a resist layer on the insulating layer, and then engaging the wafer with a conductive wafer holder. In the processing method, after the step of engaging the wafer with the holder,
A semiconductor comprising the step of applying a voltage between the wafer and the holder to form an electrical connection path through the insulating layer between the conductive region and the wafer holder. How to process wafers. 2. The method of processing a semiconductor wafer according to claim 1, wherein the resist layer is formed of an electron beam resist. 3. A method for processing a semiconductor wafer, comprising the steps of: coating a conductive region of a semiconductor wafer with an insulating layer; forming a resist layer on the insulating layer; and then engaging the wafer with a conductive wafer holder. After engaging the wafer with the retainer,
applying a voltage between the wafer and the holder to form an electrical connection through the insulating layer between the conductive region and the wafer holder;
and a step of exposing the resist layer to an electron beam in an electron beam device and conducting a current generated by the electron beam to the electrical connection path. . 4. The method of processing a semiconductor wafer according to claim 3, wherein the resist layer is formed of an electron beam resist. 5. A method of processing a semiconductor wafer forming an electrical connection through an insulating layer covering a conductive region of the semiconductor wafer, the method comprising: a conductive holder mechanically engaging the semiconductor wafer; a discharge device comprising a needle in contact with a surface; and applying a voltage pulse between the needle and the retainer to connect the retainer and the conductive region when the needle is in contact with the surface; 1. A semiconductor wafer processing apparatus, comprising: means for permanently creating an electrical connection between the semiconductor wafers.