JPS61290554A - Channel device - Google Patents

Abstract

PURPOSE:To prevent a fact that a data transfer becomes impossible whenever a page address is switched, by adding tag information corresponding to the existence of a skip designation by a channel command word, when writing a real address to a RAM. CONSTITUTION:A read page address provided with a skip TAG is written in a DAT-RAM 19 for storing the result of the address conversion of a microcomputer 11, it is read out, and when a write data and a read-out data are compared, for instance, the dissidence is detected. In this case, the computer 11 decides that the DAT-RAM 19 is faulty, resets a transfer permission FF 24, and its output is transferred as a data transfer inhibiting command to a DMA controlling circuit 25. As a result, the DMA controlling circuit 25 stops a data transfer. As a result, a main memory device 30 is brought to an access by using a wrong real page address which is read out of the DAT-RAM 19, that is to say, a wrong data transfer is executed, and the storage area of the main memory device 30 is prevented from being broken down.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a virtual memory computer system, and in particular to a channel including a channel command word specifying a skip operation in data transfer from an input/output device to main memory. The present invention relates to a channel device suitable for executing programs.

[Technical background of the invention and its problems] This type of channel device converts a virtual address into a real address by referring to an address conversion table in main memory for input/output transfer control specified in a channel program. Perform the conversion. This address conversion is executed by a microcomputer in the channel device, and generally the channel D A T (D VnaliCA
ddress Translation).

However, with conventional channel devices, when a high-speed input/output device such as a magnetic disk device is connected to the device, the microcomputer in the channel device performs address conversion every time the page address changes. There was a problem in that data transfer was impossible every time the address was switched.

Now, the channel command words included in the channel program (Channel Com5 and Word:
A skip operation in data transfer from an input/output device, such as a magnetic disk device, to the main memory may be specified by a group of CCWs (hereinafter referred to as CCW). Now, this type of channel program specifies a first CCW that specifies data transfer of a first amount of data and that data following the transfer data specified by this first CCW is to be skipped by a second amount of data. It is assumed that the third CCW includes a second CCW and a third CCW that specifies that data following the skip data specified by the second CCW is transferred by a third amount of data. In this case, the conventional channel device
After the first amount of data is transferred by outputting a seek command to the magnetic disk device when executing
Skip designation is determined by CW, and based on this determination, the third C
When the CW is executed, a seek command is output to the magnetic disk device again to transfer the third amount of data. Note that when outputting a seek command after skipping, the bulk address is calculated taking the skipped amount into consideration.

As described above, in conventional channel devices, when executing a channel program with a skip specification, a seek operation to the data transfer restart track is specified by issuing a seek command when data is transferred after skipping, and the corresponding C
In order to execute the data transfer indicated by the CW, there is a problem in that the head of the magnetic disk has passed the target sector at the time of execution of the CCW, and the data transfer cannot be started unless it rotates once.

[Object of the Invention] An object of the present invention is to provide a channel device that can prevent data transfer from becoming impossible every time a page address is switched in a virtual memory computer system.

Another object of the present invention is to provide a channel device that can prevent the occurrence of a long period of time due to rotation of a magnetic disk device during data transfer with skip designation (scatter gathering).

[Summary of the Invention] This invention provides an RA that stores multiple pages of real page addresses to which tag information indicating whether or not main memory writing has been performed.
M and an address conversion means for converting virtual addresses into real addresses for the number of pages required for data transfer specified by the channel program, and write the real page address obtained by the address conversion means to the RAM. I try to keep it that way. At this time, tag information is added to the real address written in the RAM depending on whether skip is specified in the corresponding channel command word in the channel program.

The address of the RAM is indicated by the first predetermined pit below the page address part of the virtual address for data transfer indicated by the address counter, or for writing the real page address (to which tag information is added) to the RAM. This is indicated by the output of a selector that selects either the lower second location or the fixed pit of the page address portion of the virtual address. The real page address read from the RAM when the first predetermined pit is selected by the selector is concatenated with the intra-page offset of the virtual address indicated by the address counter to generate a real address for the main memory. At this time, the output of the memory request signal is prohibited depending on the tag information read from the RAM (along with the real page address), and the corresponding data transfer is skipped.

[Embodiment of the Invention] FIG. 1 shows the peripheral configuration of a channel device 10 according to an embodiment of the present invention, and 11 is a microcomputer that controls the entire channel device 10. As shown in FIG.

The microcomputer 11 is the microcomputer 1
The microprocessor 1 has a central microprocessor, a ROM in which various microprograms are stored, and an internal RAM (none of which are shown) that is a work memory for the microprocessor. When an input/output start command is issued from a CPU (not shown), the microcomputer 11 takes out a group of CCW (channel command words) (ie, a channel program) from the area of the main storage device 30 indicated by the command from the beginning.

At this time, the address (real address) for the main memory device 30 is set in the address register 13 by the microcomputer 11 via the internal bus 12 of the computer 11, and from the register 13 to the driver 14 via the system bus 31. The data is supplied to the storage device 30. Further, the CCWs sequentially taken out from the main storage device 30 are latched into the data register 16 via the system bus 31 and the receiver 15, and then taken into the microcomputer 11 via the internal bus 12. This data register 16 is used for inputting and outputting control data between the channel device 10 and the main storage device 30, such as inputting the above-mentioned CCW and further inputting a real page address to be described later. Further, the address register 13 is used for setting addresses for the above-mentioned input/output.

When the microcomputer 11 takes in the CCW, it stores it in the internal RAM each time. The microcomputer 11 then performs the input/output control shown in the flowcharts of FIGS. 2(a) and 2(b) according to the group of CCWs (ie, channel program) stored in the internal RAM. The CCW applied in this embodiment consists of a count field (16 pits), a flag field (8 bits), a command field (8 bits) and a data address field (32 pits), as shown in FIG. The command field is used to specify operations (seek, read, write, etc.), and the flag field is used to specify the command chain,
It is used to specify data chains, skip chains, etc. by bit correspondence. The data address field is used to indicate the start address (virtual address) of the area of the main storage device 30 required for the operation specified by the command field, and the count field is used to indicate the data size of the same area. .

Now, the microcomputer 11 internally stores the group of CCWs, that is, the channel program, taken in from the main memory 30.
When the data is stored in the AM, data transfer preparations are first made to perform the data transfer specified by the same channel program (step 310). In this embodiment, the channel program includes CCW1 to CCW3 that specify a read operation (from the magnetic disk device 40) as shown in FIG.
Contains. Further, in the flag fields of CCW1 and CCW2, a data chain and a skip chain are respectively designated. In the case of a channel program including the CCW group shown in the fourth factor, the microcomputer 11 transfers Ill
C to the address counter 18 in the 7th part of the III counter section 1.
A predetermined field of data address 1 (which is the transfer start virtual address to the main storage device 30) specified by the data address field of CWl is initialized. Further, the microcomputer 11 sets a size counter (not shown) in the transfer control counter section 17 to count 1 < sum of 3 (count 1 + count 2 + count 3) Initialize. As shown in FIG. 5, a virtual address such as data address 1 consists of a 21-bit page address and 32 bits of an 11-pit in-page offset, and the predetermined field is the lower 14 pits of the virtual address, that is, the page address. lower 3 of address
Bits and offsets. However, in this embodiment, the upper three bits of the predetermined field of the transfer start virtual address initialized in the address counter 18, that is, the lower three bits of the page address, are all set to 0'' regardless of the actual value.This will be explained later. This is to simplify control over the DAT-RAM 19.

When the microcomputer 11 prepares for data transfer in step S10, it refers to an address conversion table (not shown) placed on the main storage device 30 and determines the transfer start virtual address (in this example, data address 1).
) is converted into a real page address as shown in Figure 6 (Step 5).
12). At this time, the address (actual address) for referring to the address conversion table is supplied to the main storage device 30 via the address register 13, as in the case of CCW extraction. In addition, the address conversion result, that is, the main memory 30
The real page address taken out from the address conversion table is taken into the microcomputer 11 via the data register 16.

Now, the channel device 10 in FIG. 1 is provided with a RAM (hereinafter referred to as DAT-RAfVI) 19 that stores, for example, a maximum of eight address conversion results of the microcomputer 11. When the microcomputer 11 obtains the real page address of the first page address through address conversion in step 812, it writes the same address into the DAT-RAM 19 as described below.

The DAT-RAM 19 has an address port A1, a data input port DI, and a data output port Do.

Address port A of DAT-RAM19 has a selector (
The output port of S'EL) 21 is connected. The 1H side input port of selector 21 is microcomputer 1.
It is connected to the internal bus 12 so as to receive the lower three pits of the page address (virtual address) output from "
The 0'' side input port is connected to the address counter 18 so as to receive the upper three pits (that is, the lower three pits of the page address) of the information indicated by the address counter 18.The microcomputer 11 transfers the real page to the DAT-RAM 19 When writing the address, the selector 21 is switched to the "1" side (step 514).

Next, the microcomputer 11 stores the DAT-RAM 19
The 3-pit all "O" data (that is, the same data as the upper 3 pits of the information set in the address counter 18 in step 81G) is sent to "1" of the selector 21 via the internal bus 12. Supply to the side input port. At this time, microcomputer 1
1 transfers the real page address obtained by address conversion (in this example, the real page address corresponding to the first page) along with 1-bit tag information (hereinafter referred to as skip TAG) to the data in the DAT-RAM 19 via the internal bus 12. input port DI, and sets DAT-RAM 19 to write mode. This skip TAG indicates whether the page indicated by the real page address to which the same TAG is attached is specified to be skipped (in the case of "0") or not (in the case of "1").
That is, it indicates whether or not there is writing to the main storage device 30). Therefore, the skip TAG corresponding to the first page is CCWl
This is “1” because skip is not specified in .

The 3-pit RAM address from the microcomputer 11 is selected by the selector 21 and transferred to the DAT-RAM.
19 address port A. As a result, the address of the DAT-RAM 19 specified by the microcomputer 11 (in this example, address 0) is transferred from the microcomputer 11 to the real page address with skip TAG (in this example, the real page address corresponding to the first page). )
is written (step 816).

The microcomputer 11 inputs the DAT- in step 81B.
When a real page address with skip TAG is written to the RAM 19, the written data is read (
step 818). For this purpose, microcomputer 1
1, while keeping the RAM address for DAT-RAM 19 at the time of writing in step 318.
Switch T-RAM 19 to read mode. However, the DAT-RAM 19 was written in step 81B.
The data at that address (in this example, address O) is read from the data output port Do.

DAT-RAM 1917) Data output port Do is connected to internal bus 12 via gate 22 and to the real base address field of address register 23 which holds real addresses. This address register 23 is used to indicate a real address for the main storage device 30 in data transfer between an input/output device connected to the channel device 10, such as a magnetic disk device 40, and the main storage device 30. Further, the offset field of the address register 23 is connected to the address counter 18 so as to receive the intra-page offset of the information indicated by the address counter 18.

When performing the reading in step 818, the microcomputer 11 sets the gate 22 to an output enable state and prohibits the latching operation of the address register 23. As a result, the read data from the DAT-RAM 19 is outputted to the internal bus 12 by the gate 22 and guided to the microcomputer 11.

The microcomputer 11 internally takes in the data on the internal bus 12 (ie, the read data from the DAT-RAM 19) for comparison with the write data used in step 816 (step 520). At this time, the microcomputer 11 switches the selector 21 to the a On side.

When the microcomputer 11 takes in read data from the DAT-RAM 19, it responds to the same successive data.
Compare with the included data to see if both data match.
In other words, the real page address obtained by address conversion and the skip TAG added to the same address are DAT-R.
It is checked whether it is correctly written to AM19 (step 522). If they match, the microcomputer 11 determines that writing of the real page address with skip tag to the DAT-RAM 19 has been performed normally, and executes step 824. In this step S24, it is determined whether or not a transfer start has already been applied. If the transfer has not been started, the microcomputer 11 determines whether the writing in step 816 is the first writing (step 526). If it is the first write as in this example, the microcomputer 11 uses the magnetic disk device 40.
Issue a seek command to (step 828)
. As a result, the magnetic disk device 40 starts a seek operation. As is well known, this seek operation involves a mechanical operation and therefore takes a relatively long time. Therefore, while the magnetic disk device 40 is executing the seek operation, the microcomputer 11 performs step 312 of all the pages corresponding to the areas specified by CCW1 to CCW3.
Repeat the above address conversion for pages other than the page (first page) obtained in step 530).
The results are sequentially stored in the internal RAM of the microcomputer 11 along with the skip TAG (step 532).

In this case, since skip is specified in CCW2 among CCW1 to CCW3, a logical "O" skip TAG is added only to real page addresses corresponding to the number of pages indicated by count 2 in CCW2.

When step 832 is completed, the microcomputer 11
The operation returns to step 814. As a result, for the remaining skip TAG real page addresses (up to seven of them), processing including writing to the DAT-RAM 19 is performed in the same way as for the real page address corresponding to the first page.

However, the address from the microcomputer 11 to the DAT-RAM 19 is incremented by 1 for each write.

Furthermore, since this is the second and subsequent writing to the DAT-RAM 19, the determination at step 826 is No, unlike in the case of the real page address corresponding to the first page. In this case, the microcomputer 11 is a DAT-RAM.
19 is full (FULL) (step 534), and if it is not full, the internal RAM' (DA
It is determined whether unwritten data (unwritten real page address with skip TAG) (to the T-RAM 19) remains (step $36). If there is unwritten data, the operation of the microcomputer 11 returns to step 814. On the other hand, if the DAT-RAM 19 is full, or if there is no unwritten data even if the DAT-RAM 19 is not full, the microcomputer 11
is the real page address DAT-RA required for data transfer.
It is determined that writing to M19 has been completed. The microcomputer 11 then determines whether the seek operation of the magnetic disk device 40 has been completed (step 838).
Repeat until the seek operation is completed.

When the microcomputer 11 detects that the seek operation of the magnetic disk device 40 is completed in step 838, the microcomputer 11 sends CCW1 to CCW3 to the magnetic disk device 40.
The transfer is started by issuing a command specified by (in this example, a read command) and setting a transfer permission flip-flop (hereinafter referred to as transfer permission F/F) 24 that specifies transfer permission/prohibition (step 540).

Transfer permission F/F 24 set output is DMA
III m circuit 25. This allows D.M.
A ill 18 circuit 25 initiates control for DMA transfers between main memory 30 and data buffer 26 in channel device 10 . This data buffer 26 is connected to a magnetic disk device 40, and for example, in the case of a discrete device, read data from the magnetic disk device 40 is stored in the buffer 26. In this case, DM
When data of a predetermined size or more is stored in the data buffer 26, the A control circuit 25 starts reading data from the data buffer 26. In the case of discrete, the data read from the data buffer 26 is stored in the data register 21.
The data is latched and transferred from the register 21 to the main storage device 30 via the driver 28 and system bus 31. For each transfer of one word, the address counter 18 in the transfer control counter section 17 is incremented by 1, and the same is true (the size counter is incremented by -1).

Now, the upper three bits of the address counter 18, ie, the lower three bits of the page address, are supplied to the "0" side input of the selector 21. The selector 21 is DAT-RAM1
Except when writing the real page address with skip TAG to 9 (and when reading the write data following that write), the switch is made to select the large input on the "O" side, and the 3 bits from the address counter 18 are used as DAT- R
Selectively output to address port A of AM19. DAT-
The RAM 19 is set to read mode except when step 816 is executed. Therefore, after the transfer start is applied, the DAT-RA indicated by the 3 bits from the address counter 18 (lower 3 bits of the page address)
Data at address M19 (real page address with skip 'TAG) is read. On the first read,
In the initial state, the lower three bits of the page address set in the address counter 18 are all "
Since it is 0'', the data at address O in the DAT-RAM 19, ie, the real page address with skip TAG corresponding to the first page is read out.

The real page address of the data read from the DAT-RAM 19 by addressing the upper three bits of the address counter 18 is latched into the real address field of the address register 23. At this time, the offset field of the address register 23 contains the address counter 18.
The intra-page offset data indicated by the lower 11 bits of is latched. This operation is performed every time one word is transferred.

The contents of address register 23, i.e. DAT-RAM19
A real address obtained by concatenating the real page address from 1 and the intra-page offset data from the lower 11 bits of the address counter 18 is supplied to the main memory 30 via the driver 14 and the system bus 31.

Also, the skip TAG of the data read out from the DAT-RAM 19 by addressing the upper 3 bits of the address counter 18 is supplied to the AND gate (A>50). A memory request signal output from the DMA control circuit 25 is also supplied in synchronization with the AND gate 5.
0 is skip only when TAG is logic “1” D”M A
Passage of the memory request signal from the control circuit 25 is permitted. The memory request signal that has passed through the AND gate 50 is sent to the main storage device 30 via the system bus control circuit 51 that controls the system bus 31 and the system bus 31.
guided by. Therefore, skip TAG is logic “1”
In this case, from the address register 23 to the driver 14,
The area of the main memory device 30 indicated by the real address output via the system bus 31 is accessed (write access)
be done. On the other hand, when the skip TAG is at logic "0°", access (write access) to the main memory device 30 is prohibited regardless of data transfer under the control of the DMA III m circuit 25. In this example,
A skip TAG of logic "O" is added only to real page addresses corresponding to the number of pages indicated by CCW2 among ccwi to CCW3. Therefore, the DMA control circuit 25
Even if the data transfers specified by CW1 to CCW3 are executed continuously regardless of whether skip is specified or not, writing to the main storage device 13G is automatically prohibited during the period of data transfer specified by CCW2, and the DMAtAm circuit The correct skip operation is performed without CCW25 interrupting data transfer, ie, without issuing a seek command during CCW3 execution.

On the other hand, when the microcomputer 11 initiates a transfer in step 840, it detects the presence or absence of a transfer end interrupt from the DMA control circuit 25 (step 842).
If there is no end interrupt, it is determined whether a page switch has occurred (step 544).

This page switching is performed from the address counter 18 to the DAT-
This can be determined by switching the address indicated for RAM 19. If page switching has not occurred, the microcomputer 11 returns to step S42 to detect a transfer end interrupt.

Eventually, a page change occurs, and the microcomputer 11
When it is determined in step S44, it is determined whether unwritten data (to the DAT-RAM 19) remains in the internal RAM (step 846). If there is no unwritten data (real page address with skip TAG), the operation of the microcomputer 11 returns to step 842.

On the other hand, if there is unwritten data, the operation of the microcomputer 11 returns to step 814. This results in
Skip TA left in internal RAM (unwritten)
Regarding the first address of the real page address with G, D
Processing including writing to the AT-RAM 19 is performed in the same manner as in the above case. However, in this case, since the transfer has already been started, the determination at step 824 is YES. If the determination in step 824 is YES, the microcomputer 11 returns to the transfer end interrupt detection operation in step 842. That is, when a page switch occurs and unwritten data remains in the internal RAM, the microcomputer 11 requests data from the internal RAM during a seek operation (of the magnetic disk device 40), which was previously in an idle state. The DAT-RAM 19 is replenished with the real page address (with skip TAG) that was found. In this manner, in this embodiment, even if the page is switched, the necessary real page address is prepared in advance in the DAT-RAM 19, so that the real address can be generated without interrupting data transfer.

Now, assume that when a real page address with a skip tag is written in the DAT-RAM 19, the written data is read out, and the written data and read data are compared, a mismatch is detected. That is, the determination in step 822 is N.
It is assumed that the result is O.

In this case, the microcomputer 11 is DAT-RAM1.
Transfer permission F/F 24 is reset to stop data transfer (step 848).
). The reset output of the transfer permission F/F 24 is transmitted to the DMA control circuit 25 as a data transfer stop (prohibition) command. As a result, the DMA control circuit 25 stops data transfer. As a result, it is possible to prevent the main storage device 30 from being accessed using an incorrect real page address retrieved from the DAT-RAM 19, that is, from performing erroneous data transfer and destroying the storage area of the main memory bag W130. Ru.

Microcomputer 11 allows transfer F/F 24
When data transfer is stopped by resetting , the state returns to the state when receiving an input/output start command from CPLJ, and the operation in response to the command is restarted from the beginning (that is, from CCW reading). Furthermore, if the CCW group is saved in internal RAM,
It is also possible to start over from the data transfer preparation in step S10. Then, if such retries are repeated a predetermined number of times, it is determined that the channel device has failed.

In the above embodiment, the real page address corresponding to the first page is obtained before issuing the seek command and is written to the DAT-RAM 19 before issuing the same command. However, the real page address corresponding to the remaining pages and Similarly, the data may be written to the DAT-RAM 19 after issuing the seek command. Furthermore, it is not necessary to replenish the real page addresses in the DAT-RAM 19 every time a page is switched; for example, one or more real page addresses in the DAT-RAM 19 may be replenished when the number of real page addresses in the DAT-RAM 19 becomes less than a predetermined number. It's okay. Further, the present invention can be applied to both segment and page virtual storage systems.

[Effects of the Invention] According to the present invention, it is possible to prevent data transfer from becoming impossible every time a page address is switched.

Further, according to the present invention, when a skip-designated channel program is executed, the skip operation can be performed correctly without interrupting data transfer, so that it is possible to prevent the occurrence of waiting time such as rotation of the magnetic disk device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the peripheral configuration of a channel device according to an embodiment of the present invention, and FIG. 2(a) is a block diagram showing the peripheral configuration of a channel device according to an embodiment of the present invention. FIG. 5 is a diagram showing an example of a channel program, FIG. 5 is a diagram showing a virtual address format, and FIG. 6 is a diagram explaining address conversion. 10... Channel device, 11-... Microcomputer, 13, 23... Address register, 18... Address counter, 19... DAT-RA
M. 21... Selector (SEL), 24... Transfer permission flip 70 knob (transfer permission F/F), 30... Main storage device, 40... Magnetic disk device, 50... AND gate. (a) Figure s2 (b) Figure 2

Claims (1)

[Claims] In a virtual storage computer system equipped with a channel device that performs input/output control according to a channel program in main memory specified by an input/output start command from the CPU,
A RAM that stores multiple pages of real page addresses to which tag information indicating the presence or absence of main memory writing is added, and an address conversion that converts virtual addresses to real addresses for the number of pages required for data transfer specified by the channel program. an address converting means to be executed; and a writing means for adding tag information to the real page address obtained by the address converting means in accordance with the presence or absence of skip designation in the corresponding channel command word in the channel program, and writing the added tag information in the RAM. an address counter indicating a virtual address to the main memory for specified data transfer; and a lower first predetermined bit of the page address part of the virtual address indicated by this address counter, or writing to the RAM by the writing means. a selector that selects one of the lower second predetermined bits of the page address part of the virtual address indicated by as the address of the RAM;
an address register that holds a real address that is a combination of the real page address read from the RAM when the first predetermined bit is selected by the selector and the intra-page offset of the virtual address indicated by the address counter; A channel device comprising memory request inhibiting means for inhibiting output of a memory request signal in accordance with the tag information read from the RAM when the first predetermined bit is selected by the selector.