JPS61290553A - Channel device - Google Patents

Abstract

PURPOSE:To prevent a fact that a data transfer becomes impossible whenever a page address is switched, by switching a RAM means, in case of the dissidence of write and read-out data, when writing a real page address to a RAM means by a RAM designing means. CONSTITUTION:A real page address is written in a DAT-RAM 19 for storing the result of the address conversion of a microcomputer 11, it is read out, and when a write data and a read-out data are compared, for instance, the dissidence is detected. In this case, the computer 11 decides that the area 19-0 of the DAT- RAM 19 designated by a switching FF 20 is faulty, resets a transfer permission FF 24, and its output is transferred as a data transfer inhibiting command to a DMA controlling circuit 25. As a result, the circuit 25 stops transfer. When the computer 11 stops the data transfer by resetting the FF 24, the switching FF 20 is set, and the area of the DAT-RAM 19 is switched from the RAM area 19-0 to a RAM area 19-1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a virtual memory computer system, and more particularly to a channel device having an address conversion function for converting virtual addresses into real addresses.

[Technical Background of the Invention] This type of channel device performs address translation to convert a virtual address into a real address by referring to an address translation table in the main memory for input/output transfer control. This address conversion is executed by a microcomputer in the channel device, and generally the channel D A T (
Dynag+Ic AddressTrans
ration).

[Problems in the background art] However, in conventional channel devices, when a high-speed input/output device such as a magnetic disk device is connected to the device, the microcomputer in the channel device performs address conversion every time the page address changes. However, there was a problem in that data transfer was impossible every time the page address was switched.

[Object of the Invention] The object of the present invention is to provide a channel that can prevent data transfer from becoming impossible every time a page address is switched in a virtual memory computer system, and that does not cause erroneous data transfer. The goal is to provide equipment.

[Summary of the Invention] The present invention includes a pair of RAM means for storing real page addresses for a plurality of pages, a RAM designation means for designating one of the RAM means, and a virtual address converter for converting a virtual address into a real address. The real page address obtained by the address translation means is written into the RAM designated by the RAM designation means. At this time, reading is performed successively after writing, and it is checked whether the written data and the read data match. If they do not match, there is a possibility that the corresponding RAM means is out of order, so the RAM means designated by the RAM designation means is switched.

The address of the RAM means is the lower first predetermined bit of the page address part of the virtual address for data transfer indicated by the address counter, or the page address part of the virtual address indicated for continuous writing/reading to the RAM means. This is indicated by the output of a selector that selects one of the lower second predetermined bits. Then, when the first predetermined bit is selected by the selector, the main memory is stored using a real address that is a combination of the real page address read from the RAM means specified by the RAM specifying means and the intra-page offset of the virtual address indicated by the address counter. be accessed. On the other hand, when the second predetermined bit is selected by the selector, the real page address read from the RAM means designated by the RAM designation means becomes data to be detected for matching with the write data described above.

[Embodiment of the Invention] FIG. 1 shows a channel device 10 according to an embodiment of the invention.
11 shows a peripheral configuration of the channel device 10, where 11 is a microcomputer that controls the entire channel device 10.

The microcomputer 11 is the microcomputer 1
The microprocessor 1 has a central microprocessor, a ROM in which various microprograms are stored, and an internal RAM (none of which are shown) that is a work memory for the microprocessor. When the microcomputer 11 receives an input/output start command from the CPU (not shown), the microcomputer 11 reads the channel command! from the area of the main storage device 30 indicated by the command. ! ii
(ChannelCosgiandWord
: Hereinafter referred to as CCW) (hereinafter referred to as a channel program) is extracted from the beginning. At this time, the main storage device 3
The address (real address) for 0 is set in the address register 13 by the microcomputer 11 via the internal bus 12 of the computer 11, and
3 to the main storage device 30 via the driver 14 and the system bus 31. Further, the CCW taken out from the main storage device 130 is latched into the data register 16 via the system bus 31 and the receiver 15, and then taken into the microcomputer 11 via the internal bus 12. This data register 16 is used for inputting the above-mentioned CCW, as well as for inputting a real page address (described later), etc., as well as the channel device @10 and the main memory! It is used for inputting and outputting control data to and from 30. Further, the address register 13 is used for setting addresses for the above-mentioned input/output.

When the microcomputer 11 takes in the CCW, it stores it in the internal RAM each time. The microcomputer 11 then performs the input/output control shown in the flowcharts of FIGS. 2(a) and 2(b) according to the group of CCWs stored in the internal RAM.

First, the microcomputer 11 prepares for data transfer in order to perform the data transfer specified by the CCW (step 510). That is, the microcomputer 11 inputs CC to the address counter 18 in the transfer control counter section 17.
The transfer size (number of transfer words) is initialized in a size counter (not shown) in a predetermined field of the transfer start virtual address (to the main storage device 30) specified by W. The above virtual address is, as shown in Figure 3,
It consists of 32 bits: a 21-bit page address and an 11-bit intra-page offset, and the predetermined field is the lower 14 bits of the virtual address, that is, the lower 3 bits of the page address and the offset.

However, in this embodiment, the top three of the predetermined fields of the transfer start virtual address initially set in the address counter 18
The bits, ie, the lower three bits of the page address, are all set to "O" regardless of the actual value.

This is to simplify control of the DAT-RAM 19, which will be described later.

When the microcomputer 11 prepares for data transfer in step 810, it refers to an address conversion table (not shown) stored in the main storage device 30 and determines the page address (first page address) in the transfer start virtual address. ) into a real page address as shown in FIG. 4 (step 512). At this time, the address (actual address) for referring to the address conversion table is CC
As in the case of W extraction, the data is supplied to the main storage device 30 via the address register 13. Further, the address conversion result, that is, the real page address taken out from the address conversion table of the main storage device 30, is taken into the microcomputer 11 via the data register 16.

Now, the channel device 10 of FIG. 1 is provided with a RAM (hereinafter referred to as DAT-RAM) 19 for storing address conversion results of the microcomputer 11. When the microcomputer 11 obtains the real page address of the first page address by the address conversion in step 812, the microcomputer 11 stores the same address in the DAT-RAM 19 as described below.
Write to.

The DAT-RAM 19 is used by being divided into two parts: a RAM area 19-0 and a RAM area 19-1. RAM area 19-
0.19-4, for example, can store up to eight real page addresses. DAT-RAM19 is
It has an address boat A1, a data input boat DI, and a data output boat Do.

The address port A (4 bits) of the DAT-RAM 19 contains the output of the switching flip 70 (under LA, referred to as switching F/F) 20 that specifies switching of either one of the RAM areas 19-0.19-1. Q output) and the output port (3 bits) of the selector (SEL) 21 are connected. The output of switching F/F 20 is DAT-RA
Indicates the most significant bit of the address (4 bits) of M19,
The output of the selector 21 indicates the lower three bits of the same address. The “1” side input port of the selector 21 is connected to the internal bus 12 so as to receive the lower three bits of the page address (virtual address) output from the microcomputer 11, and the “O” side input port receives the lower three bits of the page address (virtual address) output from the microcomputer 11. It is connected to the counter 18 so as to receive the upper three bits of the information (ie, the lower three bits of the page address). Microcomputer 11 is DAT-RAM19
When writing the 6 real page address to
1'' side (step 514).

Next, the microcomputer 11 stores the DAT-RAM 19
All “0” data (that is, the same data as the upper three bits of the information set in the address counter 18 in step S10) is sent as the lower three bits of the address (RAM address) to the selector 21 as “1” via the internal bus 12.
The first page (address) is supplied to the side input boat.
The real page address corresponding to D is sent via the internal bus 12.
It is supplied to the data input port DI of AT-RAM19, and
Set AT-RAM2O to write mode. The 3-bit lower address from the microcomputer 11 is selected by the selector 21 and supplied to the lower field of address port A of the DAT-RAM 19. The upper field (most significant bit) of the same address port A is supplied with the Q output (“0” in the initial state) of the switching F/F 20. As a result, the address of the DAT-RAM 19 specified by the switching F/F 20 and the microcomputer 11 (in this example, address O, that is, the starting address of the RAM area 19-0) is assigned the real page address (in this example, the starting address) from the microcomputer 11. The real page address corresponding to the page is written (step 516).

The microcomputer 11 inputs DAT- in step 816.
When the real page address is written to the RAM 19, the written data is read (step $18).

For this purpose, the microcomputer 11 uses the DAT-RA
3-bit lower address for M19 in step 81
DAT-RAM with the same state as when writing in 6.
19 to read mode. However, step 81
The data at the address (in this example, address O) of the DAT-RAM 19 written in step 6 is read out from the data output port DO.

DAT-RAM19(F)7'-food output port Do is
connected to the internal bus 12 via the gate 22;
It is connected to the real page address field of the address register 23 that holds the real address. This address register 23 includes input/output devices connected to the channel device 10,
For example, in data transfer between the magnetic disk device 40 and the main storage device 30, it is used to indicate the real address for the main storage device 30. Further, the offset field of the address register 23 is connected to the address counter 18 so as to receive the intra-page offset of the information indicated by the address counter 18.

When performing the reading in step 818, the microcomputer 11 sets the gate 22 to an output enable state and prohibits the latching operation of the address register 23. As a result, the read data from the DAT-RAM 19 is outputted to the internal bus 12 by the gate 22 and guided to the microcomputer 11.

The microcomputer 11 internally takes in the data on the internal bus 12 (ie, the read data from the DAT-RAM 19) for comparison with the write data used in step S16 (step 520). At this time, the microcomputer 11 switches the selector 21 to the "O" side.

When the microcomputer 11 takes in the read data from the DAT-RAM 19, it compares the read data with the corresponding write data and checks whether the two data match or whether the real page address obtained by address conversion is DA.
It is checked whether the data is correctly written into the T-RAM 19 (step 522). If they match, the microcomputer 11 determines that the writing of the real page address to the DAT-RAM 19 has been performed normally, and executes step 824. In step 824, it is determined whether a transfer start has already been applied. If the transfer start has not been applied, the microcomputer 11 will write 1 in step 316.
At this time, it is determined whether or not it is the first writing (step 826). If it is the first write as in this example, the microcomputer 11 issues a seek command to the magnetic disk device 40 (step 828). As a result, the magnetic disk device 40 starts a seek operation.

As is well known, this seek operation involves a mechanical operation and therefore takes a relatively long time. Therefore, while the magnetic disk device 40' is performing a seek operation, the microcomputer 11 calculates the remaining addresses excluding the address obtained in step 812 among all real page addresses corresponding to the transfer area specified by the CCW. The address conversion for this purpose is repeatedly executed for the necessary pages (step 830), and the results are sequentially stored in the internal RAM of the microcomputer 11 (step 532).

When step 832 is completed, the microcomputer 11
The operation returns to step 814. As a result, for the remaining real page addresses (up to 7 of them), DAT
- Processing including writing to the RAM 19 is performed in the same way as for the real page address corresponding to the first page. However, the 3-bit lower address from the microcomputer 11 to the DAT-R''AM 19 is incremented by 1 for each write. Also, since this is the second and subsequent write to the DAT-RAM 19, the 3-bit lower address from the microcomputer 11 is incremented by one. The determination is NO as in the case of the real page address corresponding to the first page. In this case, the microcomputer 11 selects the DAT-RAM 19 specified by the switching F/F 20.
area (RAM area 19-0 in this example) is full (FL
ILL), and if it is not full, it is determined whether unwritten data (unwritten real page address) remains in the internal RAM (to DAT-RAM 19). (Step 836). If there is unwritten data, the microcomputer 11
The operation returns to step 814. On the other hand, DAT-RA1
If the DAT-RAM 19 is full, or if there is no unwritten data even if the DAT-RAM 19 is not full, the microcomputer 11 writes the DAT of the real page address necessary for data transfer.
- It is determined that writing to the RAM 19 has been completed. Then, the microcomputer 11 determines whether the seek operation of the magnetic disk device 40 is completed (step 8).
38) is repeated until the seek operation is completed.

When the microcomputer 11 detects that the seek operation of the magnetic disk device 40 is completed in step 838, it issues a command (read command or write command) specified by the CCW to the magnetic disk device 40, and also issues a transfer permission/write command to the magnetic disk device 40. Transfer is started by setting a transfer permission flip-flop (hereinafter referred to as transfer permission F/F) 24 that specifies prohibition (step 540).

The set output of the transfer permission F/F 24 is sent to the DMA control circuit 25.
transmitted to. As a result, the DMA control circuit 25 starts controlling DMA transfer between the main storage device 30 and the data buffer 26 in the channel device 10. This data buffer? 26 is connected to a magnetic disk device 40, and for example, in the case of a discrete device, read data from the magnetic disk device 40 is stored in the buffer 26. In this case, the DMA control circuit 25 controls the data buffer 2
When data of a predetermined size or more is stored in the data buffer 26, data reading from the data buffer 26 is started. In the case of discrete data, read data from the data buffer 2G is latched in the data register 27, and sent from the register 27 to the main storage device 3 via the driver 28 and system bus 31.
Transferred to 0. Then, each time one word is transferred, the address counter 18 in the transfer control counter section 11 is incremented by 1, and the size counter is similarly incremented by 1.

Now, the upper 3 bits of the address counter 18, that is, the lower 3 bits of the page address, are "0" of the selector 21.
supplied to the side input. Selector 2t is DAT-RAM
Except when writing the real page address to 19 (and when reading the write data following that write), the switch is switched to select the "O" side large input, and the 3 bits from the address counter 18 are transferred to the DAT-RAM 19. Selectively output to address port A. DAT-RAM19 is
The read mode is set except when step 816 is executed.

Therefore, after the transfer start is applied, the switching F
/F 20 Q output (“O” in this example) and 3 bits from address counter 18 (lower 3 of page address)
The data (actual page address) at the address of the DAT-RAM 19 indicated by the bit) is read out. In the first read, since the lower 3 bits of the page address set in the address counter 1B are all "0" as described above in the initial state, the data at address O of the DAT-RAM 19, that is, the actual data corresponding to the first page. The page address is read. The real page address read from the DAT-RAM 19 by addressing the upper 3 bits of the address counter 1B is latched into the real address field of the address register 23. Also address register 2
Intra-page offset data indicated by the lower 11 bits of the address counter 18 is latched in the offset field No. 3. This operation is performed every time one word is transferred. The contents of the address register 23, that is, the real page address from the DAT-RAM 19 and the lower 1 of the address counter 18
The real address concatenated with the intra-page offset data starting from 1 bit is supplied to the main storage device 30 via the driver 14 and the system path 31.

On the other hand, when the microcomputer 11 initiates a transfer in step 840, it detects the presence or absence of a transfer end interrupt from the DMA control circuit 25 (step 542).
If there is no end interrupt, it is determined whether a page switch has occurred (step 544).

This page switching is performed from the address counter 18 to the DAT-
This can be determined by switching the address indicated for the RAM 19. If page switching has not occurred, the microcomputer 11 returns to step 842 to detect a transfer end interrupt.

Eventually, a page change occurs, and the microcomputer 11
If it is determined in step 844, it is determined whether or not unwritten data (unwritten real page address) remains in the internal RAM (to the DAT-RAM 19) (step 846). If there is no unwritten real page address, the operation of the microcomputer 11 returns to step 842.

On the other hand, if there is an unwritten real page address, the operation of the microcomputer 11 returns to step 814.

This leaves the (unwritten) data in the internal RAM.
For the first address of the real page address, DAT-
Processing including writing to the RAM 19 is performed in the same manner as described above.

However, in this case, since the transfer has already been started, the determination at step 824 is YES. If the determination in step 824 is YES, the microcomputer 11 returns to the transfer end interrupt detection operation in step 842. That is, when a page switch occurs and an unwritten real page address remains in the internal RAM, the microcomputer 11 stores data in the internal RAM during a seek operation (of the magnetic disk device 40), which was previously in an idle state. The DAT-RAM 19 is supplemented with the obtained real page address. In this way, in this embodiment, even if the page is switched, the necessary real page address is stored in the DAT-RAM.
19, it is possible to generate a real address without interrupting data transfer.

Now, suppose that when a real page address is written into the DAT-RAM 19, the written data is read out, and the written data and read data are compared, a mismatch is detected. That is, it is assumed that the determination in step S22 is NO. In this case, the microcomputer 11 switches F/
The transfer permission F/F is used to determine a failure in the area r of the DAT-RAM 19 (in this example, RAM area 19-0) specified by F20, and to stop data transfer.
24 (step 848). Transfer permission F
The reset output of /F 24 is transmitted to the DMA III m1 circuit 25 as a data transfer stop (prohibition) command. As a result, the DMA control circuit 25 stops data transfer. As a result, it is possible to prevent the main storage device 30 from being accessed using an incorrect real page address read from the DAT-RAM 19, that is, from performing erroneous data transfer and destroying the storage area of the main storage device 30. Ru.

Microcomputer 11 allows transfer F/F 24
If you reset the data transfer and stop the data transfer, the switching F
/F 20 is set (step 550). As a result, the area of the DAT-RAM 19 is switched from the RAM area 19-0 to the RAM area 19-1. The microcomputer 11 then returns to the state it was in when it received the input/output start command from the CPU, and restarts the operation in response to the command from the beginning (that is, from reading the CCW). In addition, CC
If the group W is stored in the internal RAM, step S10
It is also possible to start over from data transfer preparation. If a discrepancy is detected in step S22 even with the above-mentioned retry, glue drying is performed again. In this case, RAM area 1 is
9-1 is used.

Of course, the state of the switching F/F 20 may be reversed in step S50, and the area of the DAT-RAM 19 may be switched at each retry. In this embodiment, if the above-mentioned connection attempt is repeated a predetermined number of times, it is determined that the channel device has failed.

In the above embodiment, the real page address corresponding to the first page is obtained before issuing the seek command and is written to the DAT-RA19 before issuing the same command. However, the real page address corresponding to the remaining pages and Similarly, the data may be written to the DAT-RAM 19 after issuing the seek command. Furthermore, it is not necessary to replenish the real page addresses in the DAT-RAM 19 every time a page is switched; for example, when the number of real page addresses in the DAT-RA and M19 falls below a predetermined number, one or more real page addresses are replenished. You can do it like this. Further, the present invention can be applied to both segment-based and page-based virtual storage systems.

[Effects of the Invention] According to the present invention, it is possible to prevent data transfer from becoming impossible every time a page address is switched, and there is no risk of causing erroneous data transfer.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the peripheral configuration of a channel device according to an embodiment of the present invention, and FIG. 2(a) is a block diagram showing the peripheral configuration of a channel device according to an embodiment of the present invention. (b) is a flowchart for explaining the operation, FIG. 3 is a diagram showing an example of the format of a virtual address, and FIG. 4 is a diagram for explaining address conversion. 10... Channel device, 11... Microcomputer, 13, 23... Address register, 18...
Address counter, 19...DAT-RAM, 19
-0.19-1...RAM area (RAM means), 20
...Switching flip 7O tube (switching F/F), 21
...Selector (SEL), 22...Gate, 24.
・Transfer permission flip-flop (transfer permission F/F), 3
0... Main storage device, 40... Magnetic disk device. Figure 2 (b) Figure 2

Claims (1)

[Claims] In a virtual storage computer system equipped with a channel device that performs input/output control according to a channel program in main memory specified by an input/output start command from the CPU,
A pair of RAMs that store multiple pages of real page addresses
RAM specifying means for specifying one of the pair of RAM means, and address conversion for converting virtual addresses into real addresses for the number of pages required for data transfer specified by the channel program. writing/reading means for sequentially writing the real page address obtained by the address conversion means into the RAM means and reading the written data; An address counter indicating a virtual address, and the first lower page address part of the virtual address indicated by this address counter.
The above R by a predetermined bit or the above writing/reading means.
a selector for selecting one of the lower second predetermined bits of the page address portion of the virtual address indicated for writing/reading to/from the AM means as part of the address of the RAM means; an address register that holds a real address obtained by concatenating the real page address read from the RAM means designated by the RAM designation means when a predetermined bit is selected and the intra-page offset of the virtual address indicated by the address counter; and a coincidence detection means for detecting a coincidence between the real page address read from the RAM means designated by the RAM designation means and the corresponding write data when the second predetermined bit is selected by the selector; If no match is detected by this match detection means, the above RA
A channel device comprising: means for switching the RAM means specified by the M specifying means.