JPS61272972A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PURPOSE:To realize the electrical effective channel length of a submicron region with excellent controllability, and to inhibit the generation of hot electrons by forming a first conduction type semiconductor layer at the central section in the channel length direction and second conduction type semiconductor layers on both sides of the first conduction type semiconductor layer. CONSTITUTION:A thermal oxide film 22 and an silicon nitride film 23 are formed onto a P-type Si substrate 21, a field oxide film 24 is shaped while using the film 23 as a mask, and the films 23, 22 are removed. A gate oxide film 25 is shaped, and the ions of B and As are implanted. A polycrystalline silicon layer 26 is deposited, and P ions are implanted and changed into an N type. The layer 26 and the film 25 are patterned. A patterned polycrystalline silicon layer 27 is irradiated by focus ion beams, and As ions are implanted in order to form a source, a drain and a diffusion layer. A P<+> type polycrystalline silicon layer 27a and N<+> type polycrystalline silicon layers 27b, 27c are shaped. N<+> type source-drain regions 28, 29 and an N-type diffusion layer 30 are formed simultaneously.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor device and its manufacturing method, and particularly improves the structure of a gate electrode. [Technical Background of the Invention and Problems thereof] Conventionally, MOS transistors are, for example, shown in FIG.
It is manufactured as shown in C).

First, a gate oxide film 2 and a polycrystalline silicon layer 3 are sequentially formed on a P-type (100) silicon substrate 1, and after death, a resist 4 is formed on the planned gate electrode formation line on the polycrystalline silicon layer 3 (see Fig. 3). (a) cause and effect).

Subsequently, using this resist 4 as a mask, the polycrystalline silicon layer 3 is selectively etched away by reactive ion bombardment (RIB) to form a gate electrode 5 made of polycrystalline silicon.

Next, the substrate IK is used as a 5″ft mask for this gate electrode.
Arsenic'I:'jJrJm Voltage 40 Ke Vl)"-
Ion implantation is performed under the conditions of -e ill 2X 10"/(MFL") to form an ion implantation layer 6t (Fig. 3(b)).
(Illustrated). Thereafter, in order to electrically activate the arsenic in the ion-implanted layer 6, annealing is performed in nitrogen at 1000° C. for 20 minutes, and the N-type source and drain regions 2.
form 8. Furthermore, P2O (P
phospho-8ilicate Glass) membrane 9
Then, a contact hole 10 is opened in the PSG film 9 and the gate oxide corresponding to the source and drain regions 7.8.
Then, an Ad pattern +w1 running on the P8G film is formed to form MO.
Manufacture an a-type transistor (as shown in Figure 3 (C)).

Incidentally, as the density of semiconductor integrated circuits increases in the future, the dimensions of date electrodes are becoming increasingly finer, and have recently reached the submicron region with a gate length of 1.0 μm or less. Therefore, according to the prior art, it is extremely difficult to form a pattern with good reproducibility and little variation in Lennost dimensions using photolithography. This will pose a problem in terms of the precision of gate electrode dimension processing in future micro[M08/LSIs]. Furthermore, as the gate length becomes smaller, the electric field near the drain of the MOS transistor becomes stronger, making it easier to generate hot electrons. As a result, these hot electrons are injected into the gate oxide film, deteriorating the transistor characteristics and reducing the reliability of the MOS transistor. Note that the above-mentioned problem becomes more likely to occur as L8I becomes larger and the gate length becomes submicron region.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is possible to realize the electrical effect channel length in the submicron region with good controllability, and to suppress the generation of hot electrons by relaxing the electric field near the drain. An object of the present invention is to provide a reliable semiconductor device and a method for manufacturing the same.

[Summary of the invention]

A first invention of the present application provides a $1 conductivity type semiconductor substrate, a second conductivity type source and drain region provided on the surface of the substrate, and a second conductivity type semiconductor substrate provided on the surface of the substrate and between the source and drain regions. a diffusion layer of conductivity type, a semiconductor layer of @1 conductivity type provided on the substrate via an insulating film, a semiconductor layer of @1 conductivity type in the center part in the channel length direction, and a semiconductor layer of the second conductivity type on both sides of this semiconductor layer in the channel length direction. a gate electrode having a semiconductor layer;
The semiconductor layer is provided with means for electrically connecting the semiconductor layer of the second conductivity type, and is intended to realize good controllability of the effective channel length and suppress generation of hot electrons.

The invention of Application 1g2 also includes a step of introducing a second conductivity type impurity into a first conductivity type semiconductor substrate, and a step of forming a second conductivity type semiconductor layer on the substrate via a gate oxide film. a step of introducing impurities of a second conductivity type into the substrate using this semiconductor layer as a mask; A step of forming a gate electrode together with a semiconductor layer of a second conductivity type, and activating the impurity introduced into the substrate by heat treatment and diffusing the second conductivity type into the source and drain regions of the second conductivity type and the amount deposited thereon. By comprising the step of forming a layer and the step of forming a means for electrically connecting the semiconductor layers of the @1 and second conductivity types, the same effect as the first invention of the present application can be obtained. .

[Embodiments of the invention]

Hereinafter, the case where the present invention is applied to the manufacture of an N-channel type MO8) transistor is shown in FIGS. 1(a) to (gl lr:
Refer to and explain.

[1] First, for example, a P-type (100) silicon substrate 2
1, a thermal oxide film 22 with a thickness of 100 OA and a thickness of 2500 Å
After forming the silicon nitride film 23t-, the silicon nitride film 23 in the area excluding the part where the element region is to be formed was removed (first
Figure (a) (not shown). Next, this silicon nitride p23'
After forming field oxidation P!J:24 as a mask and peeling off the silicon nitride film 23, the thermal oxide film 22 was removed.
After forming the gate oxidation Ill 25 t-, the poron was accelerated at a voltage of 8 to prevent punch-through in the same device region.
Q Key, dose amount 3 x 10"/call'
Ion implantation was performed under the following conditions. Thereafter, in order to control the threshold voltage of the channel region directly under the P-type gate electrode, which will be described later, arsenic was ion-implanted under the conditions of an acceleration voltage of 100 KeV and a dose of 2 x 10''/aI! (see Fig. 1(b)). ).

[2] Next, after depositing a polycrystalline silicon layer 26 with a thickness of 4000^ on the entire surface, phosphorus was accelerated at a voltage of 120 KeV.
, Ion implantation was performed at a dose of I x 101 m/cIIi. Subsequently, at 900°C in a nitrogen atmosphere,
Annealing was performed for 30 minutes to electrically activate the ion-implanted phosphorus atoms and uniformly diffuse them into the polycrystalline silicon layer 26 to make it N-type (FIG. 1(C), not shown).Next, photolithography technology was applied. And polycrystalline silicon layer 26, gate oxidation VIJ! by reactive ion etching technique. 2
In the channel length direction of the polycrystalline silicon layer 22, which has been subjected to single-turning, the polycrystalline silicon layer 22 has been subjected to single-turning.

In the area corresponding to the center, a beam diameter of 0.5μ corner y
Accelerating voltage 80KeV, dose @1x10/c1
) Focused ion beam irradiation was performed under the conditions of 1.

In this case, 1. Since the diameter of this beam is approximately equal to the effective channel length, it is possible to arbitrarily change the effective channel length in the submicron region by changing the beam diameter.

After that, arsenic was heated at an acceleration voltage of 40 KeV and a dose of 2X to form the source, drain regions, and diffusion layers.
Ion implantation was performed under the condition of 10''/- (Figure 1 (d1 not shown).

[3] Next, in order to activate the implanted poron and arsenic, and to prevent the poron in the polycrystalline silicon layer 27 from diffusing into the entire region of the polycrystalline silicon layer (the impurity diffusion layer in the polycrystalline silicon is In order to preserve the impurity distribution of the focused ion beam (faster than that in a single crystal), the tungsten lamp was used to maintain the impurity distribution of the focused ion beam.
A rapid thermal annealing was performed at ℃ for 10 seconds.

As a result, in the polycrystalline silicon layer 27, the region into which Ron ions were implanted by the focused ion beam becomes a P-type polycrystalline silicon layer 21a, and the regions on both sides thereof are N-type.
type polycrystalline silicon layers 27b and 27C. Note that these polycrystalline silicon layers 27a to 27c are collectively referred to as a gate electrode. At the same time, the element region includes N-type source and drain regions 28, 29, and these regions 28.
An N type diffusion layer 30 was formed between 29 and 29. Subsequently, a CVD-8i0z film 31 with a thickness of 3000 Å was deposited on the entire surface (Fig. 1 (e1 not shown).
A film 31t of OCV D -8+ O was etched and left on the side walls of the polycrystalline silicon layers 27b and 27C. Furthermore, titanium (Ti) is applied to the entire surface to a thickness of 100 mm.
0 A, 8 pieces, 650℃, 305+h in nitrogen atmosphere
I performed a silicidage depression. As a result, the source,
On drain region 28, 29 and polycrystalline silicon layer 27a
A titanium silicide layer 32 was formed on 27c. At this time, the CVD-5iO1 on the field oxide film 24 and
)1! Since there is no silicon on lJ l, titanium does not react. Thereafter, in order to remove unreacted titanium by etching, the titanium was etched using a mixed solution of ammonium fluoride and hydrogen peroxide.

Note that since the titanium silicide layer 32 is formed on the polycrystalline silicon layers 27a to 27c, the +N type polycrystalline silicon layers 27b and 27c are electrically connected to the P+ type polycrystalline silicon layer 21aFi. . Furthermore, the titanium silinide layer 32 remained on the source and drain regions 28 and 29 (as shown in FIG. 1(f)). Furthermore, a film 33t of PSG/8 i 0 with a thickness of 5000 Å is deposited on the entire surface, and the source and drain regions 28.2 are
A contact hole 34 was formed by opening a part of the PSG/SiO film 33 on top of the contact hole 9 and on the gate electrode, and an Al electrode 35 was formed in the contact hole 34 to manufacture an N-channel type M08 transosulfur. (Fig. 1 (gl) and Fig. 2 (gl)). Here, Fig. 2 is a cross-sectional view of Fig. 1 (g) enlarged in terms of parts.

The Nf Jarnel type MO8) Lansostar according to the present invention is 21
As shown in Figure (g), Ng source and drain regions 28.29 are provided on the surface of the element region of the P-type silicon substrate 21, and the source and drain regions 28.29 are provided on the surface of the element region.
An N-type diffusion layer 30 is provided between 9 and 9, and P-type and N-type polycrystalline silicon layers 2 are formed on the same element region via gate oxidation $25.
The structure has a structure in which a gate electrode consisting of 1a to 2 is provided, and a titanium silicide layer 32t is provided on the gate electrode and the source and drain regions 31. Therefore, according to the present invention, the following effects are achieved.

(2) The date structure of the N-channel MOa type transistor is as shown in FIG. That is, the surface of the channel region is rounded with an N-type diffusion N30, and the table of the channel region 4/4L [fJ (directly under the N-type polycrystalline silicon layer 21b, 2' IC) is the gate voltage Ov, It is a normally-on type transistor in which source and drain regions 28 and 29 are in an ON state. On the other hand, for the same reason, the surface of the channel region 4J (directly under the P-type polycrystalline silicon layer 271) is a normally-off transistor that does not turn on unless a certain positive gate voltage is applied. Therefore,
The electrical effective channel length is equal to the length of the channel region 4J, that is, the length L) of the P+ type polycrystalline silicon 77 layer 27m,
This length LLfi is almost equal to the diameter of the focused ion beam.However, since it is easy to narrow down the diameter of the focused ion beam to a submicron length, MO8) transistors with a submicron gate length can be used as a limiting factor. It is possible to realize it well.

■ Since the channel regions 41 to 43L/1N3j:j are formed, electrons, which are carriers, flow widely on the surface of the silicon substrate 21 and in the depth direction, so-called Burie.
It is a d-channel transistor. Therefore, the hot electron generation location is located relatively deeper than the surface of the substrate 21, suppressing injection of hot electrons into the gate oxide film 25, and suppressing deterioration of transistor characteristics. In addition, there is a high effective movement characteristic peculiar to the Burmu ED channel type.

In addition, the method of the present invention provides a polycrystalline silicon layer 27 which has been turned by poron using focused ion beam technology.
Ion implantation and rapid donor annealing are performed to make the center S of the polycrystalline silicon layer 22 in the channel length direction P-type, and both sides thereof are made N-type to form a gate electrode made of polycrystalline silicon. Since the process of FIG. 1U involves forming a titanium silinide layer 27 on the gate electrode, it is possible to realize an MO8) transistor with a submicron gate length as described above with good controllability, and also to inject hot electrons. can suppress deterioration of transistor characteristics.

In the above embodiment, a case was described in which titanium silicide was formed on the entire surface of the gate electrode as a means for electrically connecting P type and N type polycrystalline silicon/II. It is only necessary to electrically connect the polycrystalline silicon layers. In addition to titanium, high melting point metals such as tungsten, molybdenum, and platinum may be used as the metal material.

Further, in the above embodiment, the case where the present invention is applied to a Ny-Yarnel MOS transistor has been described, but the present invention is not limited to this, and the present invention can also be applied to a P-channel MO8 transistor as shown in FIG. In FIG. 5, 51 is an N type silicon substrate, 52 and 53 are P type source and drain regions, 54 is a P type diffusion layer, 55a is an N+ type polycrystalline silicon layer, 55b, 55CLliP+ type polycrystalline silicon layers are shown respectively.

〔Effect of the invention〕

As detailed above, according to the present invention, a conductor device and its manufacture are capable of realizing an effective electrical channel length in the submicron region with good controllability, suppressing the generation of hot electrons, and improving transistor characteristics. I can provide a method.

[Brief explanation of the drawing]

FIGS. 1(a) to (g) are cross-sectional views showing a method for manufacturing an N-channel MO8) transistor according to an embodiment of the present invention in the order of steps, and FIG. MO8) Schematic @ side view of transistor, Figure 3 +8) ~ (
C1 is a cross-sectional view showing a conventional N-channel MO8' transistor manufacturing method in order of steps, and FIG. 4 is a cross-sectional view of a P-channel MO8' transistor according to another embodiment of the present invention. 21... P type (100) silicon substrate, 22... Thermal oxidation@, 23... Silicon nitride film, 24... Field oxide film, 25... Gate oxide film, 26.21...
・Polycrystalline silicon layer, 27m, 55b, 56c...P
+ type polycrystalline silicon layer, 21b, 27c. 55a...N type polycrystalline silicon layer, 28.52...
- Source region, 29.53...Drain region, 30.
54... Diffusion layer, 31... CV D-ISiO,
1%, 32...Titanium silicide layer, 33...P8
G/8i01 film, 34... contact hole, 35.
...Alltm. Applicant's agent Patent attorney Takehiko Suzue $+1)
gewp4 Figure 1 ¥41 Figure 2v! l

Claims (4)

[Claims] (1) A semiconductor substrate of a first conductivity type, a source and drain region of a second conductivity type provided on the surface of this substrate, and a diffusion of a second conductivity type provided on the surface of the substrate and between the source and drain regions. layer, provided on the substrate via an insulating film,
a gate electrode having a semiconductor layer of a first conductivity type in a central part in the channel length direction and a semiconductor layer of a second conductivity type on both sides of the semiconductor layer in the channel length direction; and semiconductors of the first and second conductivity types. 1. A semiconductor device comprising: means for electrically connecting layers. (2) The gate electrode is comprised of a first conductivity type polycrystalline silicon layer and a second conductivity type polycrystalline silicon layer on both sides of the polycrystalline silicon layer in the channel direction. The semiconductor device according to item 1. (3) Claim 1, characterized in that the means for electrically connecting the first and second conductivity type semiconductor layers is a high melting point metal compound layer provided on these semiconductor layers. semiconductor devices. (4) a step of introducing an impurity of a second conductivity type into a semiconductor substrate of a first conductivity type; a step of forming a semiconductor layer of a second conductivity type on the substrate via a gate oxide film; A step of introducing an impurity of a second conductivity type into the substrate as a mask, and a step of introducing an impurity of a second conductivity type into the substrate,
A step of ion-implanting a conductivity type impurity using focused ion beam technology to form a first conductivity type semiconductor layer and forming a gate electrode together with the second conductivity type semiconductor layer, and activating the impurity introduced into the substrate by heat treatment. forming a second conductive type source and drain region and a second conductive type diffusion layer between these regions; and forming a means for electrically connecting the first and second conductive type semiconductor layers. A method of manufacturing a semiconductor device, comprising: