JPS61267333A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61267333A JPS61267333A JP60109522A JP10952285A JPS61267333A JP S61267333 A JPS61267333 A JP S61267333A JP 60109522 A JP60109522 A JP 60109522A JP 10952285 A JP10952285 A JP 10952285A JP S61267333 A JPS61267333 A JP S61267333A
- Authority
- JP
- Japan
- Prior art keywords
- bed
- semiconductor chip
- semiconductor device
- semiconductor
- molding resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は樹脂封止型の半導体装置に関するものである。[Detailed description of the invention] [Technical field of invention] The present invention relates to a resin-sealed semiconductor device.
（発明の技術的背景とその問題点）
添付図面の第５図おにび第６図を参照して、従来装置を
説明する。なお、図面の説明において同一要素は同一符
号で示す。(Technical background of the invention and its problems) A conventional apparatus will be described with reference to FIGS. 5 and 6 of the accompanying drawings. In addition, in the description of the drawings, the same elements are indicated by the same symbols.
第５図は従来から使用されている樹脂封止型半導体装置
の内部の斜視図である。この半導体装置は半導体デツプ
１と、リードフレームと、金線。FIG. 5 is a perspective view of the inside of a conventionally used resin-sealed semiconductor device. This semiconductor device includes a semiconductor depth 1, a lead frame, and gold wire.
アルミニウム線等のボンディングワイＡ７２とを有して
いる。そしてリードフレームは、半導体デツプ１がマウ
ントされるベッド３と、ベッド３の周囲に一定の間隔を
有して配設される多数のインナーリード４と、インナー
リード４に連設されるアウターリード（図示せず）と、
ベッド３を両側から吊り下げ状に支持するタイバー５と
からなり、インナーリード４と半導体デツプ１の電極と
の間にボンディングワイヤ２が接続されている。そして
、半導体チップ１、ボンディングワイヤ２おにびインナ
ーリード４の領域がモールド樹脂（図示せず）によって
」Ｎ止され、アウターリードがモールド樹脂の外方に突
出して外部電極となっている。It has a bonding wire A72 such as an aluminum wire. The lead frame includes a bed 3 on which the semiconductor depth 1 is mounted, a large number of inner leads 4 arranged at regular intervals around the bed 3, and outer leads ( (not shown) and
It consists of tie bars 5 that suspend and support the bed 3 from both sides, and bonding wires 2 are connected between the inner leads 4 and the electrodes of the semiconductor deep 1. The regions of the semiconductor chip 1, bonding wires 2, and inner leads 4 are sealed with a molding resin (not shown), and the outer leads protrude outside the molding resin to serve as external electrodes.
このような半導体装置は近年ますます高集積化しており
、半導体チップもそれにつれてわずかながら大型化覆る
傾向がある。半導体チップが大型化すると、第６図に示
すように半導体デツプ１の中心部Ｏに比べて半導体チッ
プ１の端部２点に加わる剪断応力がまずます大ぎくなり
、この剪断応力にＪ：って半導体チップ上のボンディン
グワイヤが塑性変形してスライド現象が発生する。特に
、半導体装置を熱衝撃試験等の苛酷な条件下においた場
合には、上記現象が促進されて導電不良を生じることが
知られている。又、ボンディングワイヤに保護膜が被覆
されている場合やボンディングワイヤ下面に絶縁膜が存
在する場合にも、塑性変形によって膜にクラックが生じ
、１ｆｆｌ不良を生じ＋ ａ。In recent years, such semiconductor devices have become increasingly highly integrated, and semiconductor chips have also tended to become larger, albeit slightly. As the semiconductor chip becomes larger, as shown in FIG. The bonding wires on the semiconductor chip are plastically deformed and a sliding phenomenon occurs. In particular, it is known that when a semiconductor device is subjected to severe conditions such as a thermal shock test, the above phenomenon is accelerated and conductivity defects occur. Furthermore, even if the bonding wire is coated with a protective film or an insulating film is present on the lower surface of the bonding wire, cracks will occur in the film due to plastic deformation, resulting in a 1ffl defect.+a.
（発明の目的）
本発明は上記事情を考慮し°Ｃなされたもので、モール
ド樹脂とベッド間の密着性を向」ニざけ゛゛ＣＣベツド
上導体チップに生じる剪断応ノ〕の低減を図り、これに
Ｊ一つてボンディングワイヤの塑性変形を防止した半導
体装置を提供することを目的どじでいる。(Objective of the Invention) The present invention was developed in consideration of the above circumstances, and aims to improve the adhesion between the mold resin and the bed, thereby reducing the shear stress generated in the conductor chip on the CC bed. Another object of the present invention is to provide a semiconductor device in which plastic deformation of bonding wires is prevented.
上記の目的を達成するため本発明は、半導体チップが載
置されるベッドの−に面であってデツプ載置部以外の部
分を凹凸にして、ベッドとモールド樹脂どの密着性を向
上させた半導体装置を提供するものである。In order to achieve the above object, the present invention provides a semiconductor chip that improves the adhesion between the bed and the molding resin by making the negative side of the bed on which the semiconductor chip is placed, other than the depth placement part, uneven. It provides equipment.
以下、本発明のいくつかの実施例を、第１図乃至第４図
を参照して具体的に説明する。Hereinafter, some embodiments of the present invention will be specifically described with reference to FIGS. 1 to 4.
第１図は一実施例のベッドの形状を示す斜視図である。FIG. 1 is a perspective view showing the shape of a bed in one embodiment.
半導体デツプ１がリードフレーｌ＼のベッド３上にマウ
ントされている。なお、図示はしないがリードフレーム
は、ベッド３の周囲に一定のｕ■隔を有して配設される
複数のインナーリードと、各インナーリードに連設され
て外部電極となるアウターリードどを具備しており、ベ
ッド３は両側からタイバーによって支持されている。ベ
ッド３−Ｆ面には、図示の通り多数の円形孔からなる凹
部７が形成されている。この凹部７は半導体チップ１が
載置される以外のベッド３の部分、すなわち半導体チッ
プ１周囲のベッド上面に形成されている。A semiconductor depth 1 is mounted on a bed 3 of a lead frame l\. Although not shown, the lead frame includes a plurality of inner leads arranged around the bed 3 at regular intervals, and outer leads connected to each inner lead and serving as external electrodes. The bed 3 is supported by tie bars from both sides. As shown in the figure, a recess 7 consisting of a large number of circular holes is formed on the bed 3-F surface. The recess 7 is formed in a portion of the bed 3 other than where the semiconductor chip 1 is placed, that is, on the upper surface of the bed around the semiconductor chip 1.
このため、半導体デツプ１の電極とインナーリードとを
ボンディングワイヤ（図示せず）で接続した後に、半導
体チップ１、ボンディングワイヤ、インナーリード領域
を樹脂封止すると、モールド樹脂（図示せず）が凹部７
内に入り込んでベッド３とモールド樹脂との密着性が向
上するようになっている。この密着性の向上により半導
体チップ１に加わる剪断応力が低減されると共に、半導
体チップの中心部に加わる樹脂の収縮力も低減する。For this reason, when the semiconductor chip 1, the bonding wires, and the inner lead area are sealed with resin after connecting the electrodes of the semiconductor depth 1 and the inner leads with bonding wires (not shown), the molding resin (not shown) will be removed from the recesses. 7
It is designed to penetrate inside and improve the adhesion between the bed 3 and the mold resin. This improved adhesion reduces the shear stress applied to the semiconductor chip 1, and also reduces the shrinkage force of the resin applied to the center of the semiconductor chip.
このため、半導体チップ１どボンディングワイヤとの連
結力が相対的に大きくなり、ボンディングワイヤの塑性
変形が小さくなり、従ってスライド現象やクラック現象
が生じることがなく、導電不良の発生が抑制される。Therefore, the connection force between the semiconductor chip 1 and the bonding wire becomes relatively large, and the plastic deformation of the bonding wire becomes small, so that sliding phenomena and cracking phenomena do not occur, and the occurrence of conductive defects is suppressed.
第２図は以上のにうな凹部７を形成した半導体装置のチ
ップに加わる剪断応力と、従来の半導体装置の半導体チ
ップに加わる剪断応力を対比してプロットしたグラフで
ある。そして、特性曲線イが本発明に係る半導体チップ
に対応し、特性曲線口が従来例の半導体チップに対応し
ている。図示の如く、特性曲線イの勾配が特性曲線口に
比べて緩やかとなっており、従来例の半導体チップの端
部に加わる剪断力（△点）に対して、本発明の半導体チ
ップの端部に加わる剪断力はＢ点に移動している。従っ
て、半導体チップの中心から同一距離だけ離れた箇所で
は、（Ａ−Ｃ）だけ剪断応力が低減することがわかる。FIG. 2 is a graph plotting the shear stress applied to the chip of the semiconductor device in which the recess 7 is formed as described above, and the shear stress applied to the semiconductor chip of the conventional semiconductor device. The characteristic curve A corresponds to the semiconductor chip according to the present invention, and the characteristic curve A corresponds to the conventional semiconductor chip. As shown in the figure, the slope of the characteristic curve A is gentler than the characteristic curve opening, and the edge of the semiconductor chip of the present invention The shear force applied to is moving to point B. Therefore, it can be seen that the shear stress is reduced by (A-C) at a location that is the same distance away from the center of the semiconductor chip.
第３図および第４図は本発明の別の実施例を示すベッド
の平面図である。第３図ではベッド上面の全面に円形孔
の凹部７が形成され、第４図ではベッド上面の周辺部分
に一列の凹部７が形成されている。第４図のようにする
と、第１図のものに比べてリードフレームの製造コスト
を低減させることができるという利点がある。3 and 4 are plan views of a bed showing another embodiment of the present invention. In FIG. 3, circular hole recesses 7 are formed on the entire surface of the bed top, and in FIG. 4, a row of recesses 7 are formed in the peripheral portion of the bed top. The structure shown in FIG. 4 has the advantage that the manufacturing cost of the lead frame can be reduced compared to the structure shown in FIG.
本発明は上記実施例に限定されるものではなく、種々変
形することが可能である。例えば、凹部は円形孔でなく
、角形孔や摺鉢形孔であってもよく、その形状は適宜選
択することができる。また凹部に限らず凸部であっても
よく、さらに一定の長さの凸条あるいは凹条でｂよい。The present invention is not limited to the above embodiments, and can be modified in various ways. For example, the recess may be a rectangular hole or a mortar-shaped hole instead of a circular hole, and the shape thereof can be selected as appropriate. In addition, it is not limited to the recessed portion, but may be a convex portion, and furthermore, it may be a convex line or a concave line of a certain length.
ざらに、凹、凸部の形成はエツチングによってもよく、
コイニング等によってもよい。Rough, concave, and convex portions can be formed by etching.
It may also be done by coining or the like.
以上の通り本発明によれば、ベッドの上面を凹凸にして
ベッドとモールド樹脂との密着性を向上させたのでボン
ディングワイヤが塑性変形することがなく、従って導電
不良を低減させることのできる半導体装置が得られる。As described above, according to the present invention, the top surface of the bed is made uneven to improve the adhesion between the bed and the molding resin, so that the bonding wire is not plastically deformed, and therefore the semiconductor device can reduce conductive defects. is obtained.
第１図は本発明の一実施例の要部の斜視図、第２図は半
導体チップに加わる剪断力をプ［１ツトしたグラフ、第
３図おＪ：び第４図は本発明の他の実施例に係るベッド
部の平面図、第５図は従来装置の要部斜視図、第６図は
その半導体チップに加わる剪断応力を示す斜視図である
。
１・・・半導体チップ、２・・・ボンディングワイヤ、
３・・・ベッド、４・・・インナーリード、７・・・凹
部。
出願人代理人 猪 股 清
−７−・
半導体チップ径
第２図
第５図
第６図FIG. 1 is a perspective view of essential parts of an embodiment of the present invention, FIG. 2 is a graph plotting the shearing force applied to a semiconductor chip, and FIGS. FIG. 5 is a perspective view of essential parts of the conventional device, and FIG. 6 is a perspective view showing shear stress applied to the semiconductor chip. 1... Semiconductor chip, 2... Bonding wire,
3...Bed, 4...Inner lead, 7...Recess. Applicant's agent Kiyoshi Inomata -7- Semiconductor chip diameter Figure 2 Figure 5 Figure 6
Claims (1)
搭載し、モールド樹脂で封止した半導体装置において、
前記ベッド部の上面の前記半導体チップを載置した部分
以外の部分が凹凸になつていることを特徴とする半導体
装置。 ２、前記ベッド部の上面には、エッチングによって複数
の凹部が形成されている特許請求の範囲第１項記載の半
導体装置。 ３、前記凹部が前記ベッド部の上面の全面に形成されて
いる特許請求の範囲第２項記載の半導体装置。 ４、前記凹部が前記ベッド部の上面の角部に形成されて
いる特許請求の範囲第２項記載の半導体装置。[Claims] 1. In a semiconductor device in which a semiconductor chip is mounted on the upper surface of a bed portion of a lead frame and sealed with mold resin,
A semiconductor device characterized in that a portion of the upper surface of the bed portion other than the portion on which the semiconductor chip is placed is uneven. 2. The semiconductor device according to claim 1, wherein a plurality of recesses are formed on the upper surface of the bed portion by etching. 3. The semiconductor device according to claim 2, wherein the recess is formed on the entire upper surface of the bed section. 4. The semiconductor device according to claim 2, wherein the recess is formed at a corner of the upper surface of the bed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60109522A JPS61267333A (en) | 1985-05-22 | 1985-05-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60109522A JPS61267333A (en) | 1985-05-22 | 1985-05-22 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61267333A true JPS61267333A (en) | 1986-11-26 |
Family
ID=14512387
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60109522A Pending JPS61267333A (en) | 1985-05-22 | 1985-05-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61267333A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0999591A1 (en) * | 1998-11-05 | 2000-05-10 | Texas Instruments Incorporated | Semiconductor package |
| JP2014207430A (en) * | 2013-03-21 | 2014-10-30 | ローム株式会社 | Semiconductor device |
| JP2017005124A (en) * | 2015-06-11 | 2017-01-05 | Ｓｈマテリアル株式会社 | Lead frame, method of manufacturing the same, and semiconductor device |
-
1985
- 1985-05-22 JP JP60109522A patent/JPS61267333A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0999591A1 (en) * | 1998-11-05 | 2000-05-10 | Texas Instruments Incorporated | Semiconductor package |
| JP2014207430A (en) * | 2013-03-21 | 2014-10-30 | ローム株式会社 | Semiconductor device |
| US10083900B2 (en) | 2013-03-21 | 2018-09-25 | Rohm Co., Ltd. | Semiconductor device |
| US10431529B2 (en) | 2013-03-21 | 2019-10-01 | Rohm Co., Ltd. | Semiconductor device |
| US10825758B2 (en) | 2013-03-21 | 2020-11-03 | Rohm Co., Ltd. | Semiconductor device |
| JP2017005124A (en) * | 2015-06-11 | 2017-01-05 | Ｓｈマテリアル株式会社 | Lead frame, method of manufacturing the same, and semiconductor device |
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