JPS61264904A - Frequency conversion circuit - Google Patents
Frequency conversion circuitInfo
- Publication number
- JPS61264904A JPS61264904A JP60107465A JP10746585A JPS61264904A JP S61264904 A JPS61264904 A JP S61264904A JP 60107465 A JP60107465 A JP 60107465A JP 10746585 A JP10746585 A JP 10746585A JP S61264904 A JPS61264904 A JP S61264904A
- Authority
- JP
- Japan
- Prior art keywords
- transistors
- signal
- transistor
- intermediate frequency
- trs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
- H03D7/1425—Balanced arrangements with transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
- H03D7/1425—Balanced arrangements with transistors
- H03D7/1433—Balanced arrangements with transistors using bipolar transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
- H03D7/1425—Balanced arrangements with transistors
- H03D7/1458—Double balanced arrangements, i.e. where both input signals are differential
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Superheterodyne Receivers (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はラジオ受信機などに用いる周波数変換回路に関
するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a frequency conversion circuit used in radio receivers and the like.
従来の技術
近年、周波数変換回路を含むラジオ受信回路がIC化さ
れているが、従来の周波数変換回路の一例について図面
を参照しながら説明する。2. Description of the Related Art In recent years, radio reception circuits including frequency conversion circuits have been integrated into ICs. An example of a conventional frequency conversion circuit will be described with reference to the drawings.
第5図は従来の受信回路の周波数変換回路の電気的結線
図を示すものである。第5図において、1はIC化した
周波数変換回路、2は中間周波信号増幅器、3は検波回
路、6はアンテナコイル、5.62はバリコン、56は
中間周波トランス、65は中間周波フィルタ、63は局
部発振用コイ/7,9,10,11.12,13.14
,24゜26はトランジスタ、4,7,64.51はコ
ンデンサ、8,19,20.90は抵抗、21,22゜
23は電流源である。FIG. 5 shows an electrical connection diagram of a frequency conversion circuit of a conventional receiving circuit. In FIG. 5, 1 is an IC frequency conversion circuit, 2 is an intermediate frequency signal amplifier, 3 is a detection circuit, 6 is an antenna coil, 5.62 is a variable capacitor, 56 is an intermediate frequency transformer, 65 is an intermediate frequency filter, 63 are local oscillation coils/7, 9, 10, 11.12, 13.14
, 24° 26 are transistors, 4, 7, 64.51 are capacitors, 8, 19, 20.90 are resistors, and 21, 22° 23 are current sources.
以上のように構成された周波数変換回路について、以下
その動作について説明する。The operation of the frequency conversion circuit configured as described above will be explained below.
アンテナe、コンデンサ4.バリコン6で同調した入力
信号は互いにエミッタ結合したトランジスタ9,1oの
一方のトランジスタ9のベースに加え、トランジスタ9
,1oのコレクタよシトランジスタ11.12のエミッ
タとトランジスタ13.14のエミッタに加えるととも
にトランジスタ24.25とコイA153.コンデンサ
51゜バリコン52の同調回路とで構成される局部発振
回路の局部発振信号は抵抗20を介してトランジスタ1
1.14のベースに加え、トランジスタ11.12と1
3.14のエミッタに加えられた信号をスイッチングし
てトランジスタ11.13のコレクタに接続した中間周
波トランス56に中間周波数信号を取り出し、セラミッ
クフィルタ55を介して中間周波増幅器2に加えて増幅
し、検波回路3で検波し、検波した信号を端子71に取
り出している。Antenna e, capacitor 4. The input signal tuned by the variable capacitor 6 is applied to the base of one of the transistors 9 and 1o whose emitters are connected to each other, and also to the base of the transistor 9.
, 1o to the emitters of transistors 11.12 and 13.14, as well as transistors 24.25 and A153. A local oscillation signal of a local oscillation circuit composed of a capacitor 51 and a tuning circuit of a variable capacitor 52 is transmitted to a transistor 1 via a resistor 20.
In addition to the base of 1.14, transistors 11.12 and 1
The signal applied to the emitter of 3.14 is switched, the intermediate frequency signal is taken out to the intermediate frequency transformer 56 connected to the collector of the transistor 11.13, and the intermediate frequency signal is added to the intermediate frequency amplifier 2 via the ceramic filter 55 for amplification. The detection circuit 3 detects the signal, and the detected signal is taken out to the terminal 71.
発明が解決しようとする問題点
しかしながら、上記のような構成では中間周波トランス
66の一次側インピーダンスは20〜3゜KΩ と高い
、そしてセラミックフィルタ等のフィルタ55のインピ
ーダンスは低く1〜3にΩのものが多い。この中間周波
トランスの一次巻線のインピーダンスを高く設計してい
るのはトランジスタ9,10,11,12,13.14
で構成する周波数変換利得を高くして中間周波トラン7
56に大きな中間周波信号を取り出すためである。そし
て中間周波トランスの2次巻線を少くしてインピーダン
スを低くしてフィルタ65とインピーダンスマツチング
を行うようにしている。Problems to be Solved by the Invention However, in the above configuration, the primary impedance of the intermediate frequency transformer 66 is as high as 20 to 3 KΩ, and the impedance of the filter 55, such as a ceramic filter, is low and is 1 to 3 KΩ. There are many things. Transistors 9, 10, 11, 12, 13, and 14 are designed to have a high impedance in the primary winding of this intermediate frequency transformer.
An intermediate frequency transformer 7 with a high frequency conversion gain consisting of
This is to extract a large intermediate frequency signal to 56. Then, the number of secondary windings of the intermediate frequency transformer is reduced to lower the impedance and impedance matching with the filter 65 is performed.
そのため中間周波トランス66が必要であシ、この中間
周波トランス66のコイA/68とコンデンサ57で中
間周波数に同調しているが、このコイA158.コンデ
ンサ57の値のバラツキがあるために一般的にはコイル
68の値を外部より調整している。そのために受信機を
つくる時に中間周波トラン7の調整が必要であった。Therefore, an intermediate frequency transformer 66 is required, and the coil A/68 of this intermediate frequency transformer 66 and the capacitor 57 are tuned to the intermediate frequency. Since the value of the capacitor 57 varies, the value of the coil 68 is generally adjusted externally. Therefore, it was necessary to adjust the intermediate frequency transformer 7 when making the receiver.
本発明は上記問題点に鑑み、周波数変換回路の出力から
中間周波信号を取り出すフィルタを無調整にし、性能も
よい周波数変換回路を提供するものである。In view of the above-mentioned problems, the present invention provides a frequency conversion circuit with good performance, in which the filter for extracting the intermediate frequency signal from the output of the frequency conversion circuit is not adjusted.
問題点を解決するための手段
上記問題点を解決するために本発明の周波数変換回路は
互いのエミッタを接続した第1と第2のトランジスタと
、この第1と第2のトランジスタのエミッタを第3のト
ランジスタのコレクタに接続し、互いのエミッタを接続
した第4と第6のトランジスタと、この第4と第6のト
ランジスタのエミッタを第6のトランジスタのコレクタ
に接続し、この第3と第6のトランジスタのエミッタを
互いに接続し、この第3と第6のトランジスタの少くと
も一方のトランジスタのベースに入力信号または局部発
振信号を加え、この第1と第6のトランジスタのベース
の接続点と、この第2と第4のトランジスタのベースの
接続点の少くとも一方の接続点に局部発振信号または入
力信号を加え、この第1と第4のトランジスタの接続点
と第2と第6のトランジスタのコレクタの接続点の両方
の接続点よシ周波数変換された互いに逆極性の2つの信
号を取り出し、この2つの信号を差動増幅器用の第7と
第8のトランジスタのベースに加えて増幅し、この信号
をこの第7と第8のトランジスタの少くとも一方からイ
ンピーダンスを低くした出力回路を介して無調整の中間
周波フィルタに取り出すように構成を備えたものである
。Means for Solving the Problems In order to solve the above problems, the frequency conversion circuit of the present invention includes first and second transistors whose emitters are connected to each other, and the emitters of the first and second transistors are connected to a second transistor. The fourth and sixth transistors are connected to the collector of the third transistor, and the emitters of the fourth and sixth transistors are connected to the collector of the sixth transistor, and the third and sixth transistors are connected to the collector of the sixth transistor. The emitters of the No. 6 transistors are connected to each other, an input signal or a local oscillation signal is applied to the base of at least one of the third and sixth transistors, and the connection point between the bases of the first and sixth transistors is connected. , a local oscillation signal or an input signal is applied to at least one connection point between the bases of the second and fourth transistors, and a local oscillation signal or an input signal is applied to the connection point between the first and fourth transistors and the second and sixth transistors. Take out two signals of opposite polarity that have been frequency-converted from both connection points of the collectors of The structure is such that this signal is extracted from at least one of the seventh and eighth transistors to an unadjusted intermediate frequency filter via an output circuit with low impedance.
作用
本発明は上記の構成によって周波数変換された互いに逆
極性の2つの信号を差動増幅器で増幅して利得をあげ、
その後にインピーダンスの低い出力回路を介して無調整
の中間周波フィルタにインピーダンスマツチングしてい
るのでS/N 感度がよく、しかもセラミックフィルタ
等の中間周波フィルタを用いて無調整化ができるもので
ある。Operation The present invention amplifies two signals of opposite polarity that have been frequency-converted by the above configuration using a differential amplifier to increase the gain.
After that, impedance matching is performed via a low-impedance output circuit to an unadjusted intermediate frequency filter, resulting in good S/N sensitivity, and it is possible to eliminate adjustment by using an intermediate frequency filter such as a ceramic filter. .
実施例
以下、本発明の実施例の周波数変換回路について、図面
を参照しながら説明する。Embodiments Hereinafter, frequency conversion circuits according to embodiments of the present invention will be described with reference to the drawings.
第1図は本発明の一実施例における周波数変換回路の電
気的結線図を示すものである。第1図において、1は周
波数変換回路、2は中間周波増幅器、3は検波回路、6
はアンテナコイル、5 r 52ハバリコン、53は局
部発振用コイル、56は中間周波フィルタ、4.了、5
1.54はコンデンサ、8.15,16,19,20,
27,28,29゜30.35,37.40は抵抗、2
1,22.23゜26.36.39は電流源、9〜14
+ 24 + 25t31〜34.38はトランジス
タである。FIG. 1 shows an electrical connection diagram of a frequency conversion circuit in one embodiment of the present invention. In FIG. 1, 1 is a frequency conversion circuit, 2 is an intermediate frequency amplifier, 3 is a detection circuit, and 6
5 r is an antenna coil, 5 r is a hub capacitor, 53 is a local oscillation coil, 56 is an intermediate frequency filter, 4. Completed, 5
1.54 is a capacitor, 8.15, 16, 19, 20,
27, 28, 29° 30.35, 37.40 are resistances, 2
1, 22.23° 26.36.39 is a current source, 9 to 14
+24+25t31 to 34.38 are transistors.
以上のように構成された周波数変換回路について第1図
を用いてその動作を説明する。The operation of the frequency conversion circuit configured as described above will be explained using FIG. 1.
バリコン5.コンデンサ4と同調回路を構成するアンテ
ナコイ/l/6の入力信号は互いにエミッタ結合したト
ランジスタ9,1oの一方のトランジスタ9のベースに
加え、トランジスタ9,10のコ、レクタよシトランジ
スタ11.12のエミッタとトランジスタ13.14の
エミッタに加えるとともにトランジスタ24.26とコ
イル53.コンデンサ51.バリコン52の同調回路と
で構成される局部発振回路の局部発振信号は抵抗2oを
介してトランジスタ11.14のベースに加え、トラン
ジスタ11.12と13.14のエミッタに加えられた
信号をスイッチングしてトランジスタ11.13のコレ
クタの接続点85とトランジスタ12.14のコレクタ
の接続点86に周波数変換された互いに逆極性の2つの
信号を取り出しコンデンサ17.18を介して差動増幅
器用トランジスタ31.32のベースに加えて増幅する
。Varicon 5. The input signal of the antenna coil/l/6 which constitutes the tuning circuit with the capacitor 4 is applied to the base of one of the transistors 9 and 1o whose emitters are coupled to each other, as well as the collector and the collector of the transistors 9 and 10. and the emitters of transistors 13.14, as well as transistors 24.26 and coils 53. Capacitor 51. The local oscillation signal of the local oscillation circuit composed of the tuning circuit of the variable capacitor 52 switches the signal applied to the base of the transistor 11.14 as well as the emitters of the transistors 11.12 and 13.14 via the resistor 2o. Then, two frequency-converted signals of mutually opposite polarity are taken out at the connection point 85 of the collector of the transistor 11.13 and the connection point 86 of the collector of the transistor 12.14, and are then passed through the capacitor 17.18 to the connection point 86 of the collector of the transistor 12.14. 32 base plus amplification.
トランジスタ31のコレクタにダイオード接続のトラン
ジスタ33(ダイオードでもよい。)を接続シ、トラン
ジスタ32のコレクタにPNP)ランジスタ34のコレ
クタを接続し、ダイオード又はダイオード接続のトラン
ジスタ33とトランジスタ34はカレントミラー回路と
して動作し、トランジスタ32.34のコレクタに増幅
された信号はエミッタフォロア用のトランジスタ38の
ベースニ加工、このトランジスタ38のエミッタよシ抵
抗40を介して中間周波フィlレタ(ここではセラミッ
クフィルタ)に中間周波信号を取り出す。A diode-connected transistor 33 (which may be a diode) is connected to the collector of the transistor 31, and a PNP (PNP) transistor 34 collector is connected to the collector of the transistor 32, and the diode or diode-connected transistor 33 and transistor 34 function as a current mirror circuit. The signal that is activated and amplified to the collectors of the transistors 32 and 34 is sent to the base of the emitter follower transistor 38, and then to the intermediate frequency filter (ceramic filter in this case) via the emitter of this transistor 38 and the resistor 40. Extract the frequency signal.
そしてこの中間周波信号は中間周波増幅回路2で増幅し
、検波回路3(ここではムM検波回路)で検波して検波
出力信号を取り出す。検波回路3がAM検波回路の時は
信号レベルの大きさによって直流電圧が変化する信号を
自動利得制御用信号として用い、第1図の線72で中間
周波増幅器2に加えて自動利得制御を行い、線73を介
して周波数変換回路1(トランジスタ1o、9のベース
)に加えて自動利得制御を行っている。この暗線73の
電圧低下するとトランジスタ9,1oの電流が低下し利
得制御する。This intermediate frequency signal is amplified by an intermediate frequency amplification circuit 2, and detected by a detection circuit 3 (here, a M detection circuit) to extract a detection output signal. When the detection circuit 3 is an AM detection circuit, a signal whose DC voltage changes depending on the magnitude of the signal level is used as an automatic gain control signal, and is added to the intermediate frequency amplifier 2 at line 72 in FIG. 1 to perform automatic gain control. , 73 to the frequency conversion circuit 1 (bases of transistors 1o, 9) and automatic gain control. When the voltage of this dark line 73 decreases, the currents of the transistors 9 and 1o decrease, thereby controlling the gain.
ここで周波数変換回路の負荷抵抗15.16の値は従来
の第5図に示す中間周波トランス56の一次側インピー
ダンスよシも低い値である。もし、第1図のこの抵抗値
を20〜30にΩに高くすると電圧降下が大きくなシ、
Vcaの電源電圧が低い場合は使用できない。そのため
低い電圧で使用するためには抵抗15.16の値を小さ
くする必要がある。例えばVccが1.6vで動作させ
るためには抵抗15.16の電圧降下をo、s〜0.7
v位にする必要がある。抵抗15.16に流れる電流が
200μムとすると2.5〜3.6にΩになる。そのた
め従来の中間周波トランス56を用いるよシも周波数変
換回路の変換利得が低い。そこで本発明の第1図の実施
例ではこの負荷抵抗16.16の2つの信号をコンデン
サ17.18を介してトランジスタ31.32のベース
に加え、差動増幅器用トランジスタ31.32で増幅し
てトランジスタ32.34のコレクタに信号を取り出す
。この時、周波数変換回路のトランジスタ11.13と
12゜14のコレクタ信号の両方の信号を差動増幅器の
トランジスタ31.32の両方に加えているのは利得を
大きくするだめである。(これらの信号の一方のみを増
幅すると利得が小さい。)もし一方の信号のみを後の増
幅器で大きく増幅しても利得が上るが後の増幅器で大き
く増幅するとトランジスタの雑音を増幅するのでS/N
比が悪くなる。そのため周波数変換回路の両方の出力を
用いて前段の利得を大きくするために、前記両方の信号
を差動増幅器を用いて増幅している。Here, the value of the load resistance 15.16 of the frequency conversion circuit is lower than the primary side impedance of the conventional intermediate frequency transformer 56 shown in FIG. If this resistance value in Figure 1 is increased to 20 to 30 Ω, the voltage drop will be large.
It cannot be used if the power supply voltage of Vca is low. Therefore, in order to use it at a low voltage, it is necessary to reduce the value of the resistor 15.16. For example, in order to operate with Vcc of 1.6V, the voltage drop across resistor 15.16 should be o,s~0.7
It needs to be in v position. If the current flowing through the resistor 15.16 is 200 .mu.m, the resistance will be 2.5 to 3.6 .OMEGA. Therefore, the conversion gain of the frequency conversion circuit is lower than when using the conventional intermediate frequency transformer 56. Therefore, in the embodiment of the present invention shown in FIG. 1, the two signals of the load resistor 16.16 are applied to the base of the transistor 31.32 via the capacitor 17.18, and are amplified by the differential amplifier transistor 31.32. A signal is taken out to the collectors of transistors 32 and 34. At this time, the reason why both signals of the collector signals of transistors 11.13 and 12.14 of the frequency conversion circuit are applied to both transistors 31.32 of the differential amplifier is to increase the gain. (If only one of these signals is amplified, the gain is small.) If only one signal is amplified by a later amplifier, the gain will increase, but if it is amplified by a later amplifier, it will amplify the noise of the transistor, so the S/ N
The ratio becomes worse. Therefore, in order to increase the gain of the previous stage by using both outputs of the frequency conversion circuit, both of the signals are amplified using a differential amplifier.
次にエミッタフォロア用トランジスタ38を用いると、
このトランジスタ38のベースインビーダンヌが高いの
で差動増幅器31,32の負荷抵抗36で利得がほぼ決
定され、大きな利得を得ることができる。さらにトラン
ジスタ38のエミッタのインピーダンスが低いのでフィ
ルタ65のインピーダンスが3にΩであれば抵抗40を
約3xΩニスるとインピーダンスマツチングすることが
できる。即ちエミッタフォロアのトランジスタ38はイ
ンピーダンス変換をするために用いている。Next, if the emitter follower transistor 38 is used,
Since the base in B-Danne of this transistor 38 is high, the gain is almost determined by the load resistor 36 of the differential amplifiers 31 and 32, and a large gain can be obtained. Furthermore, since the impedance of the emitter of the transistor 38 is low, if the impedance of the filter 65 is about 3.OMEGA., impedance matching can be achieved by varnishing the resistor 40 to about 3.times..OMEGA. That is, the emitter follower transistor 38 is used for impedance conversion.
さらに差動増幅器31.32とPNP)ランジスタを用
いてもよいがIC化した時にPNP )ランジヌタの方
がMP)i)ランジスタよシもトランジスタの雑音が大
きいのでPNP)ランジスタを用いな(%NPN)、7
ンジスタを用いた。そしてこのNPN )ランジスタ3
1.32のベース電圧とトランジスタ11,13,12
,14のコレクタ電圧が同一にできなかったのでコンデ
ンサ1了。Furthermore, differential amplifiers 31 and 32 and PNP) transistors may be used, but when integrated into an IC, PNP) transistors have a higher MP) ), 7
using a register. And this NPN ) transistor 3
1.32 base voltage and transistors 11, 13, 12
, 14 collector voltages could not be made the same, so capacitor 1 was used.
18を用いている。18 is used.
またトランジスタ31.32のエミッタの抵抗30をト
ランジスタを用いた電流源でも動作するがトランジスタ
を用いるとトランジスタの雑音が大きくなるので抵抗3
oを用いている。It is also possible to operate the resistor 30 at the emitter of the transistors 31 and 32 by using a current source using a transistor, but if a transistor is used, the noise of the transistor becomes large, so the resistor 30 at the emitter of the transistor 31 and 32
o is used.
以上のように周波数変換された互いに逆極性の2つの信
号を差動増幅器で増幅し、インピーダンスの低いセラミ
ックフィルタ等の無調整フィルタに中間周波信号を取り
出し、中間周波フィルタを無調整にして、しかも性能の
よい周波数変換回路を構成することができる。As described above, the two frequency-converted signals of opposite polarity are amplified by a differential amplifier, and the intermediate frequency signal is taken out to a non-adjustable filter such as a low impedance ceramic filter, and the intermediate frequency filter is not adjusted. A frequency conversion circuit with good performance can be constructed.
第2図は本発明の第2の実施例を示す周波数変換回路を
示す。この第2図では周波数変換回路のトランジスタ9
,1oの一方のトランジスタ9のベースに局部発振信号
を加え、トランジスタ11゜14と12,13のベース
の一方に入力信号を加えても第1図と同じように動作す
るものである。FIG. 2 shows a frequency conversion circuit showing a second embodiment of the invention. In this figure 2, transistor 9 of the frequency conversion circuit is shown.
, 1o, and if an input signal is applied to one of the bases of transistors 11, 14, 12, and 13, the same operation as in FIG. 1 is achieved.
この時の自動利得制御は線73に正方向の電圧がくると
トランジスタ96がONしてトランジスタ9.10の電
流を低下して自動利得制御をする。At this time, automatic gain control is performed by turning on the transistor 96 when a positive voltage is applied to the line 73 and lowering the current of the transistors 9 and 10.
第3図は本発明の第3の実施例を示す周波数変換回路を
示す。この第3図ではトランジスタ31゜320コレク
タに第1図に示すカレントミラー回路をなくし、抵抗3
5のみで行ったもので、第1図の実施例と同じように動
作するものである。FIG. 3 shows a frequency conversion circuit showing a third embodiment of the present invention. In this figure 3, the current mirror circuit shown in figure 1 is removed from the transistor 31°320 collector, and the resistor 3
5, and operates in the same manner as the embodiment shown in FIG.
第4図は本発明の第4の実施例を示す周波数変換回路で
ある。第4の実施例では第3図のエミッタフォロア用ト
ランジスタ38をなくしたものを示す。この負荷抵抗3
5を第1図〜第3図の抵抗りとほぼ同一の低いインピー
ダンスの3にΩにするとインピーダンスマツチングがで
きる。しかし、第1〜第3図のものよシトランジスタ3
1.32の利得が小さいが差動増幅器を用いて周波数変
換回路の2つの信号を増幅するようにしているのである
程度利得が大きいので、第4図の場合でも第1図のもの
とほぼ同じように動作させることができる。FIG. 4 shows a frequency conversion circuit showing a fourth embodiment of the present invention. In the fourth embodiment, the emitter follower transistor 38 shown in FIG. 3 is omitted. This load resistance 3
Impedance matching can be achieved by changing 5 to 3 Ω, which has a low impedance that is almost the same as the resistance shown in FIGS. 1 to 3. However, as shown in Figures 1 to 3, the transistor 3
Although the gain of 1.32 is small, since a differential amplifier is used to amplify the two signals of the frequency conversion circuit, the gain is somewhat large, so the case in Figure 4 is almost the same as the one in Figure 1. can be operated.
発明の効果
以上のように本発明は入力信号と局部発振信号とによシ
周波数変換した互いに逆位相の2つの信号を差動増幅器
で増幅して後に低インピーダンス出力として無調整の中
間周波フィルタに取り出す構成にすることによシ、S/
N感度がよい状態で中間周波数の調整をなくすることが
できるへEffects of the Invention As described above, the present invention amplifies two signals of opposite phases obtained by converting the frequency of an input signal and a local oscillation signal using a differential amplifier, and then outputs the signals as a low impedance output to an unadjusted intermediate frequency filter. By configuring it to be taken out, S/
It is possible to eliminate intermediate frequency adjustment while maintaining good N sensitivity.
第1図は本発明の第1の実施例における周波数変換回路
の電気的結線図、第2図は本発明の第2の実施例の周波
数変換回路の電気的結線図、第3図、第4図は本発明の
第3.第4の実施例を示す周波数変換回路の電気的結線
図、第5図は従来の周波数変換回路の電気的結線図であ
る。
1・・・・・・周波数変換回路、2・・・・・・中間周
波増幅器、3・・・・・・検波器、6・・・・・・アン
テナコイル、5.52・・・・・・バリコン、53・・
・・・・局部発振用コイル、65・・・・・・中間周波
フィルタ、56・・・・・・中間周波トランス、9〜1
4,24,25.31〜34,38゜96・・・・・・
トランジスタ、4,7,51.54・・・・・・コンデ
ンサ、8,15.16,19,2Φ、27゜28.29
,30,35,37,40,92゜93.94・・・・
・・抵抗、21 .22,23,26゜36.39.9
1・・・・・・電流源。FIG. 1 is an electrical connection diagram of a frequency conversion circuit according to a first embodiment of the present invention, FIG. 2 is an electrical connection diagram of a frequency conversion circuit according to a second embodiment of the present invention, and FIGS. The figure shows the third aspect of the present invention. An electrical wiring diagram of a frequency conversion circuit showing a fourth embodiment, and FIG. 5 is an electrical wiring diagram of a conventional frequency conversion circuit. 1... Frequency conversion circuit, 2... Intermediate frequency amplifier, 3... Detector, 6... Antenna coil, 5.52...・Variable capacitor, 53...
...Local oscillation coil, 65...Intermediate frequency filter, 56...Intermediate frequency transformer, 9-1
4,24,25.31~34,38°96...
Transistor, 4, 7, 51.54... Capacitor, 8, 15.16, 19, 2Φ, 27° 28.29
, 30, 35, 37, 40, 92°93.94...
...Resistance, 21. 22, 23, 26° 36.39.9
1... Current source.
Claims (1)
、この第1と第2のトランジスタのエミッタを第3のト
ランジスタのコレクタに接続し、互いのエミッタを接続
した第4と第5のトランジスタと、この第4と第5のト
ランジスタのエミッタを第6のトランジスタのコレクタ
に接続し、この第3と第6のトランジスタのエミッタを
互いに接続し、この第3と第6のトランジスタの少くと
も一方のトランジスタのベースに入力信号または局部発
振信号を加え、この第1と第5のトランジスタのベース
の接続点とこの第2と第4のトランジスタのベースの接
続点の少くとも一方の接続点に局部発振信号または入力
信号を加え、この第1、第4のトランジスタのコレクタ
の接続点と、この第2、第5のトランジスタのコレクタ
の接続点の両方の接続点より周波数変換した互いに逆極
性の2つの信号を取り出し、この2つの信号を差動増幅
器用の第7と第8のトランジスタのベースに加えて増幅
し、この信号をこの第7と第8のトランジスタの少くと
も一方からインピーダンスを低くした出力回路を介して
、セラミックフィルタ等の無調整の中間周波フィルタに
中間周波信号を取り出すように構成したことを特徴とす
る周波数変換回路。first and second transistors whose emitters are connected to each other; and fourth and fifth transistors whose emitters are connected to the collector of a third transistor, and whose emitters are connected to each other. , the emitters of the fourth and fifth transistors are connected to the collector of a sixth transistor, the emitters of the third and sixth transistors are connected to each other, and at least one of the third and sixth transistors is connected to the collector of the sixth transistor. An input signal or a local oscillation signal is applied to the base of the transistor, and the local oscillation signal is applied to at least one of the connection point between the bases of the first and fifth transistors and the connection point between the bases of the second and fourth transistors. A signal or an input signal is applied, and the frequency is converted from the connection point between the collectors of the first and fourth transistors and the connection point between the collectors of the second and fifth transistors. A signal is taken out, these two signals are added to the bases of seventh and eighth transistors for a differential amplifier, amplified, and this signal is outputted from at least one of the seventh and eighth transistors with a low impedance. 1. A frequency conversion circuit characterized in that the frequency conversion circuit is configured to extract an intermediate frequency signal to an unadjusted intermediate frequency filter such as a ceramic filter through the circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60107465A JPH0640604B2 (en) | 1985-05-20 | 1985-05-20 | Frequency conversion circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60107465A JPH0640604B2 (en) | 1985-05-20 | 1985-05-20 | Frequency conversion circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61264904A true JPS61264904A (en) | 1986-11-22 |
JPH0640604B2 JPH0640604B2 (en) | 1994-05-25 |
Family
ID=14459878
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60107465A Expired - Lifetime JPH0640604B2 (en) | 1985-05-20 | 1985-05-20 | Frequency conversion circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0640604B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63260204A (en) * | 1986-12-31 | 1988-10-27 | エス・ジー・エス ミクロエレトロニカ エス・ピー・エー | Integrated coupling circuit |
US5222016A (en) * | 1989-10-11 | 1993-06-22 | Kabushiki Kaisha Toshiba | Frequency converter |
EP0697765A3 (en) * | 1994-07-18 | 1996-11-27 | Siemens Ag | Phase shift modulation circuit |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5252513A (en) * | 1975-10-27 | 1977-04-27 | Sony Corp | Frequency converter |
JPS5646328U (en) * | 1979-09-17 | 1981-04-25 | ||
JPS5866140A (en) * | 1981-10-15 | 1983-04-20 | Sanyo Electric Co Ltd | Word processor |
JPS58225429A (en) * | 1982-06-25 | 1983-12-27 | Fujitsu Ltd | Spelling error processing system of engilish sentence processor |
JPS6190259A (en) * | 1984-10-08 | 1986-05-08 | Brother Ind Ltd | electronic typewriter |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5646328B2 (en) * | 1971-12-09 | 1981-11-02 |
-
1985
- 1985-05-20 JP JP60107465A patent/JPH0640604B2/en not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5252513A (en) * | 1975-10-27 | 1977-04-27 | Sony Corp | Frequency converter |
JPS5646328U (en) * | 1979-09-17 | 1981-04-25 | ||
JPS5866140A (en) * | 1981-10-15 | 1983-04-20 | Sanyo Electric Co Ltd | Word processor |
JPS58225429A (en) * | 1982-06-25 | 1983-12-27 | Fujitsu Ltd | Spelling error processing system of engilish sentence processor |
JPS6190259A (en) * | 1984-10-08 | 1986-05-08 | Brother Ind Ltd | electronic typewriter |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63260204A (en) * | 1986-12-31 | 1988-10-27 | エス・ジー・エス ミクロエレトロニカ エス・ピー・エー | Integrated coupling circuit |
US5222016A (en) * | 1989-10-11 | 1993-06-22 | Kabushiki Kaisha Toshiba | Frequency converter |
EP0697765A3 (en) * | 1994-07-18 | 1996-11-27 | Siemens Ag | Phase shift modulation circuit |
Also Published As
Publication number | Publication date |
---|---|
JPH0640604B2 (en) | 1994-05-25 |
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