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JPS61145936A - Radio reception circuit - Google Patents

Radio reception circuit

Info

Publication number
JPS61145936A
JPS61145936A JP26901684A JP26901684A JPS61145936A JP S61145936 A JPS61145936 A JP S61145936A JP 26901684 A JP26901684 A JP 26901684A JP 26901684 A JP26901684 A JP 26901684A JP S61145936 A JPS61145936 A JP S61145936A
Authority
JP
Japan
Prior art keywords
transistor
circuit
base
signal
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26901684A
Other languages
Japanese (ja)
Inventor
Kiyohiko Takeuchi
竹内 清彦
Tsuneo Okubo
大久保 常男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP26901684A priority Critical patent/JPS61145936A/en
Publication of JPS61145936A publication Critical patent/JPS61145936A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06Receivers
    • H04B1/16Circuits
    • H04B1/26Circuits for superheterodyne receivers
    • H04B1/28Circuits for superheterodyne receivers the receiver comprising at least one semiconductor device having three or more electrodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Superheterodyne Receivers (AREA)

Abstract

PURPOSE:To reduce its cost by connecting a constant current circuit of a frequency converting circuit and an AGC circuit in terms of DC to decrease the number of capacitors and terminals connecting them. CONSTITUTION:Emitters of the 1st transistor (Tr)1 and the 2nd Tr2 of a frequency converting circuit 31 are connected in common to a collector of the 5th Tr6 and emitters of the 3rd Tr4 and the 4th Tr5 are connected in common to a collector of the 6th Tr7. Further, bases of the 1st and 2nd Trs 1, 2 are connected, to which a local oscillating signal is fed, an intermediate frequency signal is extracted from at least one of collectors of the 1st and 3rd Trs 1, 4 or the 2nd and 4th Trs 2, 5, the emitters of the 5th and 6th Trs 6, 7 are connected to common via a common resistor 8, the bases of the 5th and 6th Trs 6, 7 are connected in terms of DC, an AGC signal is fed to a base of the 6th Tr7 and the base of the 6th Tr7 is connected to a constant current source and a bypass capacitor 37 is connected.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はAMラジオ放送受信機に適合する受信回路に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a receiving circuit suitable for an AM radio broadcast receiver.

従来の技術 近年、ラジオ受信機の小型軽量化への要望からその受信
回路においても集積回路化が進んでいるが、外付部品の
削減および端子数の削減への取組みは必要不可欠な問題
である。
Conventional technology In recent years, the desire to make radio receivers smaller and lighter has led to the use of integrated circuits in their receiving circuits, but efforts to reduce external parts and the number of terminals are essential issues. .

以下図面を参照しながら従来のラジオ受信回路について
説明する。
A conventional radio receiving circuit will be described below with reference to the drawings.

第2図は従来のラジオ受信回路における電気的結線図で
あり1図中129はAGO信号発生回路、130は周波
数変換回路、131は局部発振回路。
FIG. 2 is an electrical wiring diagram of a conventional radio receiving circuit, in which 129 is an AGO signal generation circuit, 130 is a frequency conversion circuit, and 131 is a local oscillation circuit.

132は定電流回路である。132 is a constant current circuit.

受信時の動作について説明すると、アンテナコイル13
5 ト/< IJコン134.コンデンサ133によっ
て同調された信号はムM周波数変換回路130に加えら
れる。一方、局部発振回路はコイル139.バリコン1
4o、コンデンサ141より°成る同調回路と、コイル
139の2次巻線に接続された局部発蚕用のトランジス
タ117,118によって構成され、トランジスタ11
7のベース。
To explain the operation during reception, the antenna coil 13
5 To/< IJ Con134. The signal tuned by capacitor 133 is applied to a frequency conversion circuit 130. On the other hand, the local oscillation circuit is connected to the coil 139. Varicon 1
4o, a tuning circuit consisting of a capacitor 141, and transistors 117 and 118 for local silkworm generation connected to the secondary winding of the coil 139;
7 base.

エミッタ、トランジスタ118のエミッタ、コレクタと
同一位相で増幅されて正帰還ループを作り発振するよう
に構成されている。そして、ここで得られた局部発振信
号はトランジスタ114よ構成るエミッタフォロアを介
して周波数変換回路130のトランジスタ109のベー
スに加えられる。するとトランジスタ108と109は
エミッタ結合の差動増幅器として動作し、トランジスタ
108 、109のコレクタには互いに逆位相の発振信
号が出力し、周波数変換用トランジスタ104゜105
のエミッタとトランジスタ106 、107のエミッタ
に加えられる。アンテナコイル136で受信した信号は
トランジスタ104 、107のベースに加えられる。
The emitter is amplified in the same phase as the emitter and collector of the transistor 118 to create a positive feedback loop and oscillate. The local oscillation signal obtained here is applied to the base of the transistor 109 of the frequency conversion circuit 130 via an emitter follower constituted by the transistor 114. Then, the transistors 108 and 109 operate as an emitter-coupled differential amplifier, and oscillation signals with opposite phases are output to the collectors of the transistors 108 and 109, and the frequency conversion transistors 104 and 105
and the emitters of transistors 106 and 107. The signal received by antenna coil 136 is applied to the bases of transistors 104 and 107.

トランジスタ104 、10Sとトランジスタ10S 
、 107はそれぞれエミッタ結合されているため、エ
ミッタからの発振信号と、上記アンテナ135からの受
信信号が互に混合され、その出力がトランジスタ10S
 、 107のコレクタに接続された中間周波コイル1
36の2次側137に中間周波信号として取り出される
Transistor 104, 10S and transistor 10S
, 107 are emitter-coupled, so the oscillation signal from the emitter and the received signal from the antenna 135 are mixed with each other, and the output is sent to the transistor 10S.
, intermediate frequency coil 1 connected to the collector of 107
The signal is extracted as an intermediate frequency signal to the secondary side 137 of 36.

定電流回路は、定電流源128とこれに接続されたトラ
ンジスタ127 、124 、123で構成するカレン
トミラー回路からなり、局部発振回路および周波数変換
回路に電源供給している。次に、ムGC信号発生回路は
入力レベルに応じてムGC信毎を出力し、トランジスタ
101 、102ヲ導通状態にし、周波数変換回路の電
流を減少するように動作して周波数変換回路の利得を下
げ、大入力時においても安定した振幅の中間周波信号を
得ることがでさる。
The constant current circuit consists of a current mirror circuit constituted by a constant current source 128 and transistors 127, 124, and 123 connected to the constant current source 128, and supplies power to the local oscillation circuit and the frequency conversion circuit. Next, the MGC signal generation circuit outputs each MGC signal according to the input level, turns on the transistors 101 and 102, operates to reduce the current of the frequency conversion circuit, and adjusts the gain of the frequency conversion circuit. This makes it possible to obtain an intermediate frequency signal with stable amplitude even when the input voltage is low.

発明が解決しようとする問題点 しかしながら上記のような回路構成では周波数変換回路
の定電流用トランジスタ110,112゜116のベー
ス共通ラインにバイパスコンデンサ142を接続して電
流源のインピーダンスを下げるとともに電流源ノイズを
とる必要があり、又AGCj回路にはローパスフィルタ
ーとしてコンデンサ142が接続される。よって、端子
数に制限のある集積回路装置においてはコンデンサを接
続するだめの端子が2端子必要となり、好ましいもので
はない。
Problems to be Solved by the Invention However, in the above circuit configuration, a bypass capacitor 142 is connected to the base common line of the constant current transistors 110, 112° 116 of the frequency conversion circuit to lower the impedance of the current source and to It is necessary to remove noise, and a capacitor 142 is connected to the AGCj circuit as a low-pass filter. Therefore, in an integrated circuit device having a limited number of terminals, two terminals are required to connect the capacitor, which is not preferable.

本発明は上記の問題点を解決するため外付は部品を減ら
し集積回路装置の端子数を削減することを目的としたラ
ジオ受信回路を提供するものである。
In order to solve the above-mentioned problems, the present invention provides a radio receiving circuit which aims to reduce the number of external components and the number of terminals of an integrated circuit device.

問題点を解決するだめの手段 上記問題点を解決するために本発明のラジオ受信回路は
1周波数変換回路の第1のトランジスタと第2のトラン
ジスタのエミッタを共通として第5のトランジスタのコ
レクタに接続すると共に、第3のトランジスタと第4の
トランジスタのエミッタを共通として第6のトランジス
タのコレクタに接続し、第1.第2のトランジスタのベ
ースを接続して局部発振信号を加え、第1.第3のトラ
ンジスタ又は第2.第4のトランジスタのコレクタの少
なくとも一方よシ中間周波信号を取シ出し。
Means for Solving the Problems In order to solve the above problems, the radio receiving circuit of the present invention connects the emitters of the first transistor and the second transistor of the frequency conversion circuit in common to the collector of the fifth transistor. At the same time, the emitters of the third transistor and the fourth transistor are commonly connected to the collector of the sixth transistor, and the emitters of the first and fourth transistors are connected in common to the collector of the sixth transistor. The base of the second transistor is connected to apply a local oscillation signal, and the base of the first transistor is connected. a third transistor or a second transistor; An intermediate frequency signal is extracted from at least one of the collectors of the fourth transistor.

上記第5.第6のトランジスタのエミッタを共通巨 の抵抗を介して接地し、この第6.第6のトランジスタ
のベースを直流的に接続し、第6のトランジスタのベー
スにム0C信号を加え、さらに第6のトランジスタのベ
ースを定電流源に接続するとともにバイパス用のコンデ
ンサを接続するという構成を備えたものである。
Above 5. The emitter of the sixth transistor is grounded through a common large resistor. A configuration in which the base of the sixth transistor is connected in a DC manner, a MU0C signal is applied to the base of the sixth transistor, and the base of the sixth transistor is connected to a constant current source and a bypass capacitor is connected. It is equipped with the following.

作用 本発明は上記した構成によって従来のムGO回路ニオケ
るローパスフィルターの機能を持ったコンデンサと、周
波数変換回路の定電流源のインピーダンスを下げノイズ
を削減するためのコンデンサの機能をバイパス用のコン
デンサにより満足させることができるものである。
Operation The present invention has the above-mentioned configuration, and provides a capacitor that has the function of a low-pass filter that is similar to the conventional GO circuit, and a capacitor that bypasses the function of the capacitor for lowering the impedance of the constant current source of the frequency conversion circuit and reducing noise. It is possible to satisfy the following.

実施例 以下本発明の一実施例のラジオ受信回路について図面を
参照しながら説明する。
Embodiment A radio receiving circuit according to an embodiment of the present invention will be described below with reference to the drawings.

第1図は本発明の第1の実施例におけるラジオ受信回路
の一部を示すも−のである。第1図において、31は周
波数変換回路、32は局部発振回路。
FIG. 1 shows a part of a radio receiving circuit in a first embodiment of the present invention. In FIG. 1, 31 is a frequency conversion circuit, and 32 is a local oscillation circuit.

33は定電流回路である。33 is a constant current circuit.

受°信時の動作について説明すると、アンテナコイル3
5とバリコン36.コンデンサ34によって同調された
信号は周波数変換回路31に加えられる。局部発振回路
はコイル40.バリコン42゜コンデンサ43より成る
同調回路と、コイル40の2次巻線に接続された局部発
振用のトランジスタ14.15によって構成され、トラ
ンジスタ140ベース、エミッタ、トランジスタ16の
エミッタ、コレクタと同一位相で増幅されて正帰還ルー
プを作り発振するように構成されている。そして、ここ
で得られた局部発振信号は抵抗13を介して周波数変換
回路31のトランジスタ1およびトランジスタ6のベー
スに加えられる。アンテナコイル35で受信した信号は
トランジスタ6のベースに加えられる。すると、トラン
ジスタ6と7はエミッタ結合の差動増幅器として動作し
、トランジスタ6.7のコレクタには互いに逆位相の受
信信号が出力し、周波数変換用トランジスタ1゜2のエ
ミッタとトランジスタ4.6のエミッタに加えられる。
To explain the operation during reception, antenna coil 3
5 and variable capacitor 36. The signal tuned by capacitor 34 is applied to frequency conversion circuit 31. The local oscillation circuit is a coil 40. It consists of a tuned circuit consisting of a 42° variable capacitor 43 and a local oscillation transistor 14.15 connected to the secondary winding of the coil 40, and is in phase with the base and emitter of the transistor 140 and the emitter and collector of the transistor 16. It is configured to be amplified to create a positive feedback loop and oscillate. The local oscillation signal obtained here is applied to the bases of transistor 1 and transistor 6 of frequency conversion circuit 31 via resistor 13. The signal received by antenna coil 35 is applied to the base of transistor 6. Then, the transistors 6 and 7 operate as an emitter-coupled differential amplifier, and reception signals having opposite phases are output to the collector of the transistor 6.7, and the emitter of the frequency conversion transistor 1.2 and the transistor 4.6 are connected to each other. Added to emitter.

ここで、トランジスタ1,2とトランジスタ4,5はそ
れぞれエミッタ結合されているため、エミッタからの受
信信号と、上記局部発振回路からの発信信号が互いに混
合され、その出力がトランジスタ2,6のコレクタに接
続された中間周波コイル38の2次側39に中間周波信
号として取出される。定電流回路33は定電流源29と
これに接続されたトランジスタ1B、19゜20.21
からなるカレントミラー回路で構成され、トランジスタ
18のコレクタはダイオード22と抵抗23を介して接
地されるとともに局部発振回路の定電流源用トランジス
タ160ベースに接続され、局部発振回路の電流を決め
る。トランジスタ19のコレクタはダイオード26と抵
抗24を介して接地されるとともに周波数変換回路のト
ランジスタ1,50ベ一ス電位を決めるトランジスタ1
10ベースと、トランジスタ2,4のベース電位を決め
るトランジスタ9のベースニ接続される。トランジスタ
20のコレクタはダイオード28と抵抗27を介して接
地され、又抵抗26を介して周波数変換回路のトランジ
スタ7のベースとアンテナコイル35の2次巻線を介し
てトランジスタ6のベースに接続され、周波数変換回路
の電流が決められる。ムGC信号発生回路30は、この
出力をエミッタを接地したムGC制御用トランジスタ4
1のベースに入力し、このトランジスタ41のコレクタ
を周波数変換回路のトランジスタ7およびアンテナコイ
ル35を介してWkLだトランジスタ6のベースに接続
する。ここでアンテナコイル35より大入力信号が入力
され、AGO信号発生回路30より出たAGO信号はA
GO制御用トランジスタ41を導通状態とし。
Here, since transistors 1 and 2 and transistors 4 and 5 are emitter-coupled, the received signal from the emitter and the oscillation signal from the local oscillation circuit are mixed with each other, and the output is sent to the collectors of transistors 2 and 6. The signal is output as an intermediate frequency signal to the secondary side 39 of an intermediate frequency coil 38 connected to the intermediate frequency coil 38. The constant current circuit 33 includes a constant current source 29 and a transistor 1B connected thereto, 19°20.21
The collector of the transistor 18 is grounded via a diode 22 and a resistor 23, and is also connected to the base of a constant current source transistor 160 of the local oscillation circuit to determine the current of the local oscillation circuit. The collector of the transistor 19 is grounded via the diode 26 and the resistor 24, and the transistor 1 determines the base potential of the transistors 1 and 50 of the frequency conversion circuit.
The base of transistor 9 is connected to the base of transistor 9, which determines the base potential of transistors 2 and 4. The collector of the transistor 20 is grounded via a diode 28 and a resistor 27, and is also connected to the base of a transistor 7 of the frequency conversion circuit via a resistor 26 and the base of a transistor 6 via a secondary winding of an antenna coil 35. The current of the frequency conversion circuit is determined. The MuGC signal generation circuit 30 connects this output to a MuGC control transistor 4 whose emitter is grounded.
The collector of this transistor 41 is connected to the base of the WkL transistor 6 via the transistor 7 of the frequency conversion circuit and the antenna coil 35. Here, a large input signal is input from the antenna coil 35, and the AGO signal output from the AGO signal generation circuit 30 is
The GO control transistor 41 is turned on.

周波数変換回路のトランジスタ7および直流的に結合さ
れたトランジスタ6のベース電位を下げるように動作す
る。
It operates to lower the base potential of transistor 7 of the frequency conversion circuit and transistor 6 coupled in direct current.

以上のように構成することにより、従来例に示した定電
流源のバイパス用コンデンサとムGO回路のローパスフ
ィルター用のコンデンサの機能を本実施例ではトランジ
スタ7のベースに接続するコンデンサ37で満足するこ
とができる。
With the above configuration, in this embodiment, the capacitor 37 connected to the base of the transistor 7 can fulfill the functions of the constant current source bypass capacitor and the MGO circuit low-pass filter capacitor shown in the conventional example. be able to.

発明の効果 以上のように本発明は1周波数変換回路の定電流回路と
ムGC回路とを直流的で接続することにより、定電流源
用のバイパスコンデンサと五GO回路のローパスフィル
ター用のコンデンサの2つを1つのコンデンサで機能を
満足させることができ、コンデンサを削減できるのと同
時にコンデンサを接続するための端子も減らすことがで
き、限られた端子数で設計を要求される集積回路装置に
おいて大きなコストダウンを図ることができる。
Effects of the Invention As described above, the present invention connects the constant current circuit of one frequency conversion circuit and the mu GC circuit in a direct current manner, thereby reducing the bypass capacitor for the constant current source and the capacitor for the low pass filter of the five GO circuit. It is possible to satisfy two functions with one capacitor, reducing the number of capacitors and at the same time reducing the number of terminals for connecting capacitors, making it ideal for integrated circuit devices that require design with a limited number of terminals. A large cost reduction can be achieved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例におけるラジオ受信回路のチ
ューナ部の回路図、第2図は従来のラジオ受信回路のチ
ューナ回路図である。 31・・・・・・周波数変換回路、32・・・・・・局
部発振回路、33・・・・・・定電流回路、30・・・
・・・AGC信号発生回路、41・・・・・・AGC用
トランジスタ。
FIG. 1 is a circuit diagram of a tuner section of a radio receiving circuit according to an embodiment of the present invention, and FIG. 2 is a tuner circuit diagram of a conventional radio receiving circuit. 31... Frequency conversion circuit, 32... Local oscillation circuit, 33... Constant current circuit, 30...
...AGC signal generation circuit, 41...AGC transistor.

Claims (1)

【特許請求の範囲】[Claims] 周波数変換回路、局部発振回路、中間周波増幅回路、A
M検波回路を有し、上記周波数変換回路の第1と第2の
トランジスタのエミッタを共通として第6のトランジス
タのコレクタに接続すると共に、第3と第4のトランジ
スタのエミッタを共通として第6のトランジスタのコレ
クタに接続し、上記第1、第4のトランジスタのベース
に局部発振信号を加え、上記第1、第3のトランジスタ
のコレクタ又は上記第2、第4のトランジスタのコレク
タの少なくとも一方より中間周波信号を取出し、かつ上
記第5、第6のトランジスタのエミッタを共通の抵抗を
介して接地し、上記第5のトランジスタのベースに入力
信号を加え、上記第6のトランジスタのベースと第5の
トランジスタのベースを直流的に接続し、上記第6のト
ランジスタのベースにAGC信号を加え、上記第6のト
ランジスタのベースにバイパス用コンデンサを接続した
ことを特徴とするラジオ受信回路。
Frequency conversion circuit, local oscillation circuit, intermediate frequency amplification circuit, A
M detection circuit, the emitters of the first and second transistors of the frequency conversion circuit are connected in common to the collector of the sixth transistor, and the emitters of the third and fourth transistors are connected in common to the collector of the sixth transistor. A local oscillation signal is connected to the collector of the transistor, and a local oscillation signal is applied to the bases of the first and fourth transistors. A frequency signal is taken out, the emitters of the fifth and sixth transistors are grounded via a common resistor, an input signal is applied to the base of the fifth transistor, and the base of the sixth transistor and the fifth transistor are connected to each other. A radio receiving circuit characterized in that bases of the transistors are connected in a DC manner, an AGC signal is applied to the base of the sixth transistor, and a bypass capacitor is connected to the base of the sixth transistor.
JP26901684A 1984-12-19 1984-12-19 Radio reception circuit Pending JPS61145936A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26901684A JPS61145936A (en) 1984-12-19 1984-12-19 Radio reception circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26901684A JPS61145936A (en) 1984-12-19 1984-12-19 Radio reception circuit

Publications (1)

Publication Number Publication Date
JPS61145936A true JPS61145936A (en) 1986-07-03

Family

ID=17466498

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26901684A Pending JPS61145936A (en) 1984-12-19 1984-12-19 Radio reception circuit

Country Status (1)

Country Link
JP (1) JPS61145936A (en)

Cited By (4)

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US10571800B2 (en) 2015-02-03 2020-02-25 Asml Netherlands B.V. Mask assembly and associated methods
US11036128B2 (en) 2015-12-14 2021-06-15 Asml Netherlands B.V. Membrane assembly
US11320731B2 (en) 2015-12-14 2022-05-03 Asml Netherlands B.V. Membrane for EUV lithography

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040005355A (en) * 2002-07-10 2004-01-16 주식회사 하이닉스반도체 A Pellicle Seperating Type Frame Structure
US10571800B2 (en) 2015-02-03 2020-02-25 Asml Netherlands B.V. Mask assembly and associated methods
US11029595B2 (en) 2015-02-03 2021-06-08 Asml Netherlands B.V. Mask assembly and associated methods
US11086213B2 (en) 2015-02-03 2021-08-10 Asml Netherlands B.V. Mask assembly and associated methods
US11635681B2 (en) 2015-02-03 2023-04-25 Asml Netherlands B.V. Mask assembly and associated methods
US11036128B2 (en) 2015-12-14 2021-06-15 Asml Netherlands B.V. Membrane assembly
US11320731B2 (en) 2015-12-14 2022-05-03 Asml Netherlands B.V. Membrane for EUV lithography

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