JPS6126274B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an orthogonal transform decoding circuit.

Conventionally, when looking statistically at the power distribution of video signals, there are few high-frequency components, so the idea of compressing the bandwidth by reducing the number of transmission bits used for the high-frequency components has been considered. be. One example is a method using Hadamard transform as a means of converting the time domain to the frequency domain.
For example, if an 8th-order Hadamard transform is to be performed, it can be expressed as the following equation.

Here _, [x _{1 , x 2 .} This is the 8th order sequence. Moreover, [IH] is an 8th order Hadamard matrix. Figure 1 shows an example of compressing this sequence, which can be transmitted using an average of 4.5 bits. Now, if the sequence
When _h8 is linearly compressed into 3 bits and transmitted, conventionally, when the quantization step is set to 1, the lower 3 bits _b81 , _b82 , and _b83 are transmitted. That is, as shown in A of FIG. 2A, the shaded portions are the bits to be transmitted. Furthermore, as shown in A of Fig. 2b, if the quantum ratio step is 2, then b ₈₂ , b ₈₃ , b ₈₄
In some cases, 3 bits of 1 are transmitted. Furthermore, if the quantization steps are 4 and 8, then b ₈₃ , b ₈₄ , b ₈₅ , b ₈₄ , b ₈₅ ,
Transmit b ₈₆ . In this method, the transmission 3-bit area changes depending on the value of the quantization step, but this is fixed at the initial setting and does not correspond to changes in the input signal. However, the distribution of sequence _h8 is thought to vary depending on the type of image, and some images may have stronger energy than expected. Therefore, the 3 bits to be transmitted are b ₈₁ ,
If b ₈₂ and b ₈₃ are fixed, even if the value of sequence h ₈ becomes large and overflows from the lower 3 bits, only the lower 3 bits are transmitted, resulting in distortion in the reproduced signal. Furthermore, when the probability of overflow is small, it is not so noticeable on the screen, but when the probability of overflow increases, the deterioration of the screen becomes noticeable.

In order to eliminate the drawbacks of the conventional example, the present invention detects the number of overflows of each bit of each sequence in the encoding side circuit, and switches the transmission bit for each sequence.
Even if the h _i component becomes larger than the initially set value, the number of bits to be transmitted remains fixed and only the transmission area is expanded and transmission is performed, and the decoding side circuit uses information about switching the transmission bits. The present invention provides an orthogonal transform decoding circuit that can reproduce a sequence from transmitted bits using a small number of bits, and thus can obtain a reproduced image with little distortion using a small number of bits. Hereinafter, embodiments will be described in detail with reference to the drawings.

Figure 3 shows the configuration of the encoding circuit.
The video signal supplied to the input terminal 3A is encoded into parallel 8 bits by the A/D converter 301, and then
Hadamard transform circuit 302 performs Hadamard transform. Sequence _h8 obtained by Hadamard transformation
The data is held in the register 303. Here, B ₈₁ , B ₈₂ , B ₈₃ mean 3 bits to be transmitted, and in the first certain period, B ₈₁ , B ₈₂ , B ₈₃ = b ₈₁ ,
Suppose b ₈₂ and b ₈₃ . In addition, examples of how to take this fixed period include, for example, one horizontal video period or one vertical video period. Hereinafter, a case will also be explained in which a certain period is set as one horizontal video IH period. Since FIG. 3 is an example of performing the 8th order Hadamard transform, if the number of pixels in one horizontal video period is 576, there are 72 blocks in one horizontal video period. An overflow counting circuit 305 counts the number of overflows for these 72 pieces of data. The number of overflows is b _8j for each data
It is obtained by counting the number of times each bit of (j = 4 to 8) becomes "1", and if the number of times it becomes "1" is equal to or greater than the threshold value T in 1H period, the quantization step is started. An overflow counting circuit 305 generates a signal for switching. Now, when the number of times b ₈₄ = “1” is T or more and the number of times each bit of b ₈₅ to b ₈₈ is “1” is less than T, the signal for switching the quantum ratio step to 2 is activated. is generated in the overflow counting circuit 305. Similarly b ₈₅ =
If the number of times each bit becomes "1" is T times or more, and the number of times each bit of _b86 to _b88 becomes "1" is less than T times, a signal for switching the quantization step to 4 is sent to the overflow counting circuit 305. Make at. Also
Any one bit of b ₈₆ , b ₈₇ , b ₈₈ is “1”
If the number of times is T or more, the overflow counting circuit 305 generates a signal for switching the quantization step to 8. This quantization step switching signal is held until the end of the next 1H period. Therefore, the next
The switching will take place during the 1H period, but
Since the images have a strong correlation, there is no problem in practical use. This quantization step switching signal is transmitted to the coder 306.
The signals M 81 and M 82 are converted into transmission mode instruction signals M ₈₁ and M ₈₂ and inserted in the form of pulses into the blanking period. Using this quantization step switching signal, the transmission bit switching circuit 304 selects three bits B ₈₁ , B ₈₂ , M ₈₃ to be transmitted from b ₈₁ to _{b 86} . FIG. 2 is a table showing this relationship. For example, when the mode instruction signal is M ₈₁ = "1" and M ₈₂ = "0 _" , b ₈₃ , b ₈₄ , and b 85 are transmitted as B ₈₁ , B ₈₂ , and B ₈₃ . In order for this mode instruction signal to be like this, the number of times b ₈₅ = “1” is T or more,
The number of times each bit of b ₈₆ , b ₈₇ , b ₈₈ becomes “1” is T
In the case of less than 1 times. The quantization step at this time is 4, and b ₈₃ , b ₈₄ , b ₈₅ are stored in the register 303.
This shows that in order to move to the position , it is sufficient to perform a two-stage shift.

As mentioned above, although this example has been explained using the sequence _h8 , the same applies to the other sequences _h1 to _h7 , and the mode instruction signal and transmitted bits of each sequence are determined by the PCM coder 3.
07 and is transmitted from the output terminal 3B.

FIG. 4 shows the decoding circuit of the present invention, and the output of the encoding side circuit shown in FIG.
The signal is input to the PCM decoder 401 through A, and the PCM decoder 401 reproduces a clock synchronized with the transmitting side as shown in FIG. 6a. In addition, the input signal of this PCM decoder 401 is a compressed signal of h ₁ to _{h 8} processed for each block. From this signal, h ₁ to h ₈ are extracted for each block, and h 1 to h ₈ are extracted for each block. Convert _h8 to parallel signal. Further, this signal is sent to a sequence reproducing circuit 402 to obtain 8-bit reproduced Hadamard sequences h' ₁ to h' ₈ using the compressed and transmitted sequence signal and the mode instruction signal. This reproduced Hadamard sequence is subjected to Hadamard inverse transform in Hadamard inverse transform circuit 403, and the video signal is reproduced from terminal 4B through D/A converter 404.

Next, FIG. 5 shows a sequence reproducing circuit which is the gist of the present invention. First, the operation of the sequence reproducing circuit 402 will be explained. In FIG. 4, when compressed and transmitted sequence signals B ₈₁ , B ₈₂ , B ₈₃ obtained from the PCM decoder 401 and mode instruction signals M ₈₁ , M ₈₂ are received, these B ₈₁ , B ₈₂ , B ₈₃ respectively in shift register 50
1, enter this B ₈₁ , B ₈₂ ,
B ₈₃ is shifted to the position occupied in the Hadamard sequence h ₈ on the encoding side. A pulse for performing this shift is generated by converting the mode instruction signal by a decoder 515. For example, when the mode instruction signal is M ₈₁ =1, M ₈₂ =0, that is, the transmitted bits B ₈₁ , B ₈₂ , B ₈₃ = b ₈₃ , b ₈₄ , b ₈₅ , the shift register 501 is b ₈₃ , b ₈₄ , b ₈₅ in position
Insert the signal. In order to move this signal to _the position . Accordingly
The mode instruction signal of M ₈₁ =1 and M ₈₂ =0 is converted by the decoder 515 to create two shift pulses, and by inputting these pulses to the terminal S of the shift register 501, the shift register 501
The signals of b ₈₃ , b ₈₄ , b ₈₅ at positions , respectively, are shifted to the positions , and the reproduced Hadamard sequence h′ ₈ = {b′ ₈₁ , b′ ₈₂ ………b′ ₈₈ }=
{0, 0, b ₈₃ , b ₈₄ , b ₈₅ , 0, 0, 0} is obtained. Comparing this sequence of h' ₈ with the Hadamard sequence h ₈ = {b ₈₁ , b ₈₂ ......b ₈₈ } of the encoding side circuit, in h ₈ , the upper b ₈₆ , b ₈₇ , b ₈₈ are "1" The number of times that becomes is less than a certain threshold T times, so in most cases b ₈₆ = b ₈₇ = b ₈₈ =
It is “0”. Also, since the third to fifth bits are common, the error in _h'8 is only the error based on the first and second bits. On the other hand, the sequence h'' ₈ = {b ₁ , b ₂ , b ₃ , 0, 0, 0,
0, 0} is an error based on the fourth and fifth bits. Comparing the error of h ₈ and the error of h' ₈ , the error of h' ₈ is much larger. Therefore, reproduction of a signal over a wide amplitude range corresponding to changes in the operating range can be achieved with fewer errors using a smaller number of bits.

Next, a specific circuit configuration of this sequence reproduction circuit 402 will be explained. In Figure 4, PCM
The input signal of the decoder 401 is a compressed signal processed block by block, and this PCM decoder extracts h' ₁ to h' ₈ for each block from this input signal, and extracts h' 1 to h _{' 8} for each block. ’ ₈ to a parallel signal. Also, FIG. 6a of this PCM decoder 401
Using the timing of the first bit of each compressed sequence in the reproduced clock shown in , the PCM decoder 401 performs loading to the shift register and shift read processing until the output of the next block is obtained. A signal at the position of the first bit of each sequence (hereinafter this signal will be referred to as a sequence discrimination signal) is transmitted from a terminal 5L to a sequence discrimination circuit 51 by a timing pulse circuit.
6, using the regenerated clock shown in FIG. The output waveforms of terminals 5D, 5E, 5I, 5J, and 5K of this sequence discrimination circuit 516 are as shown in FIGS. 6c to 6g, respectively. Moreover, FIG. 6b shows each compressed and transmitted sequence h ₁ to _{h 8}
The mode indication signals M ₈₁ and M ₈₂ are connected to terminals 5F and 5, respectively.
G is input to the decoder 515, and its waveforms are shown in FIG. 7b and c, respectively. This mode instruction signal is input to set reset flip-flops (hereinafter abbreviated as RS-FF) 508 and 509 of the decoder 515, and is reset by the horizontal synchronizing signal shown in FIG. 7a supplied from the terminal 5H. Remain in that state until. The Q output of this RS-FF508 is shown in FIG. 7d, and the Q output of the RS-FF509 is shown in FIG. 7e. The Q outputs and outputs of these RS-FFs 508 and 509 are converted to α,
It is converted into β and γ signals, but the mode instruction signal
The relationship between M ₈₁ and M ₈₂ and the signals α, β, and γ is as shown in FIG. Further, the output waveform of the signal α is shown in FIG. 7f, the output waveform of the signal β is shown in FIG. 7g, and the output waveform of the signal γ is shown in FIG. 7h. for example,
When transmitting b ₈₃ , b ₈₄ , b ₈₅ as B ₈₁ , B ₈₂ , B ₈₃ , α=“0”, β=“1”, and γ=“1”. At this time, the number of times that any one of α, β, and γ becomes “1” is exactly the number of times that the shift register 501...
This is the number of times the signals b ₈₃ , b ₈₄ , and b ₈₅ that have entered the position are shifted to the positions b ₈₃ , b ₈₄ , and b ₈₅ in the h ₈ sequence of the encoding side circuit. Such a code conversion circuit can be easily realized by using a logic circuit, for example. Also, the signal α
The output of is gated by the AND circuit 511 with the pulse shown in FIG.
The output of the signal γ is also gated by the AND circuit 512 with the pulse shown in FIG. and gate. These three gate outputs are input to the shift terminal S of the shift register 501 through the OR circuit 514.

On the other hand, the transmitted bits of B ₈₁ , B ₈₂ , and B ₈₃ are
Shift register 5 through terminals 5A, 5B, 5C
Loading is performed using the load pulse shown in FIG. Now, the shift pulse train generated by the decoder 515 is input to the shift terminal S of the register 501, and shifts B ₈₁ , B ₈₂ , and B ₈₃ to their original positions in the Hadamard sequence h ₈ . for example,
If B ₈₁ , B ₈₂ , B ₈₃ = b ₈₂ , b ₈₃ , b ₈₄ , the data is shifted to the position of the shift register. When this shift is completed, the terminal 5 shown in FIG.
AND circuit 50 with the gate pulse supplied from E
2 to 507, 517, 518, Hadamard sequence playback output h' ₈ = {b' ₈₁ , b' ₈₂ , ......
b′ ₈₈ }. Similar processing is performed on the mode instruction signals of other sequences and the compressed and transmitted sequences to obtain Hadamard reproduction outputs h' ₁ to h' ₈ .

As explained above, according to the present invention, transmission is performed by switching the quantization step according to the input signal, so it is possible to send a signal with a wide amplitude range corresponding to changes in the operating range with a small number of bits. This makes it possible to achieve the effect of reducing image distortion during playback.Also, such a circuit can also be configured by using a gate circuit, but as the number of switching increases, the required gate circuit becomes Since the number of switches becomes very large and complicated, the circuit of the present invention uses a shift register, and has the advantage that it can be realized with a simple configuration regardless of the number of switchings.

[Brief explanation of the drawing]

Figure 1 shows an example of compressing the bits of each sequence after orthogonal transformation, and Figure 2 shows the mode indication signal, the degree of overflow of each bit, the position of the three bits to be transmitted, and the quantum FIG. 3 is an explanatory diagram of the encoding side circuit, and FIG. 4 is an explanatory diagram of the entire decoding side circuit. FIG. 5 is an explanatory diagram of the sequence reproducing circuit in the decoding circuit, and FIGS. 6 and 7 are waveform diagrams for each point in FIG. 5. 3A...Input terminal, 301...A/D converter,
302...Hadamard conversion circuit, 303...Register, 304...Transmission bit switching circuit, 30
5...Overflow counting circuit, 306...Coder, 4A...Terminal, 401...PCM decoder, 402...Sequence playback circuit, 403...
Hadamard inverse conversion circuit, 404...D/A converter, 501...shift register, 502...sequence playback circuit, 502-507...AND circuit, 508, 509...set reset flipflop, 510... Code conversion circuit, 511,5
12.513...AND circuit, 514...OR circuit, 515...decoder, 516...sequence discrimination circuit.

Claims (1)

[Claims] 1 When decoding a video signal using orthogonal transformation, when receiving from the code side a signal that switches the quantization step while keeping the number of bits transmitted in each sequence fixed, and a mode instruction signal that indicates the switching state. , consists of a decoder for converting this mode instruction signal into a shift pulse, and a shift register for holding the signal transmitted from the code side, and the shift pulse output from the decoder is added to the shift register, and each sequence is An orthogonal transform decoding circuit characterized in that each sequence is restored and reproduced by shifting it to its original position.