JPS6126151A - Buffer control method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a control method for a buffer provided in a processing unit such as a central processing unit of a computer system, and particularly to a control method that can improve the access efficiency of a sofa. Regarding improvements.

In a computer system, in order to substantially speed up access to the main memory of a central processing unit, etc., the processing unit is provided with a buffer consisting of a relatively high-speed, small-capacity storage device, and the main memory is provided with a buffer. Techniques for maintaining copies of data are widely adopted.

In a processing device with a buffer, when accessing the main memory, the buffer first searches to see if the data at the corresponding storage address is held, and if the corresponding data is found, the data on the sofa is used; For the first time,
Actual access to main memory.

However, when accessing to update data, it is necessary to update the corresponding data on the main storage device using some kind of control method.

In the so-called store-through method, which is one of the data update control methods, when data is updated, the corresponding data on the main memory is immediately updated, but if the corresponding data is in the buffer, the buffer is updated at the same time. The above data will also be updated.

In order to take full advantage of the high speed of buffers, it is necessary to process the various buffer access requests as mentioned above with as little waiting time as possible and increase the number of accesses that can be processed per hour. In other words, it is necessary to increase access efficiency as much as possible. Control is needed to enhance the results.

[Conventional technology]

FIG. 2 is a block diagram showing the configuration of a conventional buffer provided in a processing device.

The storage portion of the buffer 2 consists of a tag section 21 and a data section 22. The data section 22 basically holds information that is a copy of the data on the main storage device, and the tag section 21 holds information that is held in the data section 22. It holds information indicating the storage address in the main memory of each data block.

For this purpose, the tag section 21 and the data section 22 have the same logical configuration, and each is divided into a plurality of ways (ways 0, 1 to F in the figure), and each way consists of the same number of blocks. A block is a unit of buffer access, and each block in the tag section 21 includes an indication of the validity of the data block in the block at the corresponding position in the data section, and if it is valid, an indication on the main memory of the data block. A part of the storage address of is stored. The remaining part of the storage address is stored indirectly as the address of the block within the way.

A storage address in an access request to buffer 2 is set in effective address register (hereinafter referred to as EAR) 1. In this example, the storage addresses are 0th to 3rd.
2 of the 8th to 31st bits of a 32-bit word of 1 bit
The byte address shall be displayed in 4 bits, and E
Shown as 8-31 in AR1.

Note that, as will become clear in the following description, in other parts of each figure, numerical representations indicating bit positions with similar meanings are added where necessary.

If the block size of the data section 22 is, for example, 64 hides, 18 hints, 8th to 25th, are used to determine the data block among the 24-bit addresses.

Of these, for example, the lower 6 bits (20th to 25th bits) are assigned to each block address in the way, and the remaining 8th to 19th bits are stored in the block of the tag section 21 to determine the address. is possible.

That is, when accessing the buffer 2, one block each of all ways in the tag section 21 and data section 22 is read out using the 20th to 25th bits of EARL as an address.

If the validity display of the content read from the tag section 21 is on, the 8th to 19th bits of the address and EAR1
The comparators 23 for each way simultaneously check for coincidence with the 8th to 19th bits. The result is whether a match is detected in any one way, or a mismatch is detected in all ways.

If there is a way with a matching address, the matching output of the corresponding comparator 23 is encoded by the encoder 24 and the way number register (hereinafter referred to as WNR) 25
The way number is set.

When reading data from the buffer 2, the tag section 21
Among the data read out from each way of the data section 22 at the same time as the reading of , the data of the deaf ray specified by the WNR 25 is used as the target data.

When writing data to buffer 2, if the corresponding address is found in the above operation, the same address is written to E again.
AR1 is set to 1~, and a write sequence is started, where a write operation is executed to the block specified by the 20th to 25th bits of EAR1 in the way of the data section 22 selected by the contents of -NR25. .

As schematically shown in FIG. 3, the timing of the above write operation is constituted by two sequences consisting of three control cycles.

That is, P F c lI indicates that a read request (in this case, a read as the first half of a write operation) is selected in the access request selection cycle, and as a result, in the next 81 cycles, EAI? 1 is set, reading of the tag section 21 and data section 22 of buffer 2 is started, and the next B2
Since it is read out in cycles, when an address match is obtained in the comparator 23, WNR 25 is sent at the beginning of the next R/PST cycle.

In this cycle, if the request selected in the PPCl-1 cycle is a data read request, the raw data selected by WNR25 is transferred to this access request source (R cycle), and if the request is a data write request, the data is written. This is a cycle in which a sequence is entered (ht cycle).

As shown in FIG. 4, this circuit is configured in a pipelined manner so that when a suitable access request follows, the next requested address is stored in EAR1 during the preceding 82 cycles, as shown on lines 30 and 31. Therefore, as shown in Figure 3,
The contents of EAR1 are transferred to the B2 register 3 in the B2 cycle, and the contents are transferred to the operand' address port (hereinafter referred to as 0PAP) 4 in the next cycle (R/PST), and in this \Ps7B7 cycle, The contents of 0PAP4 are reset to EARL in the next 81 cycles, and the writing to buffer 2 is completed by cycles S1 and S2.

[Problem that the invention seeks to solve]

Looking at the relationship between multiple access requests processed at the above timing in Figure 4, as shown by lines 30, 31, and 32, even if up to three write access requests are consecutive, Processing of the next request in the cycle begins without creating a wait.

However, as from the fourth cycle shown at time 33, the fourth write or read access request on line 34 causes
When four access requests overlap, this access request becomes
Until time 35 when the number of access requests being processed becomes 2 or less,
There is a problem in that the start of processing is delayed for three cycles.

[Failure to solve the problem]

This problem has a main storage device and a processing device, and the processing device stores information in the main storage device. A computer system comprising a buffer consisting of a data section that holds a copy of data to be stored, and a tag section that holds address information of the data held in the main storage in the main storage device. The device has means for separately specifying a storage address for accessing the tag section and a storage address for accessing the data section, and is configured to independently execute an access operation for the tag section and an access operation for the data section. This problem is solved by the sofa control wholesale method of the present invention.

[Effect]

That is, in writing data to the buffer using the conventional method, in the first sequence, the tag section 21 is read out to determine whether or not the data at the corresponding address is held in the buffer 2, and if so. It is only necessary to obtain which way, and in the second sequence, it is sufficient to use the way number obtained in the first sequence to write data to the data section 22. In both cases, originally, the tag section 21 is the data section. It is sufficient to operate only one of 22.

The present invention focuses on this point, and the tag part 21 and the data part 22
By arranging that they can operate independently of each other depending on storage addresses based on separate access requests, only the tag section 21 is accessed in the first sequence, and only the data section 22 is accessed in the second sequence.

By doing so, it becomes possible to execute the first sequence of other write requests in parallel with the cycle in which the second sequence of preceding write requests is executed.

Further, although the read request simultaneously reads the tag section 21 and the data section 22 as in the past, this access can also be executed in parallel with the cycle in which the second sequence of the preceding write request is executed.

However, since it is not possible to read the write destination way at the same time, if the write and read ways collide, re-access is required, resulting in a delay in access time, and it is necessary to simplify control. Taking this into consideration, when a read request overlaps with the second write sequence, it is appropriate to use a method in which the start of processing of the read request is generally delayed by one cycle.

〔Example〕

FIG. 1 is a block diagram showing the configuration of a buffer according to an embodiment of the present invention. The diagram shows the part corresponding to the conventional example in Figure 2.
Identical components are given the same reference numerals. Further, the B2 register 3 and 0PAP 4 are connected to EAR as shown in FIG. 3, as in the conventional case.

According to the invention, a selector 28 is added to the buffer 2. The selector 28 has a function of switching the block selection input line 42 of the data section 22 and connecting it to the address line 40 from the 20th to 25th hits of EAR1 or the address line 41 from 0PAP4.

The selector 28 provides write access to the data section 22, that is, P
, 7 cycles, in which case during the S1 cycle the address line 41 is connected to the block selection input line 42 to
The 25 bits specify the block in which the data of the data section 22 is to be written.

In other cases, the 20th to 25th bits of EAR1 are used to specify blocks between the data section 22 and the tag section 21.

FIG. 5 (al and fbl indicate the timing of this embodiment).

In this embodiment, when selecting an access request, it is necessary to distinguish between the first sequence of write requests and a read request, so the cycle for selecting the former is set to PCII, and the latter is set to PFCH as in the conventional case.

FIG. 5 (al indicates the case where write requests are processed continuously; four requests overlap at time 50, but at 81, S2 cycle of the first request on line 51, the data part is processed by the address from 0PAP 4. Since the 81, B2 cycle of the fourth request on line 52 is executed in tag section 21 by the address from EAR1, parallel processing is possible.

FIG. 5(b) shows parallel processing of a second sequence of write requests and a read request; when a read request, indicated by line 54, is issued at time 53, the second sequence of writes, indicated by line 55, is in progress at the same time. is executed in the data section 22 by the address in 0PAP 4, the request on line 54 starts l cycles later, and from time 56 at the end of 31 cycles on line 54, the read request address on EARl is sent to the tag section 21 and the data section. 22 to proceed with the processing of the read request.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the usage efficiency of the buffer of a processing device in a computer system is improved, so that there is a significant industrial effect in that the performance of the processing device can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a buffer according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a conventional buffer, and FIG. 3 is a block diagram showing the configuration of a conventional buffer.
The figure is a buffer control timing diagram, and FIGS. 4 and 5 are diagrams showing timing between access requests. In the figure,

Claims (3)

[Claims] (1) It has a main storage device and a processing device, and the processing device has a data section that holds a copy of the data stored in the main storage device, and a storage of the data held in the data section in the main storage device. In a computer system having a buffer consisting of a tag part holding address information, the computer system has means for separately specifying a storage address for accessing the tag part and a storage address for accessing the data part, and 1. A buffer control method, characterized in that the buffer control method is configured to independently execute an access operation and an access operation of the data section. (2) In the write access request to the buffer, the storage address specifying means specifies the storage address of the write access request in the tag section, and then specifies the storage address in the data section in a different control cycle. However, in a data read access request, the storage address of the read access request is specified in the tag part and the data part at the same time. Buffer control method. (3) Regarding the two data write access requests to the buffer, the storage address specifying means specifies one storage address of the write access request to the tag section and the other of the write access request to the data section. 2. The buffer control method according to claim 2, wherein the buffer control method is configured to specify the storage address of the buffer in the same control cycle.