JPH0385636A - Instruction advance control device - Google Patents

Abstract

PURPOSE:To reduce the hardware quantity of a work register group by providing a discriminating means to discriminate in what work register a calculation result was stored and a control means to control the storage of the calculation result to the work register group by a first-in-first-out method. CONSTITUTION:In the case where advance calculation was executed, control information to show in which work register between two work registers 109 and 110 data was stored is carried about by registers 112 to 115, and the outputs of OR gates 204 and 205 show respectively that the work registers 109 and 110 store effective advance results. Then, in respect of the work register storing the older advance calculation result between the work registers 109 and 110, the advance calculation result stored in it before is deleted and the new calculation result of the advance calculation is stored by AND gates 207 to 213, a selector 310, and the OR gate 215, 216. Thus, the hardware quantity of the work register can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an instruction advance control device used in an information processing system.

Prior Art In a conventional information processing system, the number of operations specified by a register setting instruction is taken in before being sent to an instruction execution device, and a logical or arithmetic operation is performed on the number of operations. The arithmetic device generates write data to the register that should be obtained by executing the register setting instruction without waiting for the completion of execution by the instruction execution device.

The work register that stores the calculation results of this calculation unit is
There are as many registers as there are registers that may be specified by register setting instructions. For this reason, many registers have the drawback of increasing the amount of hardware required to hold valid data.

OBJECTS OF THE INVENTION It is an object of the present invention to provide an instruction advance control device which reduces the amount of work register space.

Composition of the Invention The instruction advance control device according to the present invention provides, when a register setting operation of a register setting instruction conflicts with a read operation of another instruction, before sending the number of operations specified by the register setting instruction to the instruction execution device. arithmetic means for generating write data to a register to be obtained by executing the register setting instruction without waiting for completion of execution of the instruction execution device by performing an operation on the arithmetic operation number, and by executing the register setting instruction; an address generating means for calculating an address for an instruction that requires write data to be obtained; and a plurality of works for storing the calculation results of the calculating means in a smaller number than the number of registers used for the address calculation performed by the address generating means. register means; discriminating means for determining which register means the operation results stored in these work register means correspond to; The invention is characterized in that it includes a control means for controlling.

Embodiment Next, an embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention includes a software-visible pace register file (BR) 401 that stores pace addresses for address generation, and a pace register address register that stores addresses for this pace register file 401. (BRA) 10
0, a software-visible index register file that stores indexes for address generation (
GR) 402, index register address register 01 that stores the address for this index 1 register file 402, displacement register 102 that stores the displacement selected from the instruction word, register 05 that stores the displacement from this index 1 register 102. , work registers 09 and 110 that store the calculation results, a selector 300 that selects any one of the outputs from these work registers (09 and 110 and the pace register 401, work registers 09 and l1.0, and the index register 402). A selector 301 that selects one of the outputs of , a register 03 that stores the output of the selector 300, and a register 04 that stores the output of the selector 301.
, these registers 03. Address generator 400 that calculates outputs from +04 and 105 and generates a logical address
, a logical address register 106 that stores the logical address generated by this address generator 400, an address translation buffer (hereinafter referred to as TLB) 403 that converts the logical address from this register 06 into a physical address, and this T L
Physical address register 07 that stores the physical address from B 408, cache memory 404 that reads the operand from the location indicated by the address from this register 07, operand register 08 that stores the operand from this cache memory 404, this register Operands from 08 and pace register 40
1 and an arithmetic logic unit (hereinafter referred to as ALU) 405 that stores calculation results in an index register 402 .

Furthermore, an embodiment of the present invention is based on the premise that the above hardware elements are operated in a pipeline, and in response to a register update instruction, the register number of the register to be updated is rotated in synchronization with the pipeline. register group 119,
118, 117 and 116, registers 12 and 11 that have control information indicating which of the two work registers 09 and 110 data was stored in the preceding calculation;
3.114 and 115. Registers 119, 118, 11
OR gates 200, 201, 202, and 203, which generate a signal indicating that the preceding operation result is stored in either work register 09 or 110, for the register indicated by the register number stored in 7 and 11B; Registers (19 and Ill) generate a signal indicating a valid pre-operation result.
including.

The above pipeline will be explained in detail below.

In the D cycle, in order to generate an address, registers 401 and 402 indicated by part of the contents of the index field of the instruction word stored in address registers 100 and 101 are indexed, and the contents of the displacement field 102 of the instruction word are indexed. This is the cycle to be retrieved.

However, RI that does not issue a load request to memory
In the case of a format, etc., the contents of the register to be operated on and the immediate value are retrieved.

In the A cycle, the pace register 401. which was taken out in the D cycle. The contents of the index register 402 and the displacement unit 102 are stored in the address generator 40.
Address generation is performed by generating 0.

However, R1 does not issue a load request to memory.
In the case of a format, etc., calculations are performed in advance using the contents of the register and the imide and f-eight values.

The results of this operation are stored in work registers 109 and 11 (l) in response to the outputs of OR gates 215 and 216. Hereinafter, this operation will be referred to as a preceding operation.

The T cycle is a cycle in which the operand address generated in the A cycle is converted into a physical address by the TLB 403.

The 0th cycle is a cycle in which the cache memory 404 is indexed using the physical address of the operand generated by the T L B 403 in the T cycle to obtain operand data.

In the E cycle, an operation is performed using the operand data indexed in the O cycle and stored in the register files 401 and 402.

One embodiment of the present invention is provided with two work registers 109 and 110 for storing the results of previous operations.

In response to the generation of a register update instruction, the register number of the register to be updated is changed to register 1 in synchronization with the bypass line.
Rotated between 18 and 119.

When a preliminary operation is performed, control information indicating which of the two work registers 109 and 110 data is stored is carried by registers 12 to 115.

Since there are two work registers 09 and 1.10, registers 112-115 are each filled with 2 bits. When the preceding operation result is stored in the work register 09, 1'' is stored in the first bit of each of the 17 registers 112 to 115, and when the result is stored in the work register 110, the second bit of each register is 1” is stored in the th bit.

The outputs of the OR gates 200 to 203 are from each register 19°118.117. and tte indicates that the preceding operation result is stored in either work register 09 or 110 for the register with the register number indicated by tte.

The outputs of OR gates 204 and 205 indicate that work registers 109 and 110, respectively, store valid previous results.

When a preliminary operation is performed, the operation result is stored in the work register 10.
Whether to write to 9 or (10) is controlled as follows.

When the output of the OR gate 204 indicates 0'', the work register 109 does not store a valid result of the preceding operation, so the result of the preceding operation is stored in the work register 109.

If the output of OR gate 204 is "1" and the output of OR gate 205 is "0", work register +09 stores a valid pre-operation result, but work register 110
does not indicate a valid predecessor result. Therefore, the result of the preceding calculation is stored in the work register 104.

If AND gate 21.4 is 1°, it means that work registers 109 and 110 are both storing valid pre-operation results.

If a preceding operation occurs in this state, and get 207~
213, selector 310 and or game 1-215 and 2
16, in the work registers 109 and 110,
In the work register storing the older preceding operation result, the already stored preceding operation result is erased and the new operation result of the preceding operation is stored.

] 0 This is because the instruction for which the pre-operation was performed first should be lower in the pipeline, so even if the pre-operation result is erased, the update data will be more accurate than the ALU 405 in the E stage. This is because files 401 and 402 are returned immediately, so the impact is small.

In the D stage, the register numbers of the registers necessary for address generation stored in registers 100 and 101 are compared with the contents of registers 119, 118, 117, and 6, respectively. If they do not match, the outputs of register files 400 and 401 are set in registers 103 and 104. It was a match but or gate 2
If it is determined by 00 to 203 and the AND gates 217 to 220 that the preceding operation results are stored in the work registers 109 and 110, the work register 109
Alternatively, the work registers storing the required preliminary operation results in 110 are set in registers 103 and 104 by instructions from comparison circuits 302 to 305, OR circuits 200 to 208, AND circuits 217 to 220, and selector 310. .

Furthermore, the contents of registers 100 and +01 are compared with the contents of registers 111 9, 118, 117 and 116, and if they match and the result of the preceding operation is not preceding, the AL
Address generation is interrupted from U405 until update data is written to registers necessary for address generation in register files 401 and 4 (12).

When an update instruction is issued to a register having the same register number as the register number of the register on which the preceding operation was performed by the register update instruction of the subsequent instruction, the comparison circuits 306 to 3
Register 112 for erasing the preceding operation result by 09.
~11.5 are initialized respectively.

In this way, the result of the preceding operation is stored in the work register 109.
and 110, and the work register hardware for storing the preceding operation results by controlling the storage of the preceding operation results in the work registers 19 and 110 using a first-in, first-out method. The amount of wear can be reduced.

Effects of the Invention According to the present invention, the number of operations specified by the register setting instruction is taken in before being sent to the instruction execution device, logical operations and arithmetic operations are performed on the number of operations, and this register setting instruction is executed. A discriminating means for determining in which work register the operation result of the arithmetic unit which generates the write data to be obtained by performing the write data before the execution of the execution unit is stored, and an operation for the work register group. By providing a control means for controlling the storage of results in a first-in, first-out manner, there is an effect that the amount of hardware in the work register group can be reduced.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention. Explanation of symbols of main parts too...Pace register address register B
RA 101... Index register address register GRA 1 [12... Displacement register D
ISP 106...Logical address register 107...
... Physical address register 108 ... Operand register + (19, 1, io ... Work register 3 02 to 309 00 01 02 03 04 05 ... Comparison circuit ... ... Address generator ... Pace register file BR ...
Index register file GR ・・・・・・Address translation buffer TLB・・・・・・
Cache memory・・・・・・Arithmetic logic unit

Claims (1)

[Claims] (1) If the register setting operation of a register setting instruction conflicts with the read operation of another instruction, the operation number specified by the register setting instruction is fetched before being sent to the instruction execution device, and the operation is performed on the operation number. an arithmetic unit that generates write data to a register that should be obtained by executing the register setting instruction without waiting for completion of execution of the instruction execution device; address generation means for calculating the address of an instruction to be executed; a plurality of work register means for storing the calculation results of the calculation means in a number smaller than the number of registers used for the address calculation performed by the address generation means; An instruction advance control device comprising: a determining means for determining whether the operation is being stored; and a control means for controlling the storing of the operation result in the work register means in a first-in, first-out manner.