JPS61258533A - Amplitude variable da conversion integrated circuit - Google Patents
Amplitude variable da conversion integrated circuitInfo
- Publication number
- JPS61258533A JPS61258533A JP10075285A JP10075285A JPS61258533A JP S61258533 A JPS61258533 A JP S61258533A JP 10075285 A JP10075285 A JP 10075285A JP 10075285 A JP10075285 A JP 10075285A JP S61258533 A JPS61258533 A JP S61258533A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- integrated circuit
- circuit
- amplitude
- ladder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、各種アナログ信号出力を必要とするＤ ／
Ａ変換回路における振幅可変型Ｄ／Ａ変換集積回路に関
する。[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to D/
The present invention relates to a variable amplitude D/A conversion integrated circuit in an A conversion circuit.
本発明は、各榴アナログ信号出力な必要とする振幅可変
型Ｄ／Ａ変換集積回路において、抵抗とアナログスイッ
チとからなるラダー回路に、第一の抵抗を追加し、出力
端子と電源間に挿入した第二の抵抗の大小によって、Ｄ
／Ａ変換回路の振幅を容易に可変できるものである。The present invention adds a first resistor to a ladder circuit consisting of a resistor and an analog switch in a variable amplitude D/A conversion integrated circuit that requires analog signal output, and inserts the first resistor between the output terminal and the power supply. Depending on the magnitude of the second resistance, D
The amplitude of the /A conversion circuit can be easily varied.
従来のＤＡ変換集積回路のアナログ出力の振幅調節は、
第２図に示す様に、カウンタ２５．デコーダ２４．ラダ
ー回路２５．バンドパスフィルタ、 （以下ＢＰＦ ）
２６に振幅調節用ボリウム２７を接続した手段か、第６
図に示す様に、振幅調節用ボリウムの代替として、演算
増幅器３１の帰還抵抗３３の大小Ｇこ依る手段が知られ
ていた。The amplitude adjustment of the analog output of the conventional DA conversion integrated circuit is
As shown in FIG. 2, the counter 25. Decoder 24. Ladder circuit 25. Bandpass filter (hereinafter referred to as BPF)
26 with an amplitude adjusting volume 27, or the sixth
As shown in the figure, as an alternative to the amplitude adjusting volume, a method that depends on the magnitude G of the feedback resistor 33 of the operational amplifier 31 has been known.
〔発明が解決しようとする問題点及び目的〕しかし、従
来のＤＡ変換集積回路の出力振幅可変手段は、第２図で
は、出力レベルの大小に応じてインピーダンスが変化す
る為、次段の回路に対する影戦２が大きぐ（次段の入力
インピーダンスに依って出力レベルが変化する）、又、
第６図では演算増幅器を挿入する為に消費電力が増加す
るという問題点を有していた。[Problems and objects to be solved by the invention] However, the output amplitude variable means of the conventional DA conversion integrated circuit, as shown in FIG. 2, changes in impedance depending on the magnitude of the output level. Shadow battle 2 is large (the output level changes depending on the input impedance of the next stage), and
In FIG. 6, there is a problem in that power consumption increases due to the insertion of an operational amplifier.
そこで、本発明は、従来のこのような問題点を解決する
為、ＤＡ変換集積回路の出力インピーダンスを変動させ
ることなく、出力レベルを容ＪＡＡＺＷ、４節すること
を目的としてし）る。Therefore, in order to solve these conventional problems, the present invention aims to increase the output level without changing the output impedance of the DA conversion integrated circuit.
上記問題点を解決するために、ＤＡ変換回路の抵抗ｙア
ナログスイッチとからなるラダー回路の一方を第１の電
源に接続し、他方を第一の抵抗を介して第二の電源に接
続する経路と制御入力端子から第二の抵抗を介して該第
２の電源に接続することを特徴とする。In order to solve the above problem, we created a path in which one side of a ladder circuit consisting of a resistor and an analog switch of the DA conversion circuit is connected to the first power supply, and the other is connected to the second power supply via the first resistor. and a control input terminal connected to the second power source via a second resistor.
上記のように構成された振幅可変ＤＡ変換集積回路は、
制御入力端子とＶＤＤ間に挿入された第二の抵抗の増減
（開放または短絡でも可）に依って、ラダー回路への′
市原を制御し、アナログ出力の振幅を容易にｎ’Ｊ ｆ
ｆｉ’Ｊ可能とするものである。The variable amplitude DA conversion integrated circuit configured as described above is
By increasing or decreasing the second resistor (open or short-circuited) inserted between the control input terminal and VDD, the
Ichihara controls the amplitude of the analog output easily.
fi'J is possible.
以下に本発明の実施例を図面Ｇこもとづいて説明する。 Embodiments of the present invention will be described below with reference to Drawing G.
第１図においてラダー抵抗３〜９によってそれぞれ重み
づけされた各ラダー抵抗の接続点は、レベル選択用アナ
ログスイッチを介してＤＡ出力２１に接続されている。In FIG. 1, the connection points of the ladder resistors weighted by the ladder resistors 3 to 9 are connected to the DA output 21 via a level selection analog switch.
またラダー抵抗９は第一の電源１０に、一方ラダー抵抗
３は、勲負荷詩振幅決定用抵抗１を介して第二の電源１
９へ、また制御入力端子２０を経由し、振幅決定用抵抗
２を介して第二の電源１９へと接続されている。第１図
からも明らかな様に、アナログ信号出力２１の波形のピ
ーク電圧をＶ。Further, the ladder resistor 9 is connected to the first power source 10, while the ladder resistor 3 is connected to the second power source 1 via the load amplitude determining resistor 1.
9, and via a control input terminal 20 and an amplitude determining resistor 2 to a second power source 19. As is clear from FIG. 1, the peak voltage of the waveform of the analog signal output 21 is V.
、抵抗１をＲ１ｅ抵抗２をＲＬ 、ラダー抵抗の合計を
ＲＴ 、電源電圧をＶｃｃとするとｖｏ＝Ｖｃｃ＊（
ＲＴ／Ｒ１／／ＲＬ＋ＲＴ）となることがらＲＬを変化
させることにより、■０が変化することが容易に理解で
きる。, resistor 1 is R1e, resistor 2 is RL, total ladder resistance is RT, power supply voltage is Vcc, then vo=Vcc*(
RT/R1//RL+RT), so it can be easily understood that by changing RL, ■0 changes.
なお、抵抗１については、制御入力端子が開放時に、ア
ナログ出力電圧を決定する為のものである。ここでは、
抵抗１及び２が第二の電源側に挿入されたケースでも同
様で、またラダーのビット数に制限のないことは言うま
でもない。Note that the resistor 1 is used to determine the analog output voltage when the control input terminal is open. here,
The same applies to the case where resistors 1 and 2 are inserted on the second power supply side, and it goes without saying that there is no limit to the number of bits in the ladder.
第４図は、本発明にかかるラダー回路を採用した振幅可
変ＤＡ変換回路の実施例を示すもので非常に容易にアナ
ログ出力の振幅が調節できる。FIG. 4 shows an embodiment of a variable amplitude DA converter circuit employing a ladder circuit according to the present invention, which allows the amplitude of the analog output to be adjusted very easily.
本発明は、以上説明したように、ラダー回路と電源間に
一本の抵抗を追加し、別途一本のレベルｉｔｌ！ ｆＥ
ｊ用抵抗を変化させることにより、次段の入力回路にま
ったく影響を与えない様な、また外付部品、消費電力の
大巾な増加なしに、容易にアナログ出力振幅を調節する
ことが可能であり、特に出力振幅を正確に調節する８装
のあるデータ伝送用モデムの変調回路に応用した場合、
特に大きな効果が期待できる。As explained above, in the present invention, one resistor is added between the ladder circuit and the power supply, and one additional level itl! fE
By changing the resistor for j, it is possible to easily adjust the analog output amplitude without affecting the next stage input circuit at all, and without significantly increasing external components or power consumption. Yes, especially when applied to the modulation circuit of a data transmission modem that has eight circuits that accurately adjust the output amplitude.
A particularly large effect can be expected.
第１図（α）は、本発明にかかる振幅可変ＤＡ変換集積
回路の実施例を示す回路図。第１図（ｈ）は、アナログ
信号２１の波形図、第２図、第３図は従来のＤＡ変換集
積回路の振幅可変手段を示す回路図であり、第４図は、
この発明にかかるラダー回路を採用した実施例を示す回
路図である。
１・・・・・・無負荷時振幅決定用抵抗２・・・・・・
本発明にかかる振幅決定用抵抗５〜９・・・・・・ラダ
ー回路分割抵抗１０・・・・・・接地電源
１１〜１８・・・・・・ラダー回路レベル選択アナログ
スイッチ
１９・・・・・・（＋）電源
２０・・・・・・本発明にかかる制御入力端子２１・・
・・・・本発明にかかるラダー回路出力２２°°°°°
°デイジタル入力端子
２３・・・・・・カウンタ回路
２４・・・・・・ラダー回路アナログスイッチ選択用デ
コーダ
２５・・・・・・従来のラダー回路
２６・・・・・・４］調波低減ＢＰ’Ｆ２７．３３・・
・・・・従来の振幅調節用抵抗２８．３４・・・・・・
従来のＤＡ変換出力端子３１・・・・・・従来の振幅１
．’Ｊ節用演算増幅器６２・・・・・・演算増幅器の基
準抵抗（Ｒ８）３７・・・・・・振＄ｉ、ｉ調節用抵抗
接続端子４１・・・・・・本発明によるラダー回路４２
・・・・・・本発明によるＤＡ変換出力以 上FIG. 1 (α) is a circuit diagram showing an embodiment of a variable amplitude DA conversion integrated circuit according to the present invention. FIG. 1(h) is a waveform diagram of the analog signal 21, FIGS. 2 and 3 are circuit diagrams showing amplitude variable means of a conventional DA conversion integrated circuit, and FIG.
FIG. 1 is a circuit diagram showing an embodiment employing a ladder circuit according to the present invention. 1... Resistor for determining amplitude at no load 2...
Amplitude determining resistors 5 to 9 according to the present invention...Ladder circuit dividing resistor 10...Ground power supplies 11 to 18...Ladder circuit level selection analog switch 19... ...(+) power supply 20... control input terminal 21 according to the present invention...
...Ladder circuit output 22°°°°° according to the present invention
°Digital input terminal 23...Counter circuit 24...Ladder circuit Decoder for analog switch selection 25...Conventional ladder circuit 26...4] Harmonic reduction BP'F27.33...
...Conventional amplitude adjustment resistor 28.34...
Conventional DA conversion output terminal 31...Conventional amplitude 1
．． 'J-node operational amplifier 62...Reference resistor (R8) of the operational amplifier 37...Vibration $i, i adjustment resistor connection terminal 41...Ladder circuit 42 according to the present invention
......DA conversion output according to the present invention or more
Claims (1)
号により、アナログ出力信号を生成するＤＡ変換集積回
路において、前記ＤＡ変換集積回路の抵抗とアナログス
イッチとからなるラダー回路の一方を第１の電源に接続
するとともに、該ラダー回路の他方を、第一の抵抗を介
して第二の電源に接続する経路と、第二の振幅可変用抵
抗を介して第２の電源に接続する経路とを具備した振幅
可変ＤＡ変換集積回路。(1) In a DA conversion integrated circuit that generates an analog output signal based on a digital input signal taken in from a signal input terminal, one of the ladder circuits consisting of a resistor and an analog switch of the DA conversion integrated circuit is connected to the first power source. and a path that connects the other side of the ladder circuit to the second power source via the first resistor, and a path that connects the other end of the ladder circuit to the second power source via the second variable amplitude resistor. Variable amplitude DA conversion integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10075285A JPS61258533A (en) | 1985-05-13 | 1985-05-13 | Amplitude variable da conversion integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10075285A JPS61258533A (en) | 1985-05-13 | 1985-05-13 | Amplitude variable da conversion integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61258533A true JPS61258533A (en) | 1986-11-15 |
Family
ID=14282251
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10075285A Pending JPS61258533A (en) | 1985-05-13 | 1985-05-13 | Amplitude variable da conversion integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61258533A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5691721A (en) * | 1994-09-30 | 1997-11-25 | Lg Semicon Co., Ltd. | Digital/analog converter having separately formed voltage dividing resistance regions |
| JP2011114514A (en) * | 2009-11-26 | 2011-06-09 | Yuhshin Co Ltd | Digital/analog conversion circuit |
-
1985
- 1985-05-13 JP JP10075285A patent/JPS61258533A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5691721A (en) * | 1994-09-30 | 1997-11-25 | Lg Semicon Co., Ltd. | Digital/analog converter having separately formed voltage dividing resistance regions |
| JP2011114514A (en) * | 2009-11-26 | 2011-06-09 | Yuhshin Co Ltd | Digital/analog conversion circuit |
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