JPS6125256B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in level shift circuits using transistors.

FIG. 1 is a circuit diagram showing a conventional level shift circuit. In Figure 1, υ ₁ is the input voltage, ν ₂
is the input voltage, Q is the transistor, R ₁ is the reference resistor, and R ₂ is the multiplier resistor.

In the level shift circuit having the above configuration, the current flowing through the reference resistor R ₁ is (υ _BE /R ₁ ), which is constant in terms of direct current (υ _BE is the base-emitter voltage of the transistor Q). Since the base current of transistor Q is small, if it is ignored, the input voltage υ
The difference between the output voltage _{υ 1} and the output voltage υ ₂ , that is, the level shift voltage υ _s , can be expressed by the following equation (1).

υ _s = (R ₁ + R ₂ )・υ _BE /R ₁ (1) Therefore, by setting the reference resistance R ₁ and multiplier resistance R ₂ in equation (1) to appropriate values, the level of the desired voltage can be shifted. .

FIG. 2 is a diagram showing an equivalent circuit of the conventional level shift circuit shown in FIG. 1, and the same elements as in FIG. 1 are given the same reference numerals. In Figure 2, r
_x is the base spreading resistance, rπ is the base-emitter resistance, rθ is the collector resistance, Cμ is the collector-base capacitance, g _n υ _c π is the dependent current source due to the base-emitter capacitance Cπ, and Z ₁ is the equivalent circuit of It is impedance.

Of the above configurations, _the base spreading resistance _r
and the multiplier resistor R2 are extremely large compared to _R2 , so they can be omitted, so the equivalent circuit shown in FIG.
It can be further simplified as shown in the figure.

Therefore, impedance Z ₁ can be expressed as (2) below.

Z ₁ =α ₁・(S+ω ₁ )/(S+ω ₂ )(S+ω
₃ ) (2) However, in the above equation (2), α, ω ₁ , ω ₂ and ω ₃ are as shown in the following equations (3) to (6). Note that “R _P ” in equations (4) and (6) above is R ₁・rπ/(R ₁ +r
π)”.

α ₁ = Cμ+Cπ/Cμ+Cπ (3) ω ₁ =R _P +R ₂ /R _P・R ₂ (Cμ+Cπ)(4
) ω ₂ =1/R ₂・Cμ (5) ω ₃ =1+gm・R _P /R _P・C _P (6) The frequency characteristics of the absolute value of the impedance Z ₁ shown in the above equation (2) are roughly shown in Figure 4. The shape is shown in . Furthermore, the fourth
In the figure, ₁ , ₂ , _{and 3} are each ω1/2
π, ω2/2π, ω ₃ /2π, and the solid line is ω ₁ <
In the case of ω ₂ , the dashed line indicates the case of ω ₂ . Therefore, for example, in order to flatten the frequency characteristic of the gain between the input and output of the conventional level shift circuit shown in FIG. Z ₁ is α ₁ /(S
+ω ₃ ). To do this, the collector-base feedback capacitance Cμ, the base-emitter capacitance Cπ, the base-emitter resistance rπ, etc. can be changed by changing the multiplier resistor R ₂ or by changing the transistor Q. However, the method described above There is a drawback that the characteristics change, and the method described above also has the drawback that it takes time and effort to find a suitable transistor. In particular, when incorporating the level shift circuit into an LSI, changing the characteristics of each transistor would be difficult to design and manufacture, so the above method could not be implemented. For this reason, the conventional level shift circuit has the disadvantage that desired frequency characteristics cannot be obtained.

In order to eliminate the above-mentioned drawbacks, the present invention connects a capacitor to at least one of the collector-base and base-emitter of the transistor, and will be described in detail below with reference to the drawings.

FIG. 5 is a circuit diagram showing an embodiment according to the present invention,
FIG. 6 is a diagram showing the frequency characteristics of the embodiment shown in FIG. 5, and the same elements as in FIGS. 1, 2, and 3 are given the same reference numerals. In FIGS. 5 and 6, C ₁ is the capacitance of the capacitor connected between the collector and base of the transistor Q (hereinafter referred to as the first capacitor capacitance), and Z ₂ is the impedance.

The level shift voltage υ _s of the embodiment with the above configuration can be obtained from the above equation (1), and therefore the reference resistance
The level can be shifted to a desired voltage by selecting the values of R ₁ and multiplier resistor R ₂ . Also, the impedance Z ₂ is as described in (3) above.
It can be calculated by replacing the collector-base feedback capacitance Cμ in equations (5) to (C ₁ +Cμ), as shown in equation (7) below.

Z ₂ =α ₂・(S+ω ₄ )/(S+ω ₅ )(S+ω
₃ ) (7) However, in the above equation (7), ω ₃ becomes as shown in the above equation (6), and α ₂ , ω ₄ and ω ₅ become as shown in the following equations (8) to (9). Become. Note that R _P =R ₁・rπ/(R ₁
+rπ).

α ₂ =C ₁ +Cμ+Cπ/(C ₁ +Cμ)・Cπ
(8) ω ₄ =R _P +R ₂ /R _P・R ₂・(C ₁ +Cμ+
Cπ) (9) ω ₅ =1/R ₂・(C ₁ +Cμ) (10) Also, since the base-emitter capacitance Cμ is much larger than the collector-base capacitance Cμ, the first capacitor capacitance C ₁ is By making it sufficiently smaller than the base-emitter capacitance Cπ, ω ₄ ≒ω ₁ . Therefore, by changing the first capacitor capacitance C ₁ , ω ₅ shown in the above equation (10) can be changed.
For example, by selecting a capacitance such that ω ₄ =ω ₅ , a flat frequency characteristic up to frequency ₃ can be obtained as shown by the solid line in FIG. The first capacitor capacity C ₁ in this case is as follows
(11) is obtained.

C ₁ =R _P /R ₂ Cπ−Cμ (11) Therefore, the above embodiment has R _P・Cπ>R ₂・Cμ
It is effective when (broken line in Figure 6).

FIG. 7 is a circuit diagram showing another embodiment according to the present invention, and FIG. 8 is a diagram showing the frequency characteristics of the circuit shown in FIG. 7. The same elements as in FIGS. Attach. In Figures 7 and 8, C ₂
is the capacitance of the capacitor connected between the base and emitter of the transistor Q (hereinafter referred to as the second capacitor capacitance), and _Z3 is the impedance.

The embodiment of the above configuration is effective when R _P・Cπ<R ₂・Cμ (broken line in FIG. 8), and the embodiment shown in FIG. 5 satisfies the above equations (3) to (5). The difference is that the collector-base feedback capacitance Cμ is replaced with (C ₁ +Cμ), while the base-emitter capacitance Cπ is replaced with (C ₂ +Cπ). In this case, when the second capacitor capacitance C ₂ is set to the value of the following equation (12), a flat frequency characteristic can be obtained up to frequency ₆ shown in the following equation (13).

C ₂ =R ₂ /R _P Cμ−Cπ (12) ₆ =Cπ/Cπ+C ₂・₃ (13) In the embodiment shown in FIG. 5, the first capacitor capacity is extremely small (on the order of several PF). This is often enough. Therefore, for example, the embodiment shown in FIG. 5 can be made into a 1-nap IC, and
Further, if the present invention is implemented in the modulation/demodulation circuit shown in FIG. 9, there is an advantage that when the modulation/demodulation circuit is made into an LSI, no external capacitor is required, and its terminals are also not required. In FIG. 9, Q ₁ to _{Q 15} are transistors, R ₃ to _{R 16} are resistors, C ₃ to _{C 5} are capacitors, and VR
is a variable resistor, T ₁ to T ₁₄ are terminals, ₁ is a DC amplifier circuit, 2 is a multiplier circuit, and ₃ is a level shift circuit. After amplification, the level shift circuit 3 lowers the DC potential and outputs it to the multiplier circuit 2. The multiplier circuit 2 multiplies the modulated and demodulated signal by the carrier signal input from the terminals _T13 and _T14 . ₁₁ and _T12 to obtain modulation and demodulation output.

Note that the present invention is not limited to the above-mentioned embodiments; for example, it is also possible to obtain a flat frequency characteristic by connecting capacitors between the collector and base and between the base and emitter of the transistor, or to obtain a frequency characteristic other than flat depending on the specifications. It is also possible to obtain desired frequency characteristics.

As explained above in detail, according to the present invention, a small capacitor is simply connected between the collector and base and at least one between the base and emitter of the transistor, so the desired frequency can be obtained without changing the DC characteristics. There is an effect that can be done.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a conventional level shift circuit, Figure 2 is an equivalent circuit diagram of the level shift circuit shown in Figure 1, and Figure 3 is a simplified equivalent circuit diagram of the equivalent circuit shown in Figure 2. , FIG. 4 is a diagram showing the frequency characteristics of the level shift circuit shown in FIG. 1, FIG. 5 is a circuit diagram showing an embodiment of the present invention, and FIG. 6 is a diagram showing the frequency characteristics of the embodiment shown in FIG. 5. 7 is a circuit diagram showing another embodiment of the present invention, FIG. 8 is a diagram showing frequency characteristics of the circuit shown in FIG. 7, and FIG. 9 is a diagram showing frequency characteristics of the circuit shown in FIG.
The figure is a circuit diagram showing a modulation/demodulation circuit using an embodiment according to the present invention. υ ₁ ... Input voltage, υ ₂ ... Output voltage, Q,
Q ₁ ~ Q ₁₅ ... Transistor, R ₁ ... Reference resistance, R ₂
...Magnification resistance, R ₃ ~ R ₁₆ ... Resistance, Z ₁ , Z ₂ , Z ₃ ...
...Impedance, C...Collector terminal, B...
Base terminal, E... emitter terminal, r _x ... base spread resistance, rπ... base emitter resistance,
r _p ... Collector resistance, Cμ... Collector-base feedback capacitance, Cπ... Base-emitter capacitance, gmυ _c π... Dependent current source, υ _BE ... Base...
Voltage between emitters, C ₃ to C ₅ ... Capacitor, VR...
…variable resistance, T ₁ to T ₁₄ …terminals. 1... DC amplifier circuit, 2... Multiplier circuit, 3... Level shift circuit.

Claims (1)

[Claims] 1. A resistor R ₂ and a resistor between the collector and base and between the base and emitter of the transistor, respectively.
In a level shift circuit using a two-terminal network connected to R ₁ , a capacitor C ₁ or a capacitor C ₂ having a value of the following formula is connected to at least one of the collector and base or base and emitter of the transistor, respectively. A level shift circuit characterized in that: C ₁ =R ₁ ·rπ/R ₁ +rπ·Cπ/R ₂ −Cμ C ₂ =R ₁ +rπ/R ₁ ·rπ·R ₂ Cμ−Cπ where rπ: Transistor base-emitter resistance Cπ: Transistor base-emitter capacitance Cμ: Transistor collector-base capacitance.