JPH05315888A - Phase shift circuit - Google Patents

Abstract

PURPOSE:To reduce noise or the like by forming the phase shift circuit with combination of a mutual conductance of a transistor(TR) and a capacitor so as to apply variable control up to a high frequency band of a cut-off frequency. CONSTITUTION:Emitters of NPN TRs 1, 2 are connected to a power supply 7, bases are connected respectively to input terminals 51, 52 and emitters are connected transmission to output terminals 53, 54. A capacitor 9 is inserted between the emitter of the NPN TR1 and a base of the NPN TR2 and a capacitor 6 is inserted between the emitter of the NPN TR2 and a base of the NPN TR2. Furthermore, a variable current source 3 is inserted between the emitter of the NPN TR1 and ground and a variable current source 4 is inserted between the emitter of the NPN TR2 and ground.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase shift circuit, and more particularly to an active filter type phase shift circuit whose cutoff frequency is variably controlled.

[0002]

2. Description of the Related Art A conventional phase shift circuit, as shown in FIG. 2, comprises resistors 8, 10 and 12, a capacitor 9 and a differential amplifier circuit 11, and is connected to an input terminal 55. When the voltage V _o output from the output terminal 56 is set to the input voltage V _i , the resistance value of the resistor 12 is R ₁₂ , and the capacity value of the capacitor 9 is C ₉ , the transfer function T ( s) is given by the following equation.

T (s) = V _o / V _i = (s−1 / R ₁₂ · C ₉ ) / (s + 1 / R ₁₂ · C ₉ ) ... (1) From the above equation, the amplitude of the phase shift circuit concerned The characteristic ┃T (s) ┃ is obviously the following formula.

┃T (s) ┃ = 1 ……………………………… (2) Therefore, the frequency characteristic of the phase shift circuit is constant without depending on the frequency, and The phase characteristic argT (s) is expressed by the following equation.

ArgT (s) = 2 tan ⁻¹ (f / f _c ) ... (3) That is, the phase characteristic is a function of frequency. Here, f _c is the cutoff frequency of the phase shift circuit and is represented by the following equation.

F _c = 1 / (2πR ₁₂ · C ₉ ) ... (4) Therefore, the resistance value R ₁₂ of the resistor ₁₂ and the capacitance value C ₉ of the capacitor ₉ make the amplitude Only the phase characteristic can be controlled and adjusted while the characteristic remains constant. In addition, the delay characteristic τ of the phase shift circuit
(F) is obtained by differentiating the phase characteristic shown in the equation (3) and is given by the following equation.

[0007] τ (f) = d [argT (s)] _{/ dω = f c / π (} f 2 + f c 2) ........................... (5)

In the conventional phase shift circuit described above, since the cutoff frequency f _c is defined by the resistor 12 and the capacitor 9, the value of the cutoff frequency f _c can be made variable. However, the differential amplifier circuit 11 is apt to be affected by noise on the power supply line, and the setting range of the cutoff frequency f _c is restricted by the frequency characteristic of the differential amplifier circuit 11.

[0008]

In the phase shift circuit according to the first aspect of the invention, the collectors are commonly connected and connected to the power source on the high potential side, and the bases are individually connected to the first and second input terminals, respectively. And a first and second emitter respectively connected to the first and second output terminals, respectively.
First NPN transistor, an emitter of the first NPN transistor, and a first capacitor that is inserted and connected between the emitter of the first NPN transistor and the base of the second NPN transistor;
A second capacitor is inserted and connected between the base of the PN transistor and the emitter of the second NPN transistor, and is inserted and connected between the emitter of the first NPN transistor and the low-potential-side power supply. A first variable current source,
A second variable current source inserted and connected between the emitter of the second NPN transistor and the power source on the low potential side;
It is configured with.

In the phase shift circuit of the second aspect of the invention, the collectors are commonly connected to the power source on the low potential side, and the bases are individually connected to the first and second input terminals, respectively, and Between the first and second PNP transistors whose emitters are individually connected to the first and second output terminals respectively, the emitter of said first PNP transistor and the base of said second PNP transistor. A first capacitor inserted and connected, a second capacitor inserted and connected between the base of the first PNP transistor and the emitter of the second PNP transistor; and the first capacitor.
First variable current source inserted and connected between the emitter of the PNP transistor and the power source on the high potential side, and the second P
And a second variable current source inserted and connected between the emitter of the NP transistor and the power source on the high potential side.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. As shown in FIG. 1, this embodiment comprises NPN transistors 1 and 2, variable current sources 3 and 4, capacitors 5 and 6, and a power supply 7. In FIG. 1, a pair of output terminals 53 is provided for a differential input voltage input from the pair of input terminals 51 and 52.
A differential output voltage corresponding to the differential input voltage is output from and 54.

Now, assuming that the current value I ₀₃ of the variable current source 3 and the current value I ₀₄ of the variable current source 4 are equal, this is I ₀
Assuming that the transconductance of the NPN transistors 1 and 2 is g _m , the following equation is obtained.

G _m = I ₀ · q / kT ……………………………… (6) q: electron charge k: Poltzmann constant T: absolute temperature input to input terminal 51 and input 52 Input voltage is V
_{If the} output voltage output from the output terminal 53 and the output terminal 54 is V _o , the transfer function T (s) has the same capacitance values C ₅ and C ₆ of the capacitances 5 and 6, and is referred to as C. And is given by the following equation.

T (s) = V _o / V _i = (s−g _m / C) / (s + g _m / C) (7) Therefore, the amplitude characteristic ┃T (s) ┃ and the phase characteristic argT
(S) is obtained by the following equation.

┃T (s) ┃ = 1 …………………………………… (8) argT (s) = 2tan ⁻¹ (f / f _c ) ………… (9) That is, , The amplitude is constant regardless of the frequency, and the phase characteristic is a function of the frequency. The cutoff frequency f _c is given by the following equation.

F _c = g _m / (2πC) ……………………………… (10) From the above equations (6) and (10), the variable current sources 3 and 4
By changing the current value I _o of the cutoff frequency f _c
Can be variable. Therefore, since the cutoff frequency f _c can be made variable, it becomes possible to control the phase characteristic itself as is apparent from the equation (9).
The delay characteristic is shown by the following equation.

Τ (s) = f _c / π (f ² + f _c ² ) ... (11) Since the cutoff frequency f _c can be made variable in the equation (11), Regarding the delay characteristic, the amount of delay can be set arbitrarily, and it can be used as a constant delay circuit.

The setting range of the cutoff frequency f _c is limited by the unity gain of the differential amplifier circuit in the conventional phase shift circuit, but in the present invention, f _T (several GHz) of the NPN transistors 1 and 2 is set. It is possible to set up to a high frequency band up to a degree), and it is also possible to make it variable.

Further, in the conventional phase shift circuit, as shown in FIG. 2, since the signal input is a single input, when noise is mixed on the power supply line and the transmission line on the input side, the signal is output to the output side. The noise is amplified and output, but in the present invention, since the operation can be performed by the differential input / differential output, the noise is canceled and reduced on the output side. Further, in the present invention, the number of elements is smaller than that of the conventional circuit, and when the semiconductor is integrated, the chip area can be reduced by about 90%.

In the above description, the operation using the NPN transistor as the pair of transistors has been described, but the power source on the high potential side and the power source on the low potential side are replaced with each other. It goes without saying that the present invention can be effectively applied by using PNP transistors instead of the NPN transistors as a pair of transistors.

[0021]

As described above, according to the present invention, the cutoff frequency is reduced to several G by forming the phase shift circuit through the combination of the transconductance g _{m of the} transistor and the capacitance.
It has an effect that it can be variably controlled up to a high frequency band up to about Hz, and can reduce noise and the like due to power supply fluctuation through the operation by differential input / differential output, and at the same time reduce the number of elements. There is an effect that a phase shift circuit can be configured.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional example.

[Explanation of symbols]

 1, 2 NPN transistor 3, 4 Variable current source 5, 6 Capacitance 7 Power supply 8, 10, 12 Resistor 9 Capacitance 11 Differential amplifier circuit

Claims (2)

[Claims] 1. Collectors are commonly connected to a power source on the high potential side, bases are individually connected to first and second input terminals, respectively, and emitters are respectively connected to first and second input terminals. First individually connected to output terminals
And a second NPN transistor, an emitter of the first NPN transistor, and a second
A first capacitor inserted and connected to the base of the NPN transistor, and a second capacitor inserted and connected to the base of the first NPN transistor and the emitter of the second NPN transistor. A first variable current source that is inserted and connected between the emitter of the first NPN transistor and a power source on the low potential side, and between the emitter of the second NPN transistor and the power source on the low potential side. A second variable current source, which is inserted and connected, and a phase shift circuit. 2. The collectors are commonly connected to a power source on the low potential side, the bases are individually connected to the first and second input terminals, respectively, and the emitters are respectively connected to the first and second input terminals. First individually connected to output terminals
And a second PNP transistor, an emitter of the first PNP transistor, and a second PNP transistor.
A first capacitor inserted and connected to the base of the PNP transistor, and a second capacitor inserted and connected to the base of the first PNP transistor and the emitter of the second PNP transistor. A first variable current source that is inserted and connected between the emitter of the first PNP transistor and a power supply on the high potential side, and between the emitter of the second PNP transistor and the power supply on the high potential side. A second variable current source, which is inserted and connected, and a phase shift circuit.