JPS6125248Y2 - - Google Patents
Info
- Publication number
- JPS6125248Y2 JPS6125248Y2 JP1980119231U JP11923180U JPS6125248Y2 JP S6125248 Y2 JPS6125248 Y2 JP S6125248Y2 JP 1980119231 U JP1980119231 U JP 1980119231U JP 11923180 U JP11923180 U JP 11923180U JP S6125248 Y2 JPS6125248 Y2 JP S6125248Y2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- foil
- mount plate
- semiconductor device
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
Description
【考案の詳細な説明】
この考案は、複数個の外部接続用アルミニウム
（Al）電極を有する半導体素子において、そのAl
電極から取扱い容易な外部リードを引き出し得る
半導体装置の構造に関するものである。[Detailed description of the invention] This invention is a semiconductor device having a plurality of aluminum (Al) electrodes for external connection.
The present invention relates to a structure of a semiconductor device that allows easy-to-handle external leads to be drawn out from electrodes.
まず、この種の従来装置の構造を第１図によつ
て説明する。第１図に従来装置の一例の断面図を
示す。第１図において、１は表面に複数個の外部
接続用のAl電極を有する半導体素子、２はセラ
ミツク基板、３はセラミツク基板２に印刷焼成さ
れた銀（Ag）／パラジウム（Pd）電極、４は半
導体素子１に内蔵困難なコンデンンサチツプ、５
は接続用ろう材、６は半導体素子１のAl電極と
Ag／Pd電極３とを接続するAlワイヤ、７は外部
リード、８はヒートシンクを形成し取付台となる
マウントプレート、９はセラミツク基板２とマウ
ントプレート８とを接着させる接着剤、１０は上
記の諸部分を包含してモルードするモールド樹脂
である。 First, the structure of this type of conventional device will be explained with reference to FIG. FIG. 1 shows a sectional view of an example of a conventional device. In FIG. 1, 1 is a semiconductor element having a plurality of Al electrodes for external connection on its surface, 2 is a ceramic substrate, 3 is a silver (Ag)/palladium (Pd) electrode printed and fired on the ceramic substrate 2, and 4 5 is a capacitor chip that is difficult to incorporate into the semiconductor device 1;
6 is the brazing material for connection, and 6 is the Al electrode of semiconductor element 1.
Al wire connecting the Ag/Pd electrode 3, 7 an external lead, 8 a mount plate forming a heat sink and serving as a mounting base, 9 an adhesive for bonding the ceramic substrate 2 and the mount plate 8, 10 the above-mentioned It is a molding resin that includes various parts and molds them.
次に、このように構成された従来装置の組立方
法について説明する。まず、セラミツク基板２上
に印刷焼成されたAg／Pd電極３上に半導体素子
１およびコンデンサチツプ４を載せ、ろう材５に
て接着させる。その後、半導体素子１のAl電極
をAlワイヤ６によりAg／Pd電極３にそれぞれ接
続する。そして、外部リード７の一端をろう材５
にてAg／Pd電極３に接続する。次に、上記取付
台となるマウントプレート８上にセラミツク基板
２を接着剤９により接着させる。そして最後に、
これをモールド樹脂１０によりモールドする。 Next, a method of assembling the conventional device configured as described above will be explained. First, a semiconductor element 1 and a capacitor chip 4 are placed on an Ag/Pd electrode 3 printed and fired on a ceramic substrate 2, and bonded with a brazing material 5. Thereafter, the Al electrodes of the semiconductor element 1 are connected to the Ag/Pd electrodes 3 by Al wires 6, respectively. Then, connect one end of the external lead 7 to the brazing material 5.
Connect to Ag/Pd electrode 3 at. Next, the ceramic substrate 2 is bonded with an adhesive 9 onto the mount plate 8 which serves as the mounting base. And finally,
This is molded with mold resin 10.
上記のような従来装置においては、半導体素子
１、コンデンサチツプ４および外部リード７を保
持するためにAg／Pd電極３を印刷焼成したセラ
ミツク基板２が用いられており、このセラミツク
基板２が高価となる。また、半導体素子１のAl
電極を外部リード７に引き出すために、Alワイ
ヤ６とセラミツク基板２に印加焼成されたAg／
Pd電極３とを介しているから、接続箇所が多く
なり、それだけ信頼性に限界があつた。さらに、
セラミツク基板２がマウントプレート８に接着剤
９により接着されており、半導体素子１からマウ
ントプレート８までの熱抵抗が大きくなり、それ
を補うためには大きなマウントプレート８が必要
となる。また、外部リード７を接続するための接
続バツドが必要となるから、実装効率が悪く、セ
ラミツク基板２が大きくなり、装置全体として大
きなものとなるなどの欠点があつた。 In the conventional device described above, a ceramic substrate 2 on which Ag/Pd electrodes 3 are printed and fired is used to hold the semiconductor element 1, capacitor chip 4, and external leads 7, and this ceramic substrate 2 is expensive. Become. In addition, Al of the semiconductor element 1
In order to draw out the electrode to the external lead 7, an applied and fired Ag/fiber wire is applied to the Al wire 6 and the ceramic substrate 2.
Since it is connected to the Pd electrode 3, there are many connection points, which limits the reliability. moreover,
Since the ceramic substrate 2 is bonded to the mount plate 8 with an adhesive 9, the thermal resistance from the semiconductor element 1 to the mount plate 8 becomes large, and a large mount plate 8 is required to compensate for this. Furthermore, since a connection pad is required to connect the external lead 7, there are disadvantages such as poor mounting efficiency, an increase in the size of the ceramic substrate 2, and an increase in the overall size of the device.
この考案は、上記の点に鑑みてなされてもの
で、信頼性を向上させ、かつ全体の形状を小さく
できる半導体装置を提供することを目的としたも
のである。 This invention has been made in view of the above points, and is intended to provide a semiconductor device that has improved reliability and can be made smaller in overall size.
この考案に係る半導体装置は、半導体素子の位
置決め用凸部を有するマウントプレートの上記位
置決め用凸部の上面に、表面に複数個の外部接続
用のAl電極を有する半導体素子の裏面を接着す
ると共に、複数個のAl箔リードとこれらを保持
し上記位置決め用凸部を露出させる窓を有する絶
縁板とからなるAl箔プリント基板を上記マウン
トプレートに接着し、複数個の上記Al箔リード
の一端をAlワイヤを介して上記Al電極に接続し
他端を外部リードとしたものである。 In the semiconductor device according to this invention, the back surface of a semiconductor element having a plurality of Al electrodes for external connection on the surface is bonded to the upper surface of the positioning convex part of a mount plate having a positioning convex part for the semiconductor element. , an Al foil printed circuit board consisting of a plurality of Al foil leads and an insulating plate that holds them and has a window exposing the positioning convex portion is adhered to the mount plate, and one end of the plurality of Al foil leads is attached to the mount plate. It is connected to the above Al electrode via an Al wire, and the other end is used as an external lead.
以下、本考案の実施例を図について説明する。
第２図、第３図および第４図はこの考案の一実施
例による半導体装置を示し、第２図は断面図、第
３図は分解斜視図、第４図はモールド前の斜視図
である。この実施例は４個のAl電極を有する半
導体素子を例に取つている。第２図〜第４図にお
いて、１ａは半導体素子１のAl電極、８ａはマ
ウントプレート８の取付穴、８ｂは半導体素子１
の位置決めをする位置決め用凸部、１１はAl箔
リード１１ｂが樹脂などからなる絶縁基板１１ａ
により保持されてなるAl箔プリント基板、１１
ｃはAl箔リード１１ｂに銅メツキなどにより選
択的に形成されたろう付け可能化部、１１ｄは位
置決め用凸部８ｂを露出させる窓である。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
2, 3, and 4 show a semiconductor device according to an embodiment of this invention, in which FIG. 2 is a sectional view, FIG. 3 is an exploded perspective view, and FIG. 4 is a perspective view before molding. . This embodiment takes as an example a semiconductor device having four Al electrodes. In FIGS. 2 to 4, 1a is the Al electrode of the semiconductor element 1, 8a is the mounting hole of the mount plate 8, and 8b is the semiconductor element 1.
11 is an insulating substrate 11a whose Al foil lead 11b is made of resin or the like.
Al foil printed circuit board held by 11
11d is a window that exposes the positioning convex portion 8b.
次に、上記のように構成された本実施例装置の
組立方法について説明する。まず、マウントプレ
ート８に設けられた位置決め用凸部８ｂに半導体
素子１を載せ、ろう材５にて接着する。次に、
Al箔プリント基板１１のろう付け可能化部１１
ｃのコンデンサチツプ接続位置にコンデンサチツ
プ４を載せ、ろう材５にて接着する。その後、
Al箔プリント基板１１の絶縁基板１１ａ側がマ
ウントプレート８の表面に接するように接着剤９
にて接着する。それから、半導体素子１のAl電
極１ａとAl箔プリント基板１１のAl箔リード１
１ｂとをAlワイヤ６により接続する。そして最
後に、モールド樹脂１０によりモールドするもの
である。 Next, a method for assembling the device of this embodiment configured as described above will be described. First, the semiconductor element 1 is placed on the positioning protrusion 8b provided on the mount plate 8 and bonded with the brazing material 5. Next,
Brazing-enabling portion 11 of Al foil printed circuit board 11
A capacitor chip 4 is placed on the capacitor chip connection position c and bonded with a brazing material 5.
The adhesive 9 is applied so that the insulating substrate 11a side of the Al foil printed circuit board 11 contacts the surface of the mount plate 8.
Then, the Al electrodes 1a of the semiconductor element 1 and the Al foil leads 11 of the Al foil printed circuit board 11 are bonded to each other.
1b is connected by an Al wire 6. Finally, it is molded with a molding resin 10.
このような本実施例装置では、半導体素子１を
直接にマウントプレート８に接着させるから、高
価なセラミツク基板を用いる必要がなく、また、
半導体素子１のAl電極１ａを外部に引き出すた
めに介するものはAlワイヤ極６のみで、接続箇
所が少なく、さらにAlワイヤ６と半導体素子１
側およびAl箔プリント基板１１側との接続は、
それぞれAl−Alの接続、すなわち、同一金属間
の接続となり、接続部の信頼性が向上する。さら
に、半導体素子１が直接にマウントプレート８上
に接着されているので、半導体素子１からマウン
トプレート８までの熱抵抗が小さくなり、マウン
トプレート８を小さくできる。また、Al箔プリ
ント基板１１上にコンデンサチツプ４が接続し、
Al箔プリント基板１１のAl箔リード１１ｂがそ
のまま外部リードとなるため実装効率が高く、装
置全体としてより小さくすることができる。 In the device of this embodiment, since the semiconductor element 1 is directly bonded to the mount plate 8, there is no need to use an expensive ceramic substrate.
Only the Al wire pole 6 is used to draw out the Al electrode 1a of the semiconductor element 1 to the outside, and there are few connection points, and the Al wire 6 and the semiconductor element 1 are
The connection with the side and the Al foil printed circuit board 11 side is as follows.
Each is an Al-Al connection, that is, a connection between the same metals, and the reliability of the connection is improved. Furthermore, since the semiconductor element 1 is directly bonded onto the mount plate 8, the thermal resistance from the semiconductor element 1 to the mount plate 8 is reduced, and the mount plate 8 can be made smaller. In addition, a capacitor chip 4 is connected on the Al foil printed circuit board 11,
Since the Al foil leads 11b of the Al foil printed circuit board 11 directly serve as external leads, mounting efficiency is high and the entire device can be made smaller.
なお上記実施例においては、ろう付け可能化部
１１ｃにコンデンサチツプに４を接着した場合に
ついて述べたが、コンデンサチツプに限られるわ
けでなく、他の受動素子または別の半導体素子で
あつてもよい。 In the above embodiment, a case has been described in which 4 is bonded to a capacitor chip to the brazing-enabled portion 11c, but it is not limited to a capacitor chip, and may be another passive element or another semiconductor element. .
以上詳述したように、この考案による半導体装
置によれば、半導体素子をマウントプレートの位
置決め用凸部の上面に接着するとともに、Al箔
プリント基板を上記マウントプレートの表面に接
着して複数個のAl箔リードの一端を半導体素子
のAl電極にAlワイヤのみを介して接続し他端を
外部リードとするようにしたので、高い信頼性を
有し、かつコンパクトな半導体装置を得ることが
できる。 As detailed above, according to the semiconductor device of this invention, a semiconductor element is bonded to the upper surface of the positioning convex portion of the mount plate, and an Al foil printed circuit board is bonded to the surface of the mount plate to form a plurality of Since one end of the Al foil lead is connected to the Al electrode of the semiconductor element through only the Al wire, and the other end is used as an external lead, a highly reliable and compact semiconductor device can be obtained.
特に、この考案は、放熱を要する大電力用集積
半導体装置であつて半導体素子に内蔵困難な素子
を含むものに有用である。 In particular, this invention is useful for high-power integrated semiconductor devices that require heat dissipation and include elements that are difficult to incorporate into a semiconductor element.
第１図は従来装置の一例の断面図、第２図〜第
４図はこの考案の一実施例による半導体装置を示
す図で、第２図は断面図、第３図はの分解斜視
図、第４図はモールド前の斜視図である。
図において、１は半導体素子、１ａは半導体素
子のAl電極、４はコンデンサチツプ（受動素
子）、６はAlワイヤ、８はマウントプレート、８
ｂは位置決め用凸部、１１はAl箔プリント基
板、１１ａは絶縁基板、１１ｂはAl箔リード、
１１ｃはろう付け可能化部、１１ｄは位置決め用
凸部８ｂを露出させる窓を示す。なお図中同一符
号は同一又は相当部分を示す。
FIG. 1 is a sectional view of an example of a conventional device, FIGS. 2 to 4 are views showing a semiconductor device according to an embodiment of the invention, FIG. 2 is a sectional view, and FIG. 3 is an exploded perspective view of the device. FIG. 4 is a perspective view before molding. In the figure, 1 is a semiconductor element, 1a is an Al electrode of the semiconductor element, 4 is a capacitor chip (passive element), 6 is an Al wire, 8 is a mount plate, 8
b is a positioning convex part, 11 is an Al foil printed board, 11a is an insulating board, 11b is an Al foil lead,
Reference numeral 11c indicates a brazing-enabled portion, and reference numeral 11d indicates a window that exposes the positioning convex portion 8b. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
下、「Al」と略記する）電極を有する半導体素
子と、 上記半導体素子の位置決めをするための位置
決め用凸部を有し、この位置決め用凸部の上面
に上記半導体素子を接着保持すると共にヒート
シンクの働きをするマウントプレートと、 一端が上記半導体素子の上記Al電極にAlワ
イヤを介して接続され他端が外部リードとなる
複数個のAl箔リードと、これらを保持すると
共に上記位置決め用凸部を露出させる窓を有す
る絶縁板とからなり、上記マウントプレートに
接着されたAl箔プリント基板とを備えたこと
を特徴とする半導体装置。 (2) 上記Al箔リードの所要部分にろう付け可能
化部が形成されていることを特徴とする実用新
案登録請求の範囲第１項記載の半導体装置。 (3) 上記ろう付け可能化部に別の半導体素子がろ
う付けされていることを特徴とする実用新案登
録請求の範囲第２項記載の半導体装置。 (4) 上記ろう付け可能化部に受動素子がろう付け
されていることを特徴とする実用新案登録請求
の範囲第２項記載の半導体装置。 (5) 上記Al箔リードの厚みが数十μｍ〜数百μ
ｍであることを特徴とする実用新案登録請求の
範囲第１項ないし第４項のいずれかに記載の半
導体装置。[Claims for Utility Model Registration] (1) A semiconductor element having a plurality of aluminum (hereinafter abbreviated as "Al") electrodes for external connection on its surface, and a positioning convex portion for positioning the semiconductor element. a mount plate that adhesively holds the semiconductor element on the upper surface of the positioning convex part and also functions as a heat sink; one end is connected to the Al electrode of the semiconductor element via an Al wire, and the other end is external. It comprises a plurality of Al foil leads serving as leads, an insulating plate that holds these leads and has a window that exposes the positioning convex portion, and an Al foil printed circuit board that is bonded to the mount plate. Characteristic semiconductor devices. (2) The semiconductor device according to claim 1, which is a utility model registration, characterized in that a brazing enable portion is formed in a required portion of the Al foil lead. (3) The semiconductor device according to claim 2, wherein another semiconductor element is brazed to the brazing portion. (4) The semiconductor device according to claim 2, wherein a passive element is brazed to the brazing portion. (5) The thickness of the above Al foil lead is from several tens of μm to several hundred μm.
The semiconductor device according to any one of claims 1 to 4 of the utility model registration claims, characterized in that m.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1980119231U JPS6125248Y2 (en) | 1980-08-21 | 1980-08-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1980119231U JPS6125248Y2 (en) | 1980-08-21 | 1980-08-21 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5741656U JPS5741656U (en) | 1982-03-06 |
| JPS6125248Y2 true JPS6125248Y2 (en) | 1986-07-29 |
Family
ID=29479880
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1980119231U Expired JPS6125248Y2 (en) | 1980-08-21 | 1980-08-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6125248Y2 (en) |
-
1980
- 1980-08-21 JP JP1980119231U patent/JPS6125248Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5741656U (en) | 1982-03-06 |
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