JPS6125247Y2 - - Google Patents
Info
- Publication number
- JPS6125247Y2 JPS6125247Y2 JP1980119230U JP11923080U JPS6125247Y2 JP S6125247 Y2 JPS6125247 Y2 JP S6125247Y2 JP 1980119230 U JP1980119230 U JP 1980119230U JP 11923080 U JP11923080 U JP 11923080U JP S6125247 Y2 JPS6125247 Y2 JP S6125247Y2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- foil
- semiconductor device
- mount plate
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 59
- 239000011888 foil Substances 0.000 claims description 35
- 239000000758 substrate Substances 0.000 claims description 13
- 238000005219 brazing Methods 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 11
- 239000000919 ceramic Substances 0.000 description 11
- 239000003990 capacitor Substances 0.000 description 9
- 239000000463 material Substances 0.000 description 6
- 238000000465 moulding Methods 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910018173 Al—Al Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Landscapes
- Wire Bonding (AREA)
- Die Bonding (AREA)
Description
【考案の詳細な説明】
この考案は、複数個の外部接続用アルミニウム
（Al）電極を有する半導体素子において、そのAl
電極から取り扱い容易な外部リードを引き出し得
る半導体装置の構造に関するものである。[Detailed description of the invention] This invention is a semiconductor device having a plurality of aluminum (Al) electrodes for external connection.
The present invention relates to a structure of a semiconductor device that allows easy-to-handle external leads to be drawn out from electrodes.
まず、この種の従来装置の構造を第１図によつ
て説明する。第１図に従来装置の一例の断面図を
示す。第１図において、１はその表面に複数個の
Al電極を有する半導体素子、２はセラミツク基
板、３はセラミツク基板２に印刷焼成された銀
（Ag）／パラジウム（Pd）電極、４は半導体素子
１に内蔵困難なコンデンンサチツプ、５は接続用
ろう材、６は半導体素子１のAl電極とAg／Pd電
極３とを接続するAlワイヤ、７は外部リード、
８はヒートシンクを形成し取付台となるマウント
プレート、９はセラミツク基板２とマウントプレ
ート８とを接着させる接着剤、１０は上記の諸部
分を包含してモルードするモールド樹脂である。 First, the structure of this type of conventional device will be explained with reference to FIG. FIG. 1 shows a sectional view of an example of a conventional device. In Fig. 1, 1 has multiple pieces on its surface.
A semiconductor element having an Al electrode, 2 is a ceramic substrate, 3 is a silver (Ag)/palladium (Pd) electrode printed and fired on the ceramic substrate 2, 4 is a capacitor chip that is difficult to incorporate into the semiconductor element 1, 5 is for connection brazing material, 6 an Al wire connecting the Al electrode of the semiconductor element 1 and the Ag/Pd electrode 3, 7 an external lead,
8 is a mount plate forming a heat sink and serving as a mounting base; 9 is an adhesive for bonding the ceramic substrate 2 and the mount plate 8; and 10 is a mold resin for molding the above-mentioned parts.
次に、このように構成された従来装置の組立方
法について説明する。まず、セラミツク基板２上
に印刷焼成されたAg／Pd電極３上に半導体素子
１およびコンデンサチツプ４を載せ、ろう材５に
て接着させる。その後、半導体素子１のAl電極
をAlワイヤ６によりAg／Pd電極３にそれぞれ接
続する。そして、外部リード７の一端をろう材５
にてAg／Pd電極３に接続する。次に、取付台と
なるマウントプレート８上にセラミツク基板２を
接着剤９により接着させる。そして最後に、これ
をモールド樹脂１０によりモールドする。 Next, a method of assembling the conventional device configured as described above will be explained. First, a semiconductor element 1 and a capacitor chip 4 are placed on an Ag/Pd electrode 3 printed and fired on a ceramic substrate 2, and bonded with a brazing material 5. Thereafter, the Al electrodes of the semiconductor element 1 are connected to the Ag/Pd electrodes 3 by Al wires 6, respectively. Then, connect one end of the external lead 7 to the brazing material 5.
Connect to Ag/Pd electrode 3 at. Next, the ceramic substrate 2 is bonded with an adhesive 9 onto a mount plate 8 serving as a mounting base. Finally, this is molded with mold resin 10.
上記のような従来装置においては、半導体素子
１、コンデンサチツプ４および外部リード７を保
持するためにAg／Pd電極３を印刷焼成したセラ
ミツク基板２が用いられており、このセラミツク
基板２が高価となる。また、半導体素子１のAl
電極を外部リード７に引き出すためにAlワイヤ
６とセラミツク基板２に印刷焼成されたAg／Pd
電極３とを介しているから、接続箇所が多くな
り、さらにAlワイヤ６とAg／Pd電極３との接続
はAl−Ag／Pdの接続、すなわち異種金属間の接
続となり、接続強度の信頼性において問題があつ
た。また、セラミツク基板２がマウントプレート
８に接着剤９により接着されており、半導体素子
１からマウントプレート８までの熱抵抗が大きく
なり、それを補うためには大きなマウントプレー
ト８が必要となる。その上、外部リード７を接続
くるための接続バツドが必要となるから、実装効
率が悪く、セラミツク基板２が大きくなり、装置
全体として大きなものとなるなどの欠点があつ
た。 In the conventional device described above, a ceramic substrate 2 on which Ag/Pd electrodes 3 are printed and fired is used to hold the semiconductor element 1, capacitor chip 4, and external leads 7, and this ceramic substrate 2 is expensive. Become. In addition, Al of the semiconductor element 1
Ag/Pd printed and fired on Al wire 6 and ceramic substrate 2 to bring out the electrode to external lead 7
Since it is connected to the electrode 3, there are many connection points, and the connection between the Al wire 6 and the Ag/Pd electrode 3 is an Al-Ag/Pd connection, that is, a connection between different metals, which increases the reliability of the connection strength. There was a problem. Further, since the ceramic substrate 2 is bonded to the mount plate 8 with an adhesive 9, the thermal resistance from the semiconductor element 1 to the mount plate 8 becomes large, and a large mount plate 8 is required to compensate for this. Furthermore, since a connecting pad is required to connect the external lead 7, the mounting efficiency is poor, the ceramic substrate 2 becomes large, and the device as a whole becomes large.
この考案は、上記の点に鑑みてなされてもの
で、信頼性を向上させ、かつ全体の形状を小さく
できる半導体装置を提供することを目的としたも
のである。 This invention has been made in view of the above points, and is intended to provide a semiconductor device that has improved reliability and can be made smaller in overall size.
この考案に係る半導体装置は、半導体素子の位
置決め用凹部を有するマウントプレートの上記位
置決め用凹部の底に、表面に複数個の外部接続用
のAl電極を有する半導体素子の裏面を接着する
と共に、複数個のAl箔リードとこれらを保持す
る絶縁板または柔軟性のある絶縁シートとからな
るAl箔プリント基板を上記マウントプレートに
接着し、上記Al箔リードの一端を上記Al電極に
Alワイヤを介することなく直接接続し他端を外
部リードとしたものである。 In the semiconductor device according to this invention, the back surface of a semiconductor element having a plurality of Al electrodes for external connection on the surface is adhered to the bottom of the positioning recess of a mount plate having a positioning recess for the semiconductor element, and a plurality of An Al foil printed circuit board consisting of Al foil leads and an insulating plate or flexible insulating sheet to hold them is glued to the mount plate, and one end of the Al foil lead is attached to the Al electrode.
It is directly connected without using Al wire, and the other end is used as an external lead.
以下、本考案の実施例を図について説明する。
第２図、第３図、第４図、第５図および第６図は
この考案の一実施例による半導体装置を示し、第
２図はその断面図、第３図はその分解斜視図、第
４図はボンデイング前のその半導体素子部の拡大
断面図、第５図はボンデイング後のその半導体素
子部の拡大断面図、第６図はモールド前のその半
導体装置の斜視図である。この実施例は４個の
Al電極を有する半導体素子の場合を例に取つて
いる。第２図〜第６図において、１ａは半導体素
子１のAl電極、８ａはマウントプレート８の取
付穴、８ｂは半導体素子１を収納する素子収容凹
部、８ｃは素子収容凹部８ｂ内に設けられ、半導
体素子１の位置決めをする位置決め用凹部、１１
はAl箔リード１１ｂが柔軟性を有する絶縁シー
ト１１ａにより保持されてなるAl箔フレキシブ
ルプリント基板、１１ｃはAl箔リード１１ｂ上
に銅メツキなどで選択的に形成されたろう付け可
能化部、１１ｄは位置決め用凹部８ｃに対応する
窓、１２はボンデイング用ツール、Ａはボンデイ
ング後の半導体素子１のエツジ部とAl箔リード
１１ｂとの間隙である。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
2, 3, 4, 5 and 6 show a semiconductor device according to an embodiment of this invention, FIG. 2 is a sectional view thereof, FIG. 3 is an exploded perspective view thereof, and FIG. 4 is an enlarged sectional view of the semiconductor element portion before bonding, FIG. 5 is an enlarged sectional view of the semiconductor element portion after bonding, and FIG. 6 is a perspective view of the semiconductor device before molding. This example has four
The case of a semiconductor device having an Al electrode is taken as an example. 2 to 6, 1a is an Al electrode of the semiconductor element 1, 8a is a mounting hole of the mount plate 8, 8b is an element housing recess for housing the semiconductor element 1, 8c is provided in the element housing recess 8b, A positioning recess 11 for positioning the semiconductor element 1
11c is an Al foil flexible printed circuit board in which an Al foil lead 11b is held by a flexible insulating sheet 11a, 11c is a brazing enable portion selectively formed on the Al foil lead 11b with copper plating, and 11d is a positioning portion. 12 is a bonding tool, and A is a gap between the edge portion of the semiconductor element 1 and the Al foil lead 11b after bonding.
次に、上記のように構成された本実施例装置の
組立方法に一例について説明する。まず、半導体
素子１を位置決め用凹部８ｃの底面にろう材５に
て接着する。次に、Al箔フレキシブルプリント
基板１１のろう付け可能化部１１ｃのコンデンサ
チツプ接続位置にコンデンサチツプ４を載せ、ろ
う材５にて接着する。その後、Al箔フレキシブ
ルプリント基板１１をその絶縁シート１１ａの面
がマウントプレート８の表面に接するように接着
剤９にて接着する。そして、第４図に示すよう
に、ボンデイング用ツール１２を用いて半導体素
子１のAl電極１ａとAl箔リード１１ｂとを超音
波ボンデイング法などによりボンデイングする。
この場合、ボンデイング用ツール１２は第４図に
示すようにすべてのAl箔リード１１ｂを同時に
ボンデイングする構造のものでも良いし、また、
各Al箔リード１１ｂを別々にボンデイングする
構造のものでも良い。そして、最後にこのように
して組立てた装置モールド樹脂１０によりモール
ドする。 Next, an example of a method for assembling the apparatus of this embodiment configured as described above will be explained. First, the semiconductor element 1 is bonded to the bottom surface of the positioning recess 8c using a brazing material 5. Next, the capacitor chip 4 is placed on the capacitor chip connection position of the brazing portion 11c of the Al foil flexible printed circuit board 11, and bonded with the brazing material 5. Thereafter, the Al foil flexible printed circuit board 11 is bonded with the adhesive 9 so that the surface of the insulating sheet 11a is in contact with the surface of the mount plate 8. Then, as shown in FIG. 4, using the bonding tool 12, the Al electrode 1a of the semiconductor element 1 and the Al foil lead 11b are bonded by an ultrasonic bonding method or the like.
In this case, the bonding tool 12 may be structured to bond all the Al foil leads 11b at the same time as shown in FIG.
A structure in which each Al foil lead 11b is bonded separately may also be used. Finally, the device assembled in this way is molded using molding resin 10.
このような本実施例装置では、半導体素子１を
マウントプレート８に直接に接着させるから、高
価なセラミツク基板を用いる必要がない。また、
半導体素子１のAl電極１ａを外部に引き出すた
めに中継しているものはなく、上記Al電極１ａ
はAl箔リード１１ｂのみにより直接外部に引き
出されているので、接続箇所が最小となり、か
つ、半導体素子１のAl電極１ａとAl箔リード１
１ｂとの接続はAl−Alの接続、すなわち、同一
金属間の接続となり、接続部の信頼性が大きく向
上する。また、半導体素子１が直接にマウントプ
レート８上に接着されているので、半導体素子１
からマウントプレート８までの熱抵抗が小さくな
り、マウントプレート８を小さくできる。また、
Al箔フレキシブルプリント基板１１上にコンデ
ンサチツプ４が接続され、Al箔フレキシブルプ
リント基板１１のAl箔リード１１ｂがそのまま
外部リードとなるため実装効率が高くなり、装置
全体としてより小さくすることができる。さらに
は、Al箔フレキシブルプリント基板１１のAl箔
リード１１ｂが柔軟性のある外部リードとなるの
で、実装時および装置としての使用時において、
外部リードへのストレスに対し装置内部を保護す
る役目を果たす。また、半導体素子１がマウント
プレート８に設けられた素子収納凹部８ｂに収納
されており、かつ該素子１に接続されるAl箔リ
ード１１ｂが外部に突起していないので、半導体
素子１およびAl箔リード１１ｂを外力から保護
することができる。その上、半導体素子１のエツ
ジ部とAl箔リード１１ｂとの間隙Ａは十分に得
られ、エツジ部でシヨートすることがないなど、
種々のすぐれた効果がある。 In the device of this embodiment, since the semiconductor element 1 is directly bonded to the mount plate 8, there is no need to use an expensive ceramic substrate. Also,
There is no relay for pulling out the Al electrode 1a of the semiconductor element 1 to the outside, and the Al electrode 1a is
is directly led out to the outside only by the Al foil lead 11b, so the number of connection points is minimized, and the Al electrode 1a of the semiconductor element 1 and the Al foil lead 1
The connection with 1b is an Al-Al connection, that is, a connection between the same metals, and the reliability of the connection is greatly improved. Furthermore, since the semiconductor element 1 is directly bonded onto the mount plate 8, the semiconductor element 1
The thermal resistance from to the mount plate 8 is reduced, and the mount plate 8 can be made smaller. Also,
The capacitor chip 4 is connected on the Al foil flexible printed circuit board 11, and the Al foil leads 11b of the Al foil flexible printed circuit board 11 directly serve as external leads, so the mounting efficiency is increased and the entire device can be made smaller. Furthermore, since the Al foil leads 11b of the Al foil flexible printed circuit board 11 serve as flexible external leads, during mounting and use as a device,
It serves to protect the inside of the device from stress on the external leads. Furthermore, since the semiconductor element 1 is housed in the element storage recess 8b provided in the mount plate 8, and the Al foil lead 11b connected to the element 1 does not protrude outside, the semiconductor element 1 and the Al foil The lead 11b can be protected from external force. In addition, the gap A between the edge part of the semiconductor element 1 and the Al foil lead 11b is sufficient, and there is no possibility of shooting at the edge part.
It has various excellent effects.
第７図は、この考案により半導体装置の他の実
施例の断面図である。第７図に示す実施例装置
は、モールド樹脂１０でモールドする代わりに、
プリコート材１３でその要所のみを覆うものであ
る。本実施例の効果は上記実施例装置と同様であ
る。 FIG. 7 is a sectional view of another embodiment of the semiconductor device according to this invention. In the example device shown in FIG. 7, instead of molding with mold resin 10,
The pre-coating material 13 covers only the important parts. The effects of this embodiment are similar to those of the apparatus of the above embodiment.
さらに、第８図はこの考案による半導体装置の
さらに他の実施例の断面図である。第８図に示す
実施例装置は、Al箔フレキシブルプリント基板
１１の代わりに、樹脂などからなる絶縁基板１１
０ａからなるAl箔プリント基板１１０を用いて
いる。この場合には、マウントプレート８に素子
収納凹部８ｂを設ける必要はない。本実施例の効
果は、外部リードが柔軟性を持たない点を除い
て、上記２つの実施例と同様である。 Furthermore, FIG. 8 is a sectional view of still another embodiment of the semiconductor device according to this invention. The embodiment shown in FIG. 8 has an insulating substrate 11 made of resin or the like instead of the Al foil flexible printed circuit board 11.
An Al foil printed circuit board 110 made of 0a is used. In this case, there is no need to provide the element storage recess 8b in the mount plate 8. The effects of this embodiment are similar to those of the above two embodiments, except that the external leads do not have flexibility.
なお、上記実施例においては、コンデンサチツ
プ４をろう付け可能化部１１ｃに接着した場合に
ついて述べたが、これはコンデンサチツプに限定
されず他の受動素子または別の半導体素子であつ
てもよい。 In the above embodiment, a case has been described in which the capacitor chip 4 is bonded to the brazing portion 11c, but this is not limited to the capacitor chip, and may be another passive element or another semiconductor element.
以上詳述したように、この考案による半導体装
置によれば、半導体素子をマウントプレートの位
置決め用凹部の底面に接着するとともに、Al箔
プリント基板を上記マウントプレートの表面に接
着して複数個のAl箔リードの一端を半導体素子
のAl電極に直接に接続し他端を外部リードとす
るようにしたので、高い信頼性を有し、かつコン
パクトな半導体装置を得ることができる。 As described in detail above, according to the semiconductor device according to this invention, the semiconductor element is bonded to the bottom surface of the positioning recess of the mount plate, and an Al foil printed circuit board is bonded to the surface of the mount plate, and a plurality of Al foil printed circuit boards are bonded to the surface of the mount plate. Since one end of the foil lead is directly connected to the Al electrode of the semiconductor element and the other end is used as an external lead, a highly reliable and compact semiconductor device can be obtained.
特に、この考案は、放熱を要する大電力用集積
半導体装置であつて半導体素子に内蔵困難な素子
を含むものに有用である。 In particular, this invention is useful for high-power integrated semiconductor devices that require heat dissipation and include elements that are difficult to incorporate into a semiconductor element.
第１図は従来装置の一例の断面図、第２図〜第
６図はこの考案の一実施例による半導体装置を示
す図で、第２図はその断面図、第３図はの分解斜
視図、第４図はボンデイング前のその半導体素子
部の拡大断面図、第５図はボンデイング後のその
半導体素子部の拡大断面図、第６図はモールド前
のその半導体装置の斜視図、第７図および第８図
はそれぞれの考案の他の実施例による半導体装置
の断面図である。
図において、１は半導体素子、１ａは半導体素
子のAl電極、４はコンデンサチツプ（受動素
子）、８はマウントプレート、８ｃは位置決め用
凹部、１１はAl箔フレキシブルプリント基板
（Al箔プリント基板）、１１ａは絶縁シート、１
１ｂはAl箔リード、１１ｃはろう付け可能化
部、１１０はAl箔プリント基板、１１０ａは絶
縁基板を示す。なお図中同一符号は同一又は相当
部分を示す。
FIG. 1 is a sectional view of an example of a conventional device, FIGS. 2 to 6 are views showing a semiconductor device according to an embodiment of this invention, FIG. 2 is a sectional view thereof, and FIG. 3 is an exploded perspective view of the device. , FIG. 4 is an enlarged sectional view of the semiconductor element portion before bonding, FIG. 5 is an enlarged sectional view of the semiconductor element portion after bonding, FIG. 6 is a perspective view of the semiconductor device before molding, and FIG. 7 and FIG. 8 are cross-sectional views of semiconductor devices according to other embodiments of the respective inventions. In the figure, 1 is a semiconductor element, 1a is an Al electrode of the semiconductor element, 4 is a capacitor chip (passive element), 8 is a mount plate, 8c is a positioning recess, 11 is an Al foil flexible printed circuit board (Al foil printed circuit board), 11a is an insulating sheet, 1
1b is an Al foil lead, 11c is a brazing part, 110 is an Al foil printed board, and 110a is an insulating board. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
下、「Al」と略記する。）電極を有する半導体
素子と、 上記半導体素子の位置決めをするための位置
決め用凹部を有し、この位置決め用凹部の底面
に上記半導体素子を接着保持すると共にヒート
シンクの働きをするマウントプレートと、 一端が上記半導体素子のAl電極と接続され
他端が外部リードとなる複数個のAl箔リード
を絶縁基板または柔難性を有する絶縁シートを
介してその上に保持し上記マウントプレートに
接着されたAl箔プリント基板とを備えたこと
を特徴とする半導体装置。 (2) 上記Al箔リードの所要部分にろう付け可能
化部が形成されていることを特徴とする実用新
案登録請求の範囲第１項記載の半導体装置。 (3) 上記ろう付け可能化部に別の半導体素子がろ
う付けされれていることを特徴とする実用新案
登録請求の範囲第２項記載の半導体装置。 (4) 上記ろう付け可能化部に受動素子がろう付け
されていることを特徴とする実用新案登録請求
の範囲第２項記載の半導体装置。 (5) 上記Al箔リードの厚みが数十μｍ〜数百μ
ｍであることを特徴とする実用新案登録請求の
範囲第１項ないし第４項のいずれかに記載の半
導体装置。[Claims for Utility Model Registration] (1) A semiconductor element having a plurality of aluminum (hereinafter abbreviated as "Al") electrodes for external connection on its surface, and a positioning recess for positioning the semiconductor element. a mount plate that adheres and holds the semiconductor element on the bottom surface of the positioning recess and also functions as a heat sink; and a plurality of aluminum plates, one end of which is connected to the Al electrode of the semiconductor element and the other end of which is an external lead. 1. A semiconductor device comprising: an Al foil printed circuit board on which foil leads are held via an insulating substrate or a flexible insulating sheet and bonded to the mount plate. (2) The semiconductor device according to claim 1, which is a utility model registration, characterized in that a brazing enable portion is formed in a required portion of the Al foil lead. (3) The semiconductor device according to claim 2, wherein another semiconductor element is brazed to the brazing portion. (4) The semiconductor device according to claim 2, wherein a passive element is brazed to the brazing portion. (5) The thickness of the above Al foil lead is from several tens of μm to several hundred μm.
The semiconductor device according to any one of claims 1 to 4 of the utility model registration claims, characterized in that m.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1980119230U JPS6125247Y2 (en) | 1980-08-21 | 1980-08-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1980119230U JPS6125247Y2 (en) | 1980-08-21 | 1980-08-21 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5741655U JPS5741655U (en) | 1982-03-06 |
| JPS6125247Y2 true JPS6125247Y2 (en) | 1986-07-29 |
Family
ID=29479879
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1980119230U Expired JPS6125247Y2 (en) | 1980-08-21 | 1980-08-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6125247Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2589358B2 (en) * | 1988-12-12 | 1997-03-12 | 日立電線株式会社 | Double-sided mounting TAB tape carrier |
-
1980
- 1980-08-21 JP JP1980119230U patent/JPS6125247Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5741655U (en) | 1982-03-06 |
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