JPS6124728B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to microprogrammed control circuits.

Conventional addressing of microprogram storage means is accomplished by two methods described below. In the first method, each microinstruction has an instruction address field indicating the storage address in the microprogram storage means of the microinstruction to be executed next. As a result, the capacity of the microprogram storage means increases by the number of address hits, resulting in an increase in the amount of hardware. Next, in the second method, "1" is added to the storage address of the current microinstruction in the microprogram storage means, and the result of the addition is used as the storage address of the next microinstruction to be executed. Therefore, in this method, since the number of microinstruction steps required for each of the various soft instructions differs, it is difficult to effectively use the storage area in the microprogram storage means.
There is a drawback that the amount of hardware increases due to the increase in the microinstruction storage area.

SUMMARY OF THE INVENTION An object of the present invention is to provide a microprogram control circuit in which the storage area in a microprogram storage means can be used effectively and the amount of hardware can be reduced.

The circuit of the present invention includes a first storage circuit that stores a microprogram consisting of a plurality of microinstructions for controlling the operation of an information processing circuit, an instruction code storage means for storing a plurality of instruction codes, and the instruction code storage means. a second storage circuit that stores an address to read from the first storage circuit a microinstruction to be read next to the microinstruction read from the first storage circuit at an address specified by an instruction code given from the first storage circuit; a counting circuit that adds or subtracts a predetermined value to an address for reading a microinstruction from the first storage circuit; and a counting circuit that selects an instruction code from the instruction code storage means and reads a microinstruction from the first storage circuit. and a selection circuit which selects either the second storage circuit or the counting circuit after giving it as an address for reading, and gives it as an address for reading a microinstruction from the first storage circuit.

A feature of the present invention is that the microinstruction sequences corresponding to each soft instruction are arranged in the first storage circuit according to a predetermined rule, and only the storage address of the second step microinstruction is stored in the second storage circuit. The reason lies in the fact that it is obtained from the circuit.

Next, one embodiment of the present invention will be described in detail with reference to the drawings.

Referring to the figure, the circuit of the present invention is composed of a first address decoder 11 that receives a 10-bit first address 600 and a first memory 12 of 1024 words, and includes a microinstruction 120 corresponding to the first address 600. A first storage circuit 10 whose output data is an 8-bit instruction code 20 in a soft instruction.
An instruction code register 20 that receives 0 as an input, a second address decoder 31 that receives an 8-bit instruction code 201 that is the output of this instruction code register 20, and a second memory 32 of 256 words x 10 bits.
a second storage circuit 30 which outputs the instruction code 201, that is, a 10-bit second address 320 corresponding to the address; an address addition circuit 40 which adds "1" to the first address 600; 10 of this address adder circuit 40
The next instruction address register 50 receives the bit output data 400 and outputs the 10-bit third address 500, and the 8-bit instruction code 2
The address selection circuit 60 selects three types of data: 01, 10-bit second address 320, and 10-bit third address 500, and outputs the 10-bit first address 600. However, when selecting the instruction code 201 in the address selection circuit 60, the first address 600
The upper 2 bits of the command are set to "00", and the lower 8 bits are set to the instruction code. Next, processing of soft instructions consisting of a microinstruction sequence of three or more steps will be explained.

(1) First step...In the address selection circuit 60, the instruction code 20 is set as the first address 600.
1 is selected, the first step microinstruction is read out as the microinstruction 120 from the first storage circuit 10, and this microinstruction is executed.

(2) Second step...The address selection circuit 60 selects the second storage circuit 3 as the first address 600.
Select the second address 320, which is the output of 0,
reading out the second step microinstruction as the microinstruction 120 from the first storage circuit 10;
Execute this microinstruction.

(3) After the third step...address selection circuit 60
In this step, the third address 500, which is the result of adding "1" to the first address in the previous step, is selected as the first address 600, and the microinstructions from the third step onward are stored as the microinstructions 120 from the first storage circuit 10. Read and execute these microinstructions sequentially.

Conventionally, by adopting the above configuration, 1024 words x 10 bits were additionally required as the next instruction address field in the first storage circuit 10.
In this embodiment, the second storage circuit 30 only needs to use 256 words x 10 bits, that is, one-quarter the amount of metal compared to the conventional one.

The present invention has the advantage that a small microprogram control circuit can be realized by, for example, specifying the address of the second step microinstruction using the second storage circuit.

[Brief explanation of the drawing]

The figure is a circuit diagram showing one embodiment of the present invention. 10...First storage circuit, 11...First address decoder, 12...First memory, 20...Instruction code register, 30...Second storage circuit, 31...Second address decoder, 32...Second memory, 40
. . . address addition circuit, 50 . . . next instruction address register, 60 . . . address selection circuit.

Claims (1)

[Scope of Claims] 1. A first storage circuit that stores a microprogram consisting of a plurality of microinstructions that control the operation of an information processing circuit; instruction code storage means for storing an instruction code included in the soft instruction for reading from the first storage circuit; and instruction code storage means for reading a second step microinstruction of the microinstruction sequence from the first storage circuit. a second storage circuit for storing addresses; a counting circuit for adding or subtracting a predetermined value from the microinstruction reading address from the first storage circuit; and selecting an instruction code from the instruction code storage means. After providing the address for reading a microinstruction from the first storage circuit, either one of the second storage circuit or the counting circuit is selected, and the address for reading the microinstruction from the first storage circuit is selected. A microprogram control circuit characterized in that it is comprised of a selection circuit that provides a selection circuit.