JPS6124094A - Memory device for semiconductor - Google Patents

Abstract

PURPOSE:To shorten a rewriting time of data in total by withdrawing a charge inputted by write-in voltage by higher voltage, and by making the length of an erasing time the same degree as that of a write-in time. CONSTITUTION:A boosting circuit 8 consists of switches MOSFETs Q1, Q2 connected in series with clamp diodes D1, D2 to form a fixed write-in voltage Vpp1 and an erasing voltage Vpp2 controlling the voltage generated by charge pump 10 generating far higher voltage than electric source voltage Vcc, pushing up the level gradually receiving supply of charge from electric source voltage Vcc supplied from the outside. The voltage boosted by a charge pump 10 is clamped by break down voltage of clamp diode to generate the stabilized write-in voltage Vpp1 and erasing voltage Vpp2. Thus, the time for rewriting all the data of EEPROM device will be largely shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technique particularly effective when applied to a semiconductor memory technology and a data write/erase method in an electrically writeable/erasable read-only semiconductor memory device. The present invention relates to a technology that is effective for use in a write/erase circuit of an EEFROM (Electrically Erasable Program Read Only Memory) device.

[Background Art] Conventionally, as a read-out semiconductor memory device in which information can be electrically written and erased, for example, MNOS
An EEPROM device using an insulated gate field effect transistor called a metal nitride oxide semiconductor (metal nitride oxide semiconductor) as a memory element has been proposed. MNOS has a nitride film (S) formed under the gate electrode.
Data is written by trapping charges at the interface between the i3N4 film) and the oxide film (Si02 film) using a tunnel effect, and during erasing, a reverse voltage is applied to remove the trapped charges. pull out.

As a method for writing and erasing data in the EEPROM device as described above, the present inventor proposed that during writing, the well region in which MNOS is formed is grounded and the gate electrode is connected to +
We have developed a device in which charge is injected by applying a high voltage such as 15V, and when erasing, the gate electrode is grounded and a voltage of +15V is applied to the well region to extract the charge.

However, in the write/erase method as described above, since the write voltage and the erase voltage are equal, there is a disadvantage that the minimum erase time is about 10 times longer than the minimum write time due to the difference in the mobility of electrons and holes. .

That is, when the relationship between the write and erase voltage VPP and the required time is shown in a graph with the time axis on a logarithmic scale, as shown in FIG. 5, the write characteristic is represented by a solid line A, and the erase characteristic is represented by a solid line B.
It becomes a straight line that slopes downward to the right. Therefore, if the write voltage and the erase voltage are made equal (Vpp1), the time tE required for erasing will be approximately 10 times the time tp required for writing.

As a result, the time required to rewrite data in the entire EEPROM device becomes significantly longer. (Please note that EEPRO
M is explained in comparative detail in Japanese Patent Application Laid-open No. 156370/1983. ) [Object of the Invention] An object of the present invention is to provide a write/erase method that makes it possible to make the data erase time and write time in an EEPROM device almost equal, thereby shortening the total data rewriting time.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A summary of typical inventions disclosed in this application is as follows.

In other words, a booster circuit is provided that can generate two different voltages depending on the signals that control writing and erasing, and when erasing data, a higher voltage than when writing is applied to the nonvolatile memory element in the opposite direction to extract the charge. With this configuration, the charge injected by the write voltage is extracted with a higher voltage, thereby shortening the erase time to the same level as the write time, thereby shortening the time required to rewrite all data in the EEPROM device. This is to achieve the above purpose of

[Embodiment] FIG. 1 is a block diagram showing a schematic configuration of the entire EEPROM device to which the present invention is applied.

In the same figure, 1 has a plurality of memory cells, for example 256
This is a memory array arranged in a matrix of 256 bits. Each memory cell constituting the memory array 1 has a selection switch MOSFE whose gate terminal is connected to a word line WL and whose drain terminal is connected to a data line (or bit line) DL, as shown in FIG.
TQs, and a nonvolatile memory element Qm made of MNOS or the like connected between the source of this selection switch MO8FETQs and the ground point of the circuit.

Furthermore, although not particularly limited, the memory array 1 is:

Each row is divided into words (8 bits), and a group of memory cells (256 words) arranged in the column direction (data line direction) in word units are formed on the same well region.

On both sides of the memory array 1, there is an X-system selection circuits 2a and 2b are provided which are integrated with a write circuit that applies . In this way, it is difficult to arrange relatively large X decoders and write circuits within the minimum spacing between word lines, on the side where the X-system selection circuits 2a and 2b are arranged on both sides of the memory array l. Therefore, the word line pitch can be minimized by alternately arranging write circuits on the left and right sides of the memory array.

Also, on the outside of the memory array 1 (on the side in the drawing), a Y
A system selection circuit 3 is provided. A sense amplifier 4 is provided adjacent to this Y-system selection circuit 3, and the Y gate in the Y-system selection circuit 3 is activated when reading data by a selection signal from a Y-decoder 5 that decodes a Y-system address signal. , eight data lines to which the 8-bit memory cells are connected are connected to a sense amplifier 4 to amplify the read signal. Furthermore, when erasing data, the erase circuit in the Y-system selection circuit 3 applies the write voltage V P to the well region where the corresponding 8-bit memory cell is formed, based on the selection signal supplied from the Y decoder 5. An erase voltage V P P 2 higher than P 1 is applied.

The read data amplified by the sense amplifier 4 is outputted to the external terminal I10 via the input/output buffer circuit 6.

One side of the memory array 1 opposite to the Y system selection circuit 3 (
A write blocking circuit 7 connected to each data line in the memory array 1 is provided on the upper side in the drawing. This write holding circuit wi7 applies a write voltage V to the drain of a memory element that does not require writing (charge injection) when writing data.
A high voltage similar to P P 1 is applied to block writing.

In a memory element such as MNOS, the well region is grounded and the gate electrode is connected to a high voltage (Vp) such as 15V.
When p1) is applied, charges are trapped at the interface between the nitride film and the oxide film under the gate electrode due to the tunnel effect. However, at this time, the write voltage (
When a high voltage similar to Vpp1) is applied, charge injection due to the tunnel effect does not occur. by this,
Writing according to data zz 1 #l, II Q It is enabled.

Furthermore, in this embodiment, during writing and erasing, +
By boosting the power supply voltage Vcc such as 5V to generate the write voltage vpp1 and erase voltage V P P 2,
A booster circuit 8 supplies the write circuits in the system selection circuits 2a and 2b, the erase circuit in the Y system selection circuit 3, and the write blocking circuit 7.
Based on a plurality of control signals such as a chip enable signal GE and a write enable signal W1'' supplied from the outside, the booster circuit 8,
A control circuit 9 is provided that generates internal control signals for controlling the system selection circuit 3 and the like.

FIG. 3 shows an embodiment of the booster circuit 8. In FIG.

The booster circuit 8 receives charge from a power supply voltage Vcc such as +5V supplied from the outside and gradually raises the level to 20 to 25V, which is much higher than the power supply voltage Vcc.
A charge pump IO generates a voltage such as V, and clamp diodes D, D2 limit the voltage generated by this charge pump IO to form a constant write voltage VPP1 and erase voltage VPP2. and nine switches MO8FETQ, z, Q2 connected in series to these clamp diodes D1 and D2, respectively.

That is, in order to define the write time tp and the erase time tE, it is necessary to determine the write voltage V p P 1 and the erase voltage VPP2 relatively accurately. However, if the charge pump 10 is used alone, the level of the boosted voltage will vary considerably due to variations in the elements constituting the charge pump 10. Therefore, in the above embodiment, clamp diodes D1+'D2, which can be formed with relatively high precision, are used.
The voltage boosted by the charge pump 10 is clamped by the breakdown voltage of a clamp diode to generate stable write voltage VPP1 and erase voltage VPP2.

The clamp diodes D1 and D2 are formed to have the same breakdown voltage as the signature voltage V P P z and the erase voltage VPP2L, respectively. Diodes having different breakdown voltages can be formed with high precision by appropriately controlling the amount of ions implanted into the semiconductor region using, for example, a Zener diode.

Control signals A1 and A2 supplied from the control circuit 9 are applied to the gate terminals of the MO5FETs Q1 and Qz.
is applied. The control signal A1 is set to a high level only when writing data, and the control signal A2 is set to a high level only when erasing data. These control signals A1 and A are connected to the switch MO8FETQ1.
and Qz are controlled to turn on and off.

Therefore, when writing data, the charge pump 10 is operated, and the control circuit 9 sends a high level control signal A.
1 is supplied to the booster circuit 8.

M OS FET Q 2 is turned off and MO
SFET Q1 is turned on. Therefore, when the output voltage of charge pump 10 becomes equal to or higher than the breakdown voltage (Vppt) of diode D1, a current flows from charge pump 10 through diode D1 and MO8FET Q1. As a result, the output voltage of the booster circuit 8 is fixed at the breakdown voltage of the diode D1, that is, VPPt, and this is supplied to the write circuit and write block circuit 7 in the X-system selection circuits 2a and 2b.

On the other hand, when erasing data, a high level control signal A2 is supplied from the control circuit 9 to the booster circuit 8, and the MOS F
MOSFET Q with E T Q 1 turned off
2 is turned on. As a result, a current flows through the diode D2, and the output of the booster circuit 8 is fixed at the breakdown voltage of the diode D2, that is, vpP2, and this is supplied to the erase circuit in the Y-system selection circuit 3.

Moreover, in the above embodiment, the clamp diode D1 is
Write voltage V P P 1 and erase voltage V P P such that the breakdown voltages of
A diode D 1 t D 2 is formed to correspond to 2. As a result, erasing is performed at a higher voltage than when writing, and the time tE required for erasing becomes almost the same as the time tp required for writing, and the time required to rewrite all data is significantly increased. be shortened.

Furthermore, in the above embodiment, the MO is diode-connected between the output terminal of the charge pump 10 and the power supply voltage VCC.
8FETQa is provided and N (iF) M O
Since the gate terminal of S F E T Q 3 is connected to the power supply voltage Vcc, it is kept in an on state until the output voltage of the charge pump 10 reaches the Vcc level (5V). As a result, immediately after the charge pump 10 starts boosting the voltage, the output terminal of the charge pump 10 becomes M
The voltage is charged up to the power supply voltage Vcc through the OS FET Qs, and the time required for the voltage to rise to the target voltage is shortened.

Note that the charge pump 10 can be configured as shown in FIG. 4, for example, although it is not particularly limited.

That is, a plurality of MO5FETs Qd11Q are diode-connected between the power supply voltage Vcc and the output terminal.
d 2 t...Q d m are connected in series, and nodes N1 to Nm on the gate connection side of each MOS FET Q d 1 to Q d m have capacitors (C1e, C2, . . . - Cm is connected. Two clock pulses φ and T, which are supplied from the control circuit 9 and have an opposite phase relation to each other, are applied to opposite terminals of each of the capacitors C1 to Cm. %Nru.

When the clock pulse φ changes to a high level t, the nodes Nl, N3 . Because the level of ... is raised,
MO8FETQdz, Qda-... are momentarily turned on, and nodes N,, N3... The charge of ... is the node N
,,N4,... is sent to the side.

At this time, MO8FETQdz -Qd4. . . . are in the off state, so that charges do not flow in the opposite direction (toward the VCC supply side). Next, when the clock signal φ changes to a high level, the even-numbered signal (shita C2t C4
y... via node N 2 g N 4 t・
The level of... is raised, MO8FETQd2
g Qd+ + ··· to nodes N,, Ns
.

Charge is sent to the ... side.

In this way, the charge is gradually sent to the output terminal side, thereby increasing the output voltage of the charge pump 10. Since the charge pump 10 has a little loss at each stage, it is not possible to boost the voltage by 5V at each stage, but by connecting MO8FETQd and capacitor C in an appropriate number of stages, the desired voltage can be obtained. For example, as in the embodiment, when it is desired to generate a voltage of 20 to 25 V with the charge pump 10, one stage consisting of MO8FETQd and capacitor C is used.
It is sufficient to connect about 0 stages.

In the case of the above embodiment, the inside of the write circuit and erase circuit on the side receiving the write voltage VPP1 and erase voltage vpP2 generated by the booster circuit 8 are operated in the same way as each stage of the charge pump shown in FIG. It is also possible to provide one stage (or several stages) with a similar configuration to boost the voltage and compensate for loss along the supply path from the booster circuit 8.

[Effect] A booster circuit is provided that can generate two different voltages depending on the signals that control writing and erasing, and when erasing data, a higher voltage than when writing is applied to the nonvolatile memory element in the opposite direction to generate charge. Since the charge injected by the write voltage is pulled out by a higher voltage, the erase time is shortened to the same level as the write time, and as a result, all data in the EEPROM device can be rewritten. This has the effect of significantly shortening the time required.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the booster circuit 8 in the embodiment described above is not limited to the configuration of the embodiment shown in FIGS. 3 and 4, and various modifications can be considered. Further, the clamp diodes D1+D2 do not need to be formed on the same chip, and can be externally attached diodes.

[Field of Application] In the above description, the invention made by the present inventor has been mainly explained in relation to the application field of the invention, which is an EEPROM device using MNOS as a memory element, but the present invention is not limited thereto. The bloating gate tunnel injection type MOSFET can be used in all semiconductor memory devices using low electrically programmable and erasable nonvolatile memory elements.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of an EEPROM device to which the present invention is applied. FIG. 2 is a circuit diagram showing an example of the configuration of a memory cell of the EEFROM device. FIG. 3 is an example of a booster circuit. FIG. 4 is a circuit diagram showing a configuration example of a charge pump. FIG. 5 is an explanatory diagram showing the relationship between write voltage and erase voltage and time required for writing and erasing. 1...Memory array, 2a, 2b1...X system selection circuit, 3...Y system selection circuit, 4...Sense amplifier, 5...Y decoder, 6... Input/output buffer circuit, 7... write block circuit, 8... boost circuit,
9...Control circuit, 10...Charge pump, Q
m...Memory element (MNOS), Qs...Selection switch MO8FET, WL...Word line, DL...
...Data line, D1pD2...Clamp diode, Ql, Q2...Switch MO8FET. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] 1. A semiconductor memory device comprising a memory array consisting of non-volatile memory elements, in which data can be electrically written and erased based on an externally supplied power supply voltage. A booster circuit capable of generating two types of voltage higher than the booster circuit is provided, and the lower voltage generated by the booster circuit is used to write into the storage element, and the higher voltage generated by the booster circuit is used to write to the storage element. A semiconductor memory device characterized in that information stored in the memory element is erased by voltage. 2. The semiconductor according to claim 1, wherein the booster circuit comprises a charge pump circuit and clamp means for fixing the voltage boosted by the charge pump circuit to a constant level. Storage device. 3. The clamping means is connected in series with at least two clamp diodes each having a different breakdown voltage;
and switch means which are turned on during writing or erasing, respectively, and are formed so that the breakdown voltage of each of the clamp diodes matches the writing voltage and the erasing voltage, respectively. The semiconductor memory device according to scope 2.