JPS61240498A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase the degree of integration by constituting a 1-bit S-RAM cell with 3 elements, namely, a resistance element whose current/voltage characteristics is linear, a negative resistance element whose current-voltage characteristics become negative in the intermediate zone and a transistor having switching characteristics. CONSTITUTION:The memory cell is comprised of a switching element 1, a resistance element 2 with linear current-voltage characteristics and a negative resistance element 3 whose current-voltage characteristics become negative at the intermediate zone of the characteristics curve. When a constant DC voltage Vcc is impressed on the series connected circuit of the resistance element 2 and the negative resistance element 3, the current I and voltage V in a node 4 are obtained as to stable points, I1, V1 and I2, V2. In reading the contents stored in the cell, set the word line to H and apply voltage of the node 4 on the data line and detect V1 or V2. For example, impress 5V or OV on the data line and with the word line set at H, write '1' or '0' state in the node 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device with a new memory cell structure, and in particular to a small static random access memory (1 area) that enables high integration. Below 5-RA
The present invention relates to a semiconductor device having a cell structure (abbreviated as M).

[Background of the invention]

A conventional 5-RAM cell typically consists of 6 elements.

In other words, it consists of six transistors or two resistors and four transistors, so it is difficult to reduce the area, and it is a dynamic random access memory (hereinafter abbreviated as D-RAM). Two elements like a cell (one transistor and one capacitor)
Compared to a semiconductor integrated circuit device consisting of a semiconductor integrated circuit device, the degree of integration was only 1/4 when the same processing technology was used.

For example, when using 2/1m processing technology, D-RAM
256 bits (more precisely 262,144 bits) can be integrated on one chip, whereas 5-RA
M has 64 bits (65,536 bits) and D-RA
Only 174 bits of M can be integrated. The reason for this is that, as described above, the number of elements constituting the cell is as large as six.

[Purpose of the invention]

An object of the present invention is to be able to configure a 1-bit 5-RAM cell with three elements, and to use the same processing technology to create a D-RAM cell.
It is an object of the present invention to provide a semiconductor device that makes it possible to realize a 5-RAM with the same degree of integration as M.

[Summary of the invention]

The present invention is characterized in that, in order to achieve the above object, a resistance element whose current-to-voltage characteristic is linear, a negative resistance element whose current-to-voltage characteristic becomes negative in the intermediate region, and a transistor having switching characteristics. 5- are formed on the same semiconductor substrate, the resistance element and the negative resistance element are connected in series, and the transistor is connected to the connection portion thereof;
The reason is that it constitutes a RAM cell.

Fig. 1 is a basic circuit configuration diagram for explaining the operating principle of the 5-RAM cell in the present invention, and Fig. 2 is a current (I)-voltage (V) characteristic diagram at node 4 in Fig. 1. It is. The memory cell according to the present invention includes one switching element 1, one resistance element 2 whose current-voltage characteristic is linear, and one negative resistance element whose current-voltage characteristic is negative in the middle region of the characteristic curve. It consists of a resistance element. As is clear from the IV curve at node 4 shown in FIG. Vcc is the applied voltage).
1), the voltage v at node 4 of (I2, V2)
1 and (2) are detected by the switching element 1.

Memory read/write operations as a 5-RAM of the configuration shown in FIG. 1, which is composed of three elements, will be explained using FIGS. 1 and 2. Resistance element 2 and negative resistance element 3 shown in FIG.
By applying a constant DC voltage VCC to the series connection circuit, node 4, which is the intermediate connection point of the series connection,
The current and voltage V at are at two stable points I0. Obtained as V and 2゜■. This V and v2 are detected by the switching element 1 whose one end is connected to the node 4. That is, when reading the contents stored in a cell, by setting the word line of switching element 1 to "High", the voltage of node (node) 4 is applied to the data line, and this voltage is applied to the data line. By measuring with a connected voltage measuring means (not shown), vl or v2 is detected. This voltage difference is determined by the voltage Vcc applied to the resistance element 2 and the resistance value of the resistance element 2. For example, if VCC is 5V,
If the resistance value is about 1~LOGΩ, the logic level R1j#
The state can be set to 4.5V, and the level “O” state can be set to about 0.2V, and the logic amplitude is several V, which is different from the normal D
- It is about 100 times larger than the logic amplitude of RAM, which is about 50 mV, and is suitable for large-scale integration.

On the other hand, when writing memory contents, 5V is applied to the data line.
Alternatively, by applying Ov and making the word line "High", the node (node) 4 is set to "1" or "0".
"state is written. At this time, a current obtained from the current vs. voltage characteristic of the negative resistance element 3 flows through the switching element 1, and the two stable points (0, V) and ( I!, V, ).The switching speed during writing is determined by the transconductance of the switching element 1, so it is important to increase the transconductance of the switching element 1.

As described above, the memory cell consisting of the three elements shown in FIG. 1 can read the stored data without destroying it, and can always retain information.
The operation will be performed as follows.

[Embodiments of the invention]

An example device of the present invention and an example of its manufacturing process will be described below.

Embodiment 1 In this embodiment, a device having a basic structure as a 5-RAM cell will be described using the cross-sectional views shown in FIGS. 3(a) and 3(b). First, as shown in FIG. 3(a), after forming a gate insulating film 12 and a gate 13 on a silicon substrate 11, a source 14. drain 15
form. Here, the surface concentration of the source 14 and drain 15 is set to a value sufficient to form a tunnel junction in the completed stage of the device, that is, 1, at which band degeneration begins.
Must be greater than or equal to 0"an-". Next, Figure 3 (b
), a high concentration epitaxial layer 16 is formed on the drain 15, and a high resistance layer 10 electrically connected to the drain 15 is further formed. The impurity concentration of the high concentration epitaxial layer 16 is 10'' (!) at which band degeneration begins.
It needs to be 11-' or more. This high concentration epitaxial layer 16 forms a tunnel junction with the drain 15 and corresponds to the negative resistance element 3 shown in FIG. 1, and the high resistance layer 10 corresponds to the resistance element 2 shown in FIG. moreover.

A transistor formed by a gate 13, a source 14, and a drain 15 corresponds to the switching element 1.

The source 14 and drain 15 and the highly doped epitaxial layer 16 need to be of opposite conductivity types, and therefore the silicon substrate 11 and the highly doped epitaxial layer 16 have the same conductivity type.

Example 2 In this example, a specific example of the high resistance layer 10 shown in FIG. 3(b) will be described.

FIG. 4 shows a case where a polycrystalline silicon layer (hereinafter abbreviated as poly-Si layer) is used as the high resistance layer io in FIG. , a source 14, a drain 15, and a high-concentration epitaxial layer 16 on this drain are formed in this order in the same manner as in FIG. 3(b), and then an interlayer insulating film 17. After forming the element isolation oxide film 18, a poly-8i layer 19 is deposited, and a high concentration impurity diffusion layer 20 is formed in the contact portion of the poly-Si layer 19. This poly-
Since the S L layer 19 can provide a resistance of about 10 GΩ per 1 m of length, it is possible to reduce the current of the memory and improve the performance.

FIG. 5 also shows po as the high resistance layer 10 in FIG. 3(b).
ly-S i layer is used, but the structure is different from that in Fig. 4.
As shown in FIG. 5(a), this is an example in which a groove is formed in the substrate and a poly-Si layer as a high resistance layer is deposited inside the groove. That is, in FIG. 5(a),
The silicon substrate consists of a p-type layer 22 with a thickness of 4− formed on an n+ layer 21, and in this p-type layer 22, an n+ layer 2
A trench with a width and length of 1-1 and a depth of 4-1 or more is formed so as to reach 1-1, and an insulating film 23 is grown on the inner surface of this trench by oxidation or CVD, and after removing the insulating film at the bottom of the trench. ,
Poly-Si layer 2 as a high resistance layer by CVD method
5 is deposited, and the surface of this poly-Si layer 25 is n+
The n+ layer 24 is formed by doping.

On the other hand, using the P-type layer 22 as a substrate, as shown in FIG. 5(b), the gate insulating film 12, gate 13, source 14, drain 15, and high concentration epitaxial layer 16 are formed in the same manner as in the embodiment of FIG. The n+ layer 2 in FIG. 5(a)
By connecting 4 to the junction between the drain 15 and the heavily doped epitaxial layer 16, a 5-RAM cell is formed. The groove resistance formed in this way is made of poly-
Can be controlled by the depth of the S L layer 25, approximately 10 to 100G
A resistance value of Ω/lnn can be achieved.

Example 3 In this example, a more specific example of the configuration of the 5-RAM cell according to the present invention and its manufacturing process are shown in FIGS. 6(a) to 6(d).
).

First, in FIG. 6(a), the p-type (100) surface of a silicon substrate 11 with a resistivity of 10Ω·1 is heated at 1000° C. for 20 minutes.
After oxidizing in dry oxygen to grow a thermal oxide film 26 with a thickness of 20 nm, a silicon nitride (hereinafter referred to as SL, abbreviated as N4) layer 27 with a thickness of 50 nm is deposited by the CVD method to form a region where an element is to be formed. After removing 5L3N4Ji27, ion implantation for a channel stopper is performed, and wet oxidation is performed at too high a temperature to form a field oxide film 28 with a thickness of 0.8-
and a channel stop diffusion layer 29 is formed.

Next, in FIG. 6(b), after removing the Si and N4 layers 27 and the thermal oxide film 26, oxidation was performed in dry oxygen at 1000° C. for 15 minutes to grow a gate insulating film 30 with a thickness of 16 nm. , 0.37m thick poly-S by CVD method
An i-layer is deposited and doped to n+ type to form a gate 31, and arsenic is implanted at an applied voltage of 60 keV and an implant amount of lXl0.
Ion implantation was performed under the conditions of "an-", and a phosphosilicate glass (hereinafter abbreviated as PSG) layer was formed with a thickness of 0.6-
After being deposited to a thickness of 100° C., the source 32, drain 33, and PSG layer 34 are formed by annealing at 1000° C. for 20 minutes. At this time, the surface concentration of arsenic in each region of the source 32 and drain 33 is approximately 5X10"cm-', the number of carriers is approximately 2X10"as-', and the junction depth is approximately 0.3t1m.
It is.

Moving on to FIG. 6CQ), an interlayer insulating film 3 made of a 5i02 layer containing no impurities is formed on the PSG layer 34 by the CVD method.
After depositing a poly-Si layer 36 to a thickness of 0.21 s, a part of the drain 33 is exposed, and a poly-Si layer 36 is deposited to a thickness of 0.4 p by CVD, and an impurity-free SiO layer 36 is deposited thereon to a thickness of 0.4 s.
, an interlayer insulating film 37 having a thickness of 0.24 mm is deposited.

Further, a part of the drain 33 is exposed and a high concentration epitaxial layer 38 of phosphorus ions P4' is grown on the drain 33 by molecular beam epitaxial method (hereinafter abbreviated as MBE method). The growth conditions for the MBE method at this time were a substrate temperature of 600° C. to 800° C. and a growth rate of about 1 person/sec. The impurity was added by ionizing the impurity and irradiating the substrate with a beam of boron ions B+ at the same time as Si. The ion current was about 20 μA.

Under such growth conditions, the highly doped epitaxial layer 38 can be selectively grown only on the drain 33. However, selective growth is not essential, and after growing a silicon crystal over the entire surface, it may be patterned using a normal processing technique. The phosphorus ion P+ impurity concentration was lXl0"(m-' under the above conditions, but the impurity concentration at which the band degenerates, that is, IXIO1ga++'"3
Anything above that is fine. In addition, the high concentration epitaxial layer 38
The maximum temperature that can be used in the post-deposition manufacturing process is about 850°C.

Further, moving to FIG. 6(d), the poly-Si layer 36
After doping the contact portion of the structure, C is added again to the structure.
An interlayer insulating film 39 made of an impurity-free SiO□ layer is deposited by the VD method, and a PSG layer 40 is further deposited, and the interlayer insulating film 39 and PSG layer 40 are annealed at 800° C. for 7 times to make them dense. After forming the n'' diffusion layer 41 in the poly-8i layer 36, contact holes are formed to form the M wiring 42.

In this embodiment, the reason why the interlayer insulating films 35, 37, and 39 made of SIO layers that do not contain impurities is deposited is as follows.

This is because impurities are diffused from the PSG layer 40 into the poly-Si layer 36, making it impossible to maintain a sufficiently high resistance value in the poly-Si layer 36. therefore,
It goes without saying that these steps are unnecessary in the case of a structure in which, for example, the PSG layer does not contact the high resistance layer.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to reduce the conventional 5-RAM cell, which required six elements, to three elements. The switching speed of the element is much faster than that of conventional transistor flip-flops, so it can be used as a high-speed memory.
Therefore, high integration and high speed can be achieved at the same time, and the effects of the present invention are significant.

[Brief explanation of drawings]

Figure 1 is a basic circuit configuration diagram of a 5-RAM cell according to the present invention, Figure 2 is a current/voltage characteristic diagram at a node in Figure 1, and Figures 3 (a) and (b) are according to the present invention. A cross-sectional view showing the manufacturing process of a 5-RAM cell according to an embodiment of
Cross-sectional view of one embodiment of the high resistance layer in Figure (b), Figure 5 (a)
, (b) is a poly-
6(a) to 6(d) are cross-sectional views showing the manufacturing process of a specific example of a 5-RAM cell according to an embodiment of the present invention. Explanation of symbols 1... Switching element 2... Resistance element 3...
Negative resistance element 4... Node (node) 10... High resistance layer

Claims (2)

[Claims] (1) A resistance element with linear current-to-voltage characteristics, a negative resistance element with negative current-to-voltage characteristics in an intermediate region, and a transistor with switching characteristics are formed on the same semiconductor substrate, and 1. A semiconductor device, wherein a resistance element and the negative resistance element are connected in series, and the transistor is connected to the connection portion thereof to constitute a static random access memory cell. (2) The semiconductor device according to claim 1, wherein the negative resistance element is a tunnel diode.