JPS6322069B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device such as a MOS type dynamic RAM that stores information signals in a MOS capacitor.

The capacity of semiconductor memory devices is increasing rapidly along with advances in microfabrication technology. However, new problems have arisen as capacity increases. For example, as the number of memory cells increases, the probability of failure due to defective bits increases, leading to a decrease in yield, and as the area of memory cells decreases, the detection signal level decreases, leading to unstable operation and decreasing operating margin. thing,
etc. This problem will be explained in a little more detail using FIG. FIG. 1 shows a memory cell portion of a MOS type dynamic RAM having a one transistor/one capacitor configuration. That is, P-type Si substrate 1
For example, selective oxidation is applied to the device isolation region to a thickness of approximately
A 1 μm field oxide film 2 is formed, and a MOS capacitor is formed in the element region by a first layer polycrystalline silicon film 4 and an n ⁺ type layer 5 with a first gate oxide film 3 sandwiched therebetween. Then, a second layer polycrystalline silicon film 7 that becomes a gate electrode of a MOS transistor is formed via a second gate oxide film 6 so as to partially overlap the first layer polycrystalline silicon film 4, and this second layer polycrystalline silicon film 7 is formed to become a gate electrode of a MOS transistor. Using the silicon film 7 as a mask, a bit line 8 consisting of an n ⁺ type layer which also serves as the drain of the MOS transistor is formed by diffusion, and the entire structure is further covered with a silicon oxide film 9 by CVD method, and a contact hole is made to form a second layer of polycrystalline silicon. A word line 10 made of an Al film and in contact with the film 7 is provided. The n ⁺ -type layer 5 in the substrate region, which will become one electrode of the MOS capacitor, is formed to have a concentration of 10 ¹⁶ /cm ³ and a depth of 5000 Å by, for example, ion implantation. Although not shown in the figure, a p ⁺
A mold layer is usually formed.

To explain the operation of this memory, a negative voltage of, for example, -5V is applied to the elastic substrate 1 as a reverse bias in order to reduce the junction capacitance between the bit line 8 and the substrate 1. Further, a positive voltage is always applied to the first layer polycrystalline silicon film 4. This positive voltage is sufficient to invert the surface of the substrate 1, but due to limitations on the power supply voltage and reliability of the gate oxide film, in order to easily convert the substrate surface to an n-type with a low voltage, the method shown in the figure is used. An n ⁺ type layer 5 is formed in advance.
Writing to the memory cell is performed by applying a positive voltage to the word line 10 to make the MOS transistor conductive. When writing "1", a positive voltage is applied to the bit line 8, and the potential of the n ⁺ type layer 5 becomes a high level _VSH ; when writing "0", a normal ground potential is applied to the bit line 8, and the potential of the n + type layer 5 becomes high level VSH. The potential of ^{the +} type layer 5 becomes a low level _VSL . Information reading from the memory cell is performed by applying a positive voltage to the word line 10 while keeping the bit line 8 at a positive potential in advance to make the MOS transistor conductive. At this time, the potential of the bit line 8 takes a value corresponding to the potential of the n ⁺ type layer 5 of the memory cell, and is different from when "1" is read and when "0" is read.
The potential difference ΔV on the bit line 8 when ΔV is read out is ΔV=1/1+C _R (V _SH −V _SL ). Here, C _R is the ratio of the capacitance C _B of the bit line 8 to the capacitance C _S of the memory cell, that is, C _R = C _B /C _S ,
The capacitance C _S of the memory cell is the sum of the capacitance Cox between the n ⁺ type layer 5 and the first layer polycrystalline silicon film 4 and the junction capacitance Cjn between the n ⁺ type layer 5 and the substrate 1, that is, Cs = Cox +
It is Cjn. In order for a value proportional to this ΔV to correspond to the input of the sense amplifier, ΔV needs to be as large as possible. However, in the conventional method, the potential of the n ⁺ type layer 5 is the same as that of the n ⁺ type layer 5 and the substrate 1.
The carriers generated in the substrate 1 by thermally generated carriers and alpha particles generated in the depletion layer between
It decreases due to diffusion and inflow into the n ⁺ type layer 5.
And since the drop in V _SH is greater than that in V _SL ,
(V _SH −V _SL ) decreases with time. Normally, a refresh operation is added to compensate for this drop in write potential, but thermally generated carriers do not necessarily occur uniformly on the substrate 1, and as memory capacity increases, (V _SH −V _SL ) becomes abnormally low. The probability of memory cell occurrence increases.

In addition, in the conventional structure, for example, if the thickness of the first gate oxide film 3 is 650 Å, Cox/Cjn10,
Therefore, the memory cell capacitance Cs is determined by the so-called MOS capacitor capacitance between the n ⁺ type layer 5 and the first layer polycrystalline silicon film 4. Then, C _R in the above formula takes the value of several 10,
Since it is difficult to reduce this, it has been a cause of unstable operation of the memory or a decrease in operating margin.

The present invention provides a method for manufacturing a semiconductor memory device that solves the above-mentioned problems associated with increased capacity and miniaturization of elements.

This invention uses MOS like dynamic RAM.
In a semiconductor memory device configured by integrating memory cells on a semiconductor substrate, each of which stores an information signal in a capacitor, a MOS capacitor has a layer of conductivity type opposite to that of the substrate on the surface of the semiconductor substrate, and a capacitor on the surface of this substrate. A capacitor electrode is provided through an insulating film, and a buried insulating film is provided below the opposite conductivity type layer. When forming such a capacitor structure, the buried insulating film is provided with an opposite conductivity type layer above the opposite conductivity type layer. It is characterized by being formed by ion implantation in a self-aligned manner with respect to the mold layer.

FIG. 2 shows a memory cell structure according to an embodiment of the present invention. The difference from FIG. 1 is that a buried insulating film 25 is provided under the n ⁺ type layer 26 in the substrate region that becomes one electrode of the MOS capacitor. A specific manufacturing process for obtaining this structure will be described below with reference to FIGS. 3a to 3f. First, an oxidation-resistant mask is formed by laminating a silicon oxide film 22 with a thickness of 500 Å and a silicon nitride film 23 with a thickness of 5000 Å in the element formation region of a p-type Si substrate 21 with a resistivity of 10 Ω-cm, and then Oxidized at 1000℃ for 6 hours to a thickness of approximately 1μm
a to form a field oxide film 24; A p ⁺ -type layer may be formed under the field oxide film 24 by implanting boron ions, for example, to prevent surface inversion before oxidation. After this, the MOS capacitor forming region of the nitride film 23 is selectively removed, and nitrogen ions are implanted at an acceleration voltage of 190 KV and a dose of 3×10 ¹⁶ cm ^-2 using the remaining nitride film 23 as a mask. Phosphorus is ion-implanted at 80 KV and at a dose of 5×10 ¹² cm ⁻² to form a buried insulating film 25 made of a silicon nitride film and an n ⁺ type layer 26 b. Next, the remaining nitride film 23 and oxide film 22 are removed, and thermalization is performed at 1000°C for about 1 hour in a dry oxygen atmosphere.
A gate oxide film 27 is formed, and a first layer polycrystalline silicon film 28 doped with phosphorus by CVD method is formed thereon.
deposit c. In the step of thermally oxidizing the first gate oxide film 27, the buried insulating film 25 becomes a good insulating film.
Next, the first layer polycrystalline silicon film 28 is selectively etched to form a MOS capacitor electrode, and using this as a mask, the first gate oxide film 27 is etched to expose the substrate surface in the MOS transistor forming region. Next, thermal oxidation is performed at 850° C. for about 100 minutes in a steam atmosphere, and the substrate 21 is heated to about 1100° C.
A second gate oxide film 29 with a thickness of about 4000 Å is formed on the first layer crystalline silicon film 28, and then
A second layer polycrystalline silicon film 30 is deposited by CVD method. And this second layer polycrystalline silicon film 3
0 is patterned to form a gate electrode of a MOS transistor, and using this as a mask, the second gate oxide film 29 is etched and, for example, arsenic is diffused to form a drain/bit line 31 of the n ⁺ type layer. f to reduce the resistance of the two-layer polycrystalline silicon film 30; After this, the entire surface is covered as shown in Figure 2.
A silicon oxide film 32 is deposited by the CVD method, a contact hole is opened, and an Al film is deposited and patterned to form a word line 33, thereby completing the process.

The write and read operations of the memory cell configured in this manner are the same as those of the prior art, and therefore their explanation will be omitted.

According to this embodiment, since the n ⁺ type layer 26 and the substrate 1 are separated by the buried insulating film 25, there is no thermally generated carrier in the depletion layer of the p-n junction unlike in the conventional case. Carriers generated within the substrate by alpha particles do not flow into the n ⁺ type layer 26, and the high level V _SH of the n ⁺ type layer 26 does not decrease, so the probability of occurrence of defective memory cells is significantly reduced. . In particular, when the buried insulating film 25 is a silicon nitride film, the leakage current is small and the insulation properties are good, and the effect is large. And in this example,
The buried insulating film 25 can be formed in a self-aligned manner with respect to the n ⁺ type layer 26 by ion implantation using the ion implantation mask for the n ⁺ type layer 26 as is. That is, a MOS capacitor with a buried insulating film structure and a large capacitance can be obtained without using complicated steps.

Also, according to this embodiment, the capacity of the memory cell is
Cs is the n ⁺ type layer 26 and the first layer polycrystalline silicon film 28
and the capacitance Cox of the first gate oxide film 27 between n ⁺
It is the sum of the capacitance C _ION of the buried insulating film 25 between the mold layer 26 and the substrate 1, which is several times larger than the conventional one,
Therefore, C _R =C _B /C _S becomes several times smaller. By the way,
Under the above manufacturing conditions, the buried insulating film 25 is a silicon nitride film formed at a depth of about 5000 Å from the substrate surface to a thickness of about 1000 Å.
C _ION =1/1.3. Therefore, the output level difference .DELTA.V between "1" and "0" to the bit line 31 becomes several times larger than in the conventional case, and the input to the sense amplifier increases accordingly, greatly improving the operating margin of the memory.

In the embodiment, the buried insulating film made of a silicon nitride film was provided by nitrogen ion implantation, but the buried insulating film may be formed in the form of a silicon oxide film by, for example, implanting oxygen ions. Also, the ion implantation process for forming the buried insulating film 25 and the ion implantation process for forming the n ⁺ type layer 26 are reversed,
Alternatively, the manufacturing process can be modified in various ways, such as performing ion implantation of the n ⁺ type layer 26 after forming the first gate oxide film 27. Furthermore, although MOS dynamic RAM has been explained above, MOS static RAM
Similar effects can be obtained by applying the present invention to a type of memory that stores information signals using MOS capacitors.

As explained above, according to the present invention, a buried insulating film that is self-aligned with the opposite conductivity type layer of the substrate, which becomes one electrode of the MOS capacitor that stores information charges, is formed by ion implantation. Therefore, it is possible to prevent the occurrence of defective memory cells due to the miniaturization of elements and increase in capacity, and to provide a semiconductor memory device that has significantly improved operating margins and is manufactured using a simple process.

[Brief explanation of drawings]

FIG. 1 is a schematic sectional view showing a memory cell in a conventional MOS dynamic RAM, FIG. 2 is a schematic sectional view showing a memory cell in a MOS dynamic RAM according to an embodiment of the present invention, and FIGS. It is a sectional view of the manufacturing process. 21... p-type Si substrate, 24... field oxide film, 25... buried insulating film (silicon nitride film),
26...n ⁺ type layer, 27... first gate oxide film,
28...First layer polycrystalline silicon film, 29...Second layer
Gate oxide film, 30... Second layer polycrystalline silicon film, 31... Bit line (n ⁺ type layer), 32... Silicon oxide film, 33... Word line (Al film).

Claims (1)

[Claims] 1. When manufacturing a semiconductor memory device configured by integrating memory cells in which information charges are stored in MOS capacitors on a semiconductor substrate, the above-mentioned
The step of forming the MOS capacitor includes the steps of forming an opposite conductivity type layer on the surface of the semiconductor substrate, and forming a buried insulating film under the opposite conductivity type layer in self-alignment therewith by ion implantation. A method for manufacturing a semiconductor memory device, comprising the step of forming a capacitor electrode on the surface of the substrate via a capacitor insulating film.