JPS61227477A - Picture processor - Google Patents

Abstract

PURPOSE:To obtain a uniform picture over a wide magnifying range by reading a picture data based on a clock missing regularly in response to the magnification. CONSTITUTION:A pickup head 10 reads a color tone and density of an original picture 2 and an original picture element data is stored as it is in a picture memory device 18 at magnification. In the read of the picture data from the memory device 18, a memory address generating section 19f generates an address signal in response to the signal from a magnification setting section 20, (m-n) pulses are missing from m-set of clock pulses of a picture element clock CK1 in response to the setting magnification n/m, the same address is kept accessed in the missing part, and after the picture element having the same content is given continuously for plural number of times, the next picture element is processed, the picture data is read while the picture is being magni fied, the picture is recorded to a photosensitive member 4 via an interpolation operating circuit 21, a dot generator 22 and an exposure head 11. The operations at reduction are conversed to those at magnification.

Description

[Detailed Description of the Invention] (Industrial Application Field) This invention relates to an image processing device, and in particular, to an image processing device that inputs image data and stores it in a storage means, and then outputs this image data at a specified magnification. The present invention relates to improvements in image enlargement processing in such image processing apparatuses.

(Prior art and its problems) As an image scaling technology in image processing devices such as plate-making scanners, laser printers, and facsimiles, image data is temporarily stored in a memory with a capacity of, for example, one scanning line. The pixel clock (or memory address) when writing image data and the pixel clock when reading image data from the memory are relatively changed according to the magnification, thereby achieving an increase or decrease in the number of pixels. The technology is known. Some of them are listed below along with their features and drawbacks.

■The first method is to change the pixel clock frequency between writing and reading by using a frequency dividing circuit in the PLL circuit and changing the frequency dividing ratio in the PLL circuit (for example, Kosho 52-50561). This method has few problems at low frequencies, but
When trying to obtain high-magnification output in a device that requires high-speed processing, that is, high-frequency processing, PLL
This has the disadvantage that the circuit configuration becomes difficult and a high-speed processing circuit (device) is required, leading to an increase in the cost of the device.

■The second method is to use a pixel clock in which an extra pulse is inserted between the regular periodic pixel clocks, that is, a synchronization pulse train (for example, Japanese Patent Laid-Open No. 53
-11601).

If this new pixel clock is used to specify the write address to memory and the original pixel clock is used to specify the read address, the number of reproduced pixels of a certain original image can be read from the original image (sampled ) is increased compared to the number of pixels, resulting in an enlarged image output. Conversely, if the new pixel clock is used only for addressing during readout, a reduced image output can be obtained. However, in this method, another pulse must be inserted between a pulse train having a predetermined period, which naturally imposes restrictions on specifying the magnification when changing the magnification. -11601
In the embodiment disclosed in , the magnification range that can be output is limited to 50% to 200%. Also, the magnification setting interval (resolution) is [(n±1)/nl, where n is an integer.
x100% or 1/2.2/3. ...1. ...
There is a drawback that it is limited to 3/2.2/1.

■The third method is to write image data to memory at a fixed frequency (pixel clock) or sampling pitch, and when reading, part of the memory address is omitted (when reduced) or duplicated (when enlarged). This technique aims to reduce or increase the number of output pixels by accessing the pixels (for example, Japanese Patent Laid-Open No. 54-65601 and Japanese Patent Laid-open No. 54-35613). With this technology, by averaging the distribution of the omitted or overlapping addresses mentioned above, it is possible to considerably reduce the non-uniformity of the output image during reduction/enlargement, but the circuit configuration for this averaging is complicated. The problem is that it becomes. This tendency becomes more pronounced as the zooming range becomes larger.

As described above, the conventional variable magnification system has a problem in that it is difficult to obtain an image in which added pixels are evenly distributed over a wide variable magnification range with a relatively simple circuit configuration.

In addition, since the various devices described above perform output using only the pixel data written in the memory, if the same pixel data is repeated in the reproduced image during enlargement, it is necessary to There is also the problem that after several pixels having one tone are consecutive, the pixels suddenly shift to a pixel having another tone, and the spatial tone change in the reproduced image is not smooth.

(Objective of the Invention) As described in the above-mentioned prior art ■■, the present invention performs magnification conversion on image data picked up at a constant sampling pitch regardless of the magnification.
To provide an image device which is intended to overcome the above-mentioned problems and is capable of obtaining an image in which added pixels are uniformly distributed over a wide variable magnification range with a relatively simple circuit configuration. is the primary purpose.

A second object of the present invention is to provide an image processing device that can smooth spatial gradation changes in a reproduced image during enlargement and obtain a natural image.

(Means for Achieving the Object) In order to achieve the above-mentioned object, the image processing apparatus according to the present invention includes: ■ a periodic first clock ( A second clock (CK
3) a second clock generating means for generating; and (2) reading for reading out the image data stored in the image data storage means based on the first clock on the basis of the second clock during enlargement; (2) interpolation data generation means for generating at least one interpolation data by interpolating between the original pixel data that is the read image data at the time of enlargement; and interpolation data applying means for selectively applying the interpolation data to additional pixels added due to the omission of the first clock based on preset selection data.

(Embodiments) Hereinafter, embodiments of the present invention will be sequentially described with reference to the drawings.

(A) FIG. 1 of flIi is a schematic configuration diagram of an embodiment in which the present invention is applied to a color scanner for cylindrical scanning plate making; however, the present invention is not limited thereto; It can also be used in black-and-white scanners, plane-scanning plate-making scanners, and the like. In FIG. 1, image signals are indicated by double line arrows, control pulses are indicated by solid line arrows, and control signals for the sub-scanning drive motor are indicated by dotted line arrows.

In this color scanner 1, an original image drum 3 on which an original image 2 is wound, and a recording drum 5 on which a photosensitive material 4 is wound,
It is fixed to the drum shaft 6. This drum shaft 6 is rotated synchronously by the driving force of a motor 9 applied through a pulley 7 and a belt 8. On the other hand, a pickup head 10 and an exposure head 11 are respectively disposed so as to be movable parallel to the drum shaft 6, facing the original image drum 3 and the recording drum 5, and these are driven by a driving pulse motor 12. .13 to the feeders U14 and 15, respectively, by the driving force applied thereto.

The pickup head 10 incorporates a color separation optical system, a plurality of sets of photoelectric conversion elements, etc., and reads the tone and density of the original image 2 to generate color separation image signals of three primary colors. This color-separated m-image signal is subjected to arithmetic processing to correct the color tone and gradation in the color correction and gradation correction circuit 16, and is converted into an image signal for recording. The converted signal is given to the A/D converter 17, and this A/D converter 1
In step 7, this signal is sampled in accordance with a periodic pixel clock CK1 from a timing control section 23, which will be described later, and sequentially A/D converted.

The image signal after A/D conversion is then transferred to the image memory device 18.
given to.

On the other hand, in this apparatus, a desired reproduction image magnification is specified in advance in a magnification setting section 20 which can be configured by a CPU or a combination of a digital switch and a decoder. When writing image data to the image memory 18, the memory address generating section 19 generates an address signal in a manner described in detail later in response to the signal from the magnification setting section 20, and the image memory device @ The above image data is written to that address of 18. The same goes for reading out image data from the image memory device @18.
Image data is read from the address indicated by the output of the memory address generation section 19 and input to the interpolation calculation circuit 21 at the next stage. When the specified magnification is enlargement, this interpolation calculation circuit 21 performs interpolation between the read pixels in the manner described later, and when the specified magnification is equal magnification or reduction, no interpolation is performed and the output is used to generate halftone dots. Give to container 22. Halftone dot generator 2
2 compares the image line signal input here with a reference halftone dot signal to generate a halftone dot output, and performs image recording (reproduction) on the photosensitive material 4 via the exposure head 11.

On the other hand, the timing control unit 23 synchronizes the pixel clock CK1 and the main scanning 1 in synchronization with the pulse input from the pulse generator PG that is synchronized with the rotation of the drum shaft 6.
Main scanning period clock G that indicates the start or end of a batch
K2 and control signals to the driving pulse motors 12 and 13 are generated and applied to the various parts shown. The remaining mechanical configuration is the same as that of well-known facsimile technology, so a description thereof will be omitted.

B) IllllI Here, in order to facilitate understanding of this invention, one technology closely related to this invention will be explained first. This technology is an undisclosed technology proposed by the inventor of this invention, and is a technology that achieves the above-mentioned first objective of this invention. An implementation example of this related technology will be disclosed below.

B-1 Structure of Technical Example In this technical example, compared to the structure shown in FIG. 1 described above, the interpolation circuit 21 is not provided and the detailed structure of the memory address generation section 19 is different. The main difference is that FIG. 2 is a block diagram showing details of the memory address generation section 19a in such a technical example, and the surrounding circuit configuration, etc.
The reference numerals shown in FIG. 1 apply mutatis mutandis. In the same figure, this memory address generation section 19a is operated by a pixel clock C supplied from the timing control section 23 of FIG.
It includes an address counter (programmable N-ary counter) 31 that inputs K1.

This address counter 31 is loaded with a predetermined load value from the magnification setting section 20 configured using the CPU.
It is given in advance via 2. As this load value, when the set magnification is n/m (n, m are integers), if the address counter 31 is a down counter, the number (m-1) obtained by subtracting 1 from m, or When the address counter 31 is an up counter, the number of bits of this address counter 31 is 21 to m.
(2'-m) can be used. By doing so, the output of the address counter 31 provides a circular address output that returns to the original state every time the pixel clock CK1 generates m pulses.

The count output of this address counter 31 becomes the address input of the clock memory 33. In this clock memory 33, data of m words x 1 bit, which is determined according to a predetermined rule (described later) depending on the magnification factor, is given in advance from the magnification setting section 20 and stored. One word at a time is read from the accessed address and output to the AND circuit 34. This A
In the ND circuit 34, by gating the pixel clock CKI with the output of the clock memory 33, a clock CK3 (a second clock CK3) in which clock pulses are regularly omitted from the array of pixel clock pulses CK1 and clock pulses is generated.
tsuku) occurs.

The selector 35 at the next stage inputs the pixel clock CK1 and the clock CK3, and supplies one of them to the address counter 36. The selection operation is performed by the output of an Ex, OR circuit 39 whose inputs are the output of the flip 70 tube 37 that selects writing and reading, and the output of the register 38 that selects reduction and enlargement. The selection is made by selecting the clock CK3 when reading image data from the image memory device 18 during enlargement, and when writing image data during reduction, and selecting the pixel clock CKI in other cases. It is done like this.

In other words, for example, in Figure 2, S = 1 and 6 inputs, $ = 0
In this way, the B inputs are selected respectively. Note that the flip-flop 37 receives the main scanning synchronization clock CK2 as an input, and the register 38 receives its input from the magnification setting section 20.

The address counter 36, to which the clock selected in this manner is applied, counts the input clock, and
The address output is given to the image memory device 18, and image data is written or read in the image memory device 18 according to this address.

(B-2) Storing the clock memory 33 Next, we will explain the data contents that should be stored in the clock memory 33. This clock memory 33 has pixels as follows depending on the set magnification. The magnification setting section 20 calculates which clock pulses to be omitted from among the clock pulses CK1 and 0, and stores the calculation results each time. In this related technology example, when the magnification is n/m,
In the AND circuit 34, by taking the logical product of the pixel clock CKI and the output of the clock memory 33, (m-n) clock pulses are omitted from the m clock pulses, thereby creating the clock CK3. There is.

Therefore, the data to be stored in the clock memory 33 is 0'' for (m-n) pulses out of m pulses of the pixel clock CKI, and 1 for the remaining n pulses. Furthermore, it is desirable that the "1"s for the n pulses be distributed as evenly as possible.

Therefore, in this related technology example, we collect several consecutive words one after another, multiply the number of words by (n7m),
Every time the value exceeds one word, "1" is assigned to the last word, thereby obtaining an average distribution. This concept is illustrated in Figure 3.

In FIG. 3, in the case of a reduction rate of 30% (n=-3, m=10), the horizontal axis represents the bit order of the address or data of the clock memory 33 (1=1.2, . . . ).

This is a graph where (n7m)XI is plotted on the horizontal axis. As shown in the figure, (n7m)Xl increases linearly with respect to . Each exceeds 3. Therefore, in this example, when considering a set of words from the first to the first, and increasing ■ sequentially, new words that can be set to "1" will appear at 1 = 4, 7, and 10. Therefore, the word DATA (I>) corresponding to these values of 1 is set to 1''.

However, when considering the entire data up to I=m (10 in the illustrated example), if 1=m and (n7m)XI is strictly n
As can be seen from this, strictly speaking, n bits out of m bits are 1''.

In other words, the average distribution can be obtained with extremely high precision approximation while strictly observing the specified magnification.

FIG. 4 is a flowchart illustrating a procedure when the magnification setting section 20 creates data to be stored in the clock memory 33 according to this rule. This figure 4 will be explained below, but the relationship between the quantities called rAJ and "A1" and ■ in figure 4 is illustrated in the above figure 3, so please refer to this figure as well. .

First, in step S1, I=1. A=0 is set, and in the next step S2, the integer part of (n7m)XI is calculated and set as A1. Then, in step S3, the consistency between A1 and A is determined. For example, in the example of FIG. 3, when I=1, A1=A=
Since it is O, the process advances to step S4 and sets the data DATA(I) to be given to the first word to 0''.Then, in the next step S6, I is increased by 1 and A is changed by A1 at that point. The process is redefined and the process proceeds to step S7.Then, if I is not greater than m, the process returns to step S2.In the example of FIG. 3, I=1.2
．． This operation is repeated for each of 3, but then suppose that I=4. Then, in step S2, A1=1 (see A1 corresponding to I=4 in FIG. 3).

), so in step S3, A1≠A,
Proceeding to step S5, DATA(I) is set to "1".

Then, in step S6, A=A1 (=1). Then, in the next processing loop (1=5), A1=A(=1)
Therefore, DATA(1) becomes "0" again. In this way, DATA(1) for each {circle around (1)} is defined, and when 1>m, the data creation process is completed.

As illustrated in FIG. 3, the processing in FIGS.
/m) Taking advantage of the fact that A1, which indicates an integer portion of XI, and A, which follows A1 with a delay of one word, do not match only when A1 changes, the I DATA(1) for the data is set to "1". It can be understood from this figure that this discrepancy occurs in the area indicated by the small white circle on the graph of (n/m)XI in FIG.

Table 1 shows the data to be stored in the clock memory 33, determined based on such rules. For example, if you refer to the row with a magnification of 30% (m-10°n-3), you will see the data shown at the bottom of Figure 3 above (however, in Table 1, it is written starting with "1" for convenience). ) is shown.

Table 1 (Continued) Table 1 (Continued) By the way, the above explanation was about reduction, but reduction and enlargement mean that the clock CK3 obtained based on this data is transferred to the image memory device 18. The only difference is whether it is used for writing or reading, and the same data contents may be used in correspondence. In Table 1, data regarding reduction to n7m times is m
This is why the data is the same as the data regarding enlargement to /n times.

(Next to B-3II, the operation of this technical example will be explained focusing on the characteristic parts with reference to the timing diagram shown in FIG. 5. This FIG. 5 shows m-3, n=2. In other words, this is an example of operation when the image is enlarged to a magnification of 150% and reduced to a magnification of 66%.

150% expansion First, the operation when enlarging to a magnification of 150% will be described.

Prior to inputting the j image, this magnification m(1
50%). Then, the magnification setting section: O is the fourth
According to the flowchart shown in the figure, data of m (=3) words×1 bit to be stored in the clock memory 33 is calculated and stored in the clock memory 33. At the same time, the value of m is loaded into the address counter 31 via the register 32, and a signal is further given to the register 38 to instruct "enlargement".

At the time when reading from the original 2 is started, the main scanning period clock CK2 is applied, and the flip 70 knob 37
is in a state where it instructs "write", and the address counter 36 is cleared. Then, the pixel clock CK1 from the timing control section 23 (FIG. 1) is applied periodically as shown in FIG. 5(a). The address counter 31 counts this pixel clock CK1 and cyclically outputs an address signal that increases or decreases every pulse, every m pulses of the pixel clock CK1. The clock memory 33 uses this output as an address input and sequentially outputs the data stored therein (FIG. 5(b)). The AND circuit 34 that has received this data gates the pixel clock CK1 according to this data, and generates a signal as shown in FIG. 5(C).
A clock CK3 is generated in which the pulses of the pixel clock CK1 are regularly omitted.

On the other hand, at this point, the output of the register 37 is "1"
(write) and the output of the register 38 is "O" (enlargement), so the output of the Ex, OR circuit 39 becomes "1". As described above, the selector 35 selects six inputs for S=1, so in this case, the pixel clock CK1 is applied to the address counter 36. Therefore, the address counter 36 outputs an address (fifth factor (d)) according to the periodic pixel clock CK1.
)) is generated and provided to the image memory device 18.

Therefore, during writing, the original pixel data input to this device is stored as is in the image memory device tia.

Next, consider the read operation during enlargement.

In this case, the difference from the write operation described above is as follows. That is, the flipflop 37 is brought into the "O" (read) state by the main scanning period clock GK2. Then, the output of the EX, OR circuit 39 becomes "0", and the selector 35 selects the B input, that is, the clock CK3. Then, a pulse is given to the address counter 36 in the form shown in FIG. 5(C), and as shown in FIG. 5(e), the same address is accessed at the location where the pulse of clock CK3 is missing. continue. For this reason, when reading image data from the image memory device 18, pixels with the same content are given multiple times in succession at these locations, and then the next pixel is moved on, causing the image to become enlarged. reproduced in form.

The operation during the 66% reduction is the opposite of the above-mentioned enlargement. That is, in order for the register 38 to instruct "1" (reduction), the selector 35 selects the O clock CK3 during writing and the pixel clock CK1 during reading. Therefore, as shown in FIG. 5(f), during writing, an address signal according to the clock CK3 is generated, and image data is recorded along the main scanning direction on the original 2, with pixels omitted in the middle. will be carried out. Then, during readout, the pixel density is
Since the image is read by K1, a reduced reproduced image is obtained.

In this way, by causing a drop in the clock pulse, pixel padding (when enlarging) and interrogation (when reducing) are performed, respectively.

(B-4) Effects of related technology examples and p1 According to the above technology examples, since n and m can be determined arbitrarily, it is possible to perform image processing over a wide range of magnification, and the circuit The configuration is also simple. In addition, by making the missing pulses have an average distribution as illustrated, the non-uniformity of the reproduced image is reduced. Therefore, this related technical example achieves the first objective of the present invention.

However, the image reproduced during enlargement also includes a problem due to padding of pixel data. For example, in Figure 6 (
The above enlargement process (250%) is applied to the original image data as shown in a).
) is added, the image data becomes as shown in FIG. 5B, but when sharpness enhancement processing is added to this, a partial reversal of gradation changes occurs as shown in FIG. 2C. Furthermore, when enlarging processing is applied to an original image that has diagonal lines in a direction different from both the main scanning direction and the sub-scanning direction as gradation boundary lines, as shown in FIG. 7(a), it becomes as shown in FIG. 7(b). , resulting in a step-like gradation boundary line with a large step difference.

(C) Details of Embodiment Therefore, in the present invention, while incorporating the technical idea of the above-mentioned related art example, interpolation processing is added at the time of enlargement in order to solve the above-mentioned problems. FIG. 8 is a block diagram showing the detailed configuration of the embodiment shown in FIG. 1 described above, and the differences from the technical example shown in FIG. 2 described above will be explained as follows.

First, compared to the memory address generating section 19a of the above-mentioned related technology example, the memory address generating section 19 has a 2-bit data input/output to the clock memory 40, and the stored contents are new information (described later). contain;
It has the following characteristics: (1) One input of the AND circuit 41 has a 2-bit configuration, and (2) the clock CK3 and the output of the clock memory 40 are supplied to the interpolation calculation circuit 21. On the other hand, the output of the image memory device 18 is output from the two D-flips 70 included in the interpolation calculation circuit 21 (
The above clock CK3 is applied to the latch input of this D flip-flop 51.52, which is hereinafter referred to as D-FF and is applied to a series connection of >51.52. And the respective outputs of these two D-FF51.52 ■, ■2
are both given to three linear interpolation circuits 538 to 53G.

These linear interpolation circuits 538 to 53G are connected to the above V1, v
Input 2, (v +V2)/2...(1)(2
V +V2)/3...(2)(■
+2V2)/3 ... calculate the three types of linear interpolation values in (3), and select B-D of the selector 54.
Use as input. Further, as the six inputs of this selector 54, the output 1 (original pixel data) of the D-7 lip 70 knob 52 is applied as is. And A-D 4
One of the two inputs is selected by the 2-bit output of the clock memory 40 and becomes the Y output. In this embodiment, this selection input is "0" uln, u2n.

When specifying "3", D, C, B.

The device is configured to select each of the six inputs. Therefore, in this case, '3'' represents the original pixel data, II 21
1 means the signal according to the above formula (1), "1" means the signal according to the above formula (2), and "O" means the signal according to the above formula (3). "OII~" in Table 2 below
3" represents this. Furthermore, this selector 5
The output of 4 and the output 1 of the D-7 lip-flop 52 are input to the selector 55, and the selector 55 uses the reduction/enlargement instruction input given from the magnification setting section 20 via the register 38 as the selection input. When reducing, six inputs are required,
When enlarging, select each of the B inputs and use halftone dot generator 2.
Give to 2.

Contents stored in the clock memory 40 in the example Next, the contents of data to be stored in the clock memory 40 will be explained. In the above case, this data is 1
However, this time it is 2-bit data, which includes selection data for selecting interpolation data. In this embodiment, according to the rules adopted in the related technology example described above, clock pulses are regularly dropped from the pixel clock CK1, and clock pulses are added to newly added pixels corresponding to the dropped pulses. , we are trying to give a value by interpolating the data of the original pixels located before and after that. However, this embodiment targets enlargement up to 300%.

This interpolated value differs depending on the positional relationship between the additional pixel and the original pixel, and as shown in FIG. 9, (1) One additional pixel P. When is at the gate of two original pixels,
The additional pixel P. , if the two additional pixels P and P2 are consecutive and they are between the two original pixels, then In some cases, a value obtained by weighting the pixel data of an original pixel closer to the additional pixel P 2 and an original pixel farther away from the additional pixel P 2 and P2 is given, respectively. This is so-called linear interpolation.

Therefore, it is necessary to know which of the outputs of the image memory device 18 is an additional pixel and the positional relationship between the additional pixel and the original pixel. By modifying and using the data (Table 1) for indicating the pulse dropout rules used, the former information can be used as the word indicating the dropout in this data, and one of the three types of values described below can be used. By making them take one of the two positions, we try to indicate their positional relationship.

FIG. 10 shows such value assignment processing. This 10th
In the figure, a routine 510 performs the processing (step 85) in the case of AI-A in the routine shown in FIG.
Since they are the same except that DATA (I)-3 is closed, repeated explanation will be omitted.

Therefore, at the stage where routine S10 is completed, data in which 111 II is "3" in the data in Table 1 has been obtained.

In the next step S11, it is determined whether the specified magnification means enlargement, and if it is not enlargement, there is no need for interpolation and the process is completed as is. In the case of enlargement, proceed to step 812, set it to I-1, and
Using the data of the mth word, the 0th word is
Further, each (m+1)th word is defined using the data of the first word. In other words, when the additional pixel is located at the position corresponding to the 1st or mth word,
This definition is made in advance for the purpose of knowing the data of the pixels before and after that. This takes advantage of the fact that this data is used cyclically and repeatedly.

In the next step S13, the first word is “3”.
”, and if it is “3”, the process advances to step 819. In other words, since the pixels given by the clock pulses that are not subject to deletion are original pixels, there is no need for interpolation. Yes. On the other hand,
If it is determined in step 813 that the first word is not "3", then in the next step S14, (I
-1) Check whether the th word indicates "3". If “3” is not specified, step S1
5, set the word to O”.

This is because if the missing pulse part is processed and the pixel before one of the resulting additional pixels is also an additional pixel, it becomes a pixel corresponding to P2 in FIG. 9(b). , with the operation described below (V +2V
2) “0” to indicate that the value of /3 is to be assigned.
That is, it gives

In step 814, the (1-1)th word is “
3'', the next step 816 checks to see if the (II1)th word is ``3n''. If it is not 63', the first word is set to "1" in step 317. In other words, in this case, in order to indicate that the adjacent words are the original pixel and the additional pixel, (2V1+V2)/3 is calculated assuming that the positional relationship is as shown by Pl in FIG. 9(b). He tries to give. Then, in step S16, (1+1
')'th word is also determined to be "3", the 9th word
P in figure (a). This word indicates the additional pixel sandwiched between the original pixels, so (V1+V2)/
In order to give 2, let this word be "2".

After such data is added, in step 319, ■ is incremented by 1, and in step 20, it is determined whether ■ is larger than m. If (2) is less than or equal to m, the process returns to step 812 and repeats the above process, but if it becomes larger than m, the process is completed.

Table 2 shows the data obtained by such processing, where all 1'' in Table 1 becomes 3'', and 0 in Table 1 corresponds to any positional relationship in Figure 9. It can be seen that it is reset to one of "0" to "2" depending on whether it exists.

Table 2 (continued) (blank space below) (E) Operation of the male side The operation of this embodiment having the above configuration can be explained with reference to the above-mentioned FIG. 8 and the timing chart shown in FIG. 11. I will explain. However, portions that operate in the same way as the related technology example described above will be briefly described. Also, here, m=5. n=2, i.e. 250% expansion and 40
Consider % reduction.

250% (F) When enlarging to 250% for K people, the magnification setting unit 20 that has set this magnification sets m according to the flowchart in FIG.
(=5) words x 2 bits of data (250% of Table 2)
'' line) is calculated and stored in the clock memory 40 of FIG. 8. Also, the register 38 is set to the "enlarged" state.

When reading of the document 2 starts, the flip-flop 37
is in a state where it instructs “write”, and address counter 3
6 is cleared. The other address counter 31 has previously been loaded with the value m (=5), and the input pixel clock CK1 (FIG. 11(a))
A cyclic address signal having a period of m pulses is sequentially applied to the O-sock memory 40. Clock memory 40
outputs the stored data sequentially and cyclically, as shown in FIG. 11(b). The AND circuit 41 gates the pixel clock CK1 with the output of the clock memory 40, and outputs a clock CK3 in which pulses are regularly missing as shown in FIG. 11(C).

However, as described above, the selector 35 at the time of enlargement/writing selects the input thereto, that is, the pixel clock CKI, so the output of the address counter 36 is
As shown in Figure (d), this is a periodic address signal. Therefore, image data is written into the image memory device 18 in accordance with the periodic pixel clock CK1. During this writing, the image memory device 18 is in a data input state and does not output data, so the interpolation calculation circuit 21 does not operate.

Next, consider reading. In this case, since the flip-flop 37 instructs "read", the selector 35 selects its S input (clock CK3). Therefore, the address output of the address counter 36 follows the timing of the clock CK3, as shown in FIG. 11(e), and the readout output of the image memory device 18 also follows the timing of the clock CK3. Become something. The image data thus read becomes the data input of the D-FF 51 in the interpolation calculation circuit 21.

On the other hand, since the clock CK3 is given as a latch input to the D-FF51, the input image data is
It is latched for the pulse interval of clock CK3 and transferred to the next stage D-FF52. This next stage D-FF52
also performs the same operation. Therefore, the output V of the D-FF52 is equal to two pulses of the output CK3, and
The output v2 of the D-FF 51 is image data delayed by one pulse. This situation is shown in Figure 11(f).
Shown in (0). In this figure, Do indicates image data,
This image data D is...DD, Dn-
It is assumed that the data are read out in the order of 1-0 1"2'...

The linear interpolation circuits 53a to 53C calculate interpolated values according to Vl and V2, respectively, and output the interpolated values to the selector 54. Further, this selector 54 is also provided with Vl (as six inputs).

By the way, since the selection force S of the selector 54 is obtained from the output of the clock memory 40, the data output from the clock memory 40 is "0" to "3".
”, which input from A to D is selected is determined. The output of the selector 54 based on such selection relationship is shown in FIG. 11(h). The S input of the selector 55 of
This signal is controlled by the value of the data stored as 0.

On the other hand, the output of the D-FF 52, that is, vl, is given to the six inputs of the selector 55, and these two inputs are selected by the S input from the register 38. This signal selects the S input of . Therefore, the selector 55 provides the halftone dot generator 22 with enlarged image data in which interpolated values are added to pixels added due to missing clock pulses.

The data stored in the clock memory 40 during the above-mentioned 250% expansion can also be used during the 40% reduction.

The operation of the memory address generator 19 in the case of reduction is similar to the operation in the case of enlargement, except that the clock pulse is omitted during writing, and the operation is performed at the timing according to the pixel clock CK1 during reading. Therefore, no particular explanation is required. However, in the interpolation calculation circuit 21, a signal for selecting the six inputs is given from the magnification setting section 20 as the S input of the selector 55 included therein. Therefore, the linear interpolation circuit 53a-
The output of c is never given to the halftone dot generator 22, and the read image data is always output as is.

(F) Embodiment In this embodiment, when enlarging, interpolated values are given by the operation described above, so as shown in FIG. 6(d),
You can obtain image data that is a natural enlargement of the original image. Also,
Even if sharpness enhancement processing is applied to this, as shown in FIG. 2(e), no gradation inversion occurs. moreover,
Even when an image like that shown in Fig. 7(a) is enlarged, the image shown in Fig. 7(C)
), a fine step-like step-like boundary line is obtained.

Also, magnification (n/m)xl 00% or (m/n)X
By appropriately selecting n and m at 100%,
The increments of the set magnification can also be made arbitrarily small.

G-1) Arbitrary setting of the enlargement range As described above, in the above embodiment, the data (selection data) is used as composite data (Table 2) that is combined with data expressing the clock dropout rule. However, in the case of the configuration shown in FIG.
It is only possible to calculate the linear interpolation value when one additional pixel is sandwiched between two original pixels, and the linear interpolation value when two additional pixels are sandwiched between two original pixels, Accordingly, it is necessary to configure the data stored in the clock memory 40 so that there are no more than three types of data for selecting interpolated values. In terms of magnification, this corresponds to a range of 100% to 300%.

For this reason, when an enlargement of 300% or more is required, a different configuration is required, which can be done as follows. That is, 100% to (100XN)% (N is an integer)
When you need an expanded range up to [LV + (K L) V2]/K - (
4) However, L=1.2.3. ..., (K-1)K-2,
3, 4, . . . , N linear interpolation circuits are provided in parallel to perform respective calculations. However, among the above, substantially the same operation,
For example: (2■1+4V2)/6...(5)(V
+ 2 V 2 ) / 3...
- For those that perform (6), one of these can be omitted. The data to be stored in the storage memory 40 is the data corresponding to the smallest integer P such that (1+Q)≦2P (1), where Q is the number of linear interpolation circuits prepared. A word of length P bits is used. In this way, the instruction value of this word makes it possible to specify both the clock missing information and the interpolation value selection information. Table 3 shows an example of a configuration based on this principle. In this way, the magnification can be set within any range.

(G-2) Data Setting In the above embodiment, the data regarding clock loss and the data for selecting interpolation values are formed as composite data, but the present invention is not limited to this aspect. Therefore, it is also possible to prepare the data as separate data, read them out in relation to each other, and perform the respective processing.

Table 3 (Continued) Table 3 (Continued) (Continued) Table 3 (Continued) (Left below) G-3) Interpolation calculation circuit In addition, in the above embodiment, linear interpolation is performed as interpolation calculation. , interpolation other than linear interpolation may be performed.

Further, the method of capturing data of original pixels, which is a prerequisite for interpolation, is not limited to the method using the above-mentioned D-FF.

Further, in the above embodiment, a color scanner for plate making is taken as an example, and the output is also provided in halftone dots, but the present invention is not limited to this, and can be applied to any arbitrary image enlarging process. Applicable to devices (plate-making scanners, facsimiles, ?I! photo machines, etc.). It is not necessary to input and output images optically, and a device that inputs and outputs images electrically or magnetically may be used.

Note that in this device, since the number of significant pixels is substantially increased by interpolation, it can also be used for transmitting image data between an input device and an output device that have different sampling pitches.

(Effects of the Invention) As explained above, according to the present invention, it is possible to obtain a uniform image with a wide magnification range using a relatively simple circuit, and the spatial It is possible to obtain an image processing device that can produce natural images by smoothing gradation changes.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of an embodiment of the present invention, FIG. 2 is a detailed block diagram of a technical example related to the present invention, and FIG. 3 is a diagram showing the principle of data creation of the clock memory 33 in the related technical example. , FIG. 4 is a flowchart showing the data creation process of the clock memory 33 in the related technology example, FIG. 5 is a timing diagram showing the operation of the related technology example, and FIGS. 6 and 7 show image data in the enlargement process. 8 is a detailed configuration diagram of an embodiment of the present invention, FIG. 9 is a diagram showing the principle of interpolation in the embodiment, FIG. 10 is a flowchart showing the data creation process of the clock memory 40 in the embodiment, and FIG. FIG. 11 is a timing chart showing the operation of the embodiment shown in FIG. 18... Image memory device, 19.198... Memory address generation section, 20...
Magnification setting section, 31.36...address counter, 33.40...memory for zero check,

Claims (3)

[Claims] (1) An image processing device that inputs image data and stores it in an image data storage means, and then outputs the image data at a specified magnification, the image processing device periodically outputting the image data at a specified magnification based on a predetermined rule corresponding to the magnification. The first
a second clock generating means for generating a second clock in which clocks are regularly omitted from an array of clocks; and when the magnification is enlargement, the first clock is stored in the image data storage means. reading means for reading out the image data stored based on the second clock based on the second clock; and at least one interpolated data by interpolating between data of original pixels that are the read image data. interpolation that selectively applies the interpolation data to additional pixels added due to the omission of the clock based on selection data set in advance in accordance with the predetermined rule; An image processing device comprising a data adding means. (2) The second clock generation means includes a composite data storage means for storing composite data that collectively represents data expressing a predetermined rule and selection data, and the second clock generation means and interpolation data provision. The means is defined in claim 1, wherein the means performs respective processing based on the composite data read from the composite data storage means.
The image processing device described in Section 1. (3) The interpolation data generation means includes a plurality of linear interpolation data calculation means each calculating a plurality of types of linear interpolation data according to the positional relationship between the additional pixel and the original pixel in the image data, and the selected data is , according to the positional relationship between the additional pixel and the original pixel, the interpolation data applying means selects one of the plurality of types of interpolation data and applies it to the additional pixel according to the selection data. An image processing apparatus according to claim 1 or 2, comprising means.