JPS61222125A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61222125A JPS61222125A JP6292485A JP6292485A JPS61222125A JP S61222125 A JPS61222125 A JP S61222125A JP 6292485 A JP6292485 A JP 6292485A JP 6292485 A JP6292485 A JP 6292485A JP S61222125 A JPS61222125 A JP S61222125A
- Authority
- JP
- Japan
- Prior art keywords
- polysilicon layer
- impurity
- diffusion
- polysilicon
- added
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 65
- 229920005591 polysilicon Polymers 0.000 claims abstract description 65
- 239000012535 impurity Substances 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 abstract description 41
- 238000010438 heat treatment Methods 0.000 abstract description 7
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 52
- 238000010586 diagram Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野〕
この発明は、ポリシリコン層で電極を形成する半導体装
置の製造方法に係り、特に、不純物拡散に伴う主拡散層
の不純物プロファイルに対する影響の低減に関する。[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor device in which an electrode is formed using a polysilicon layer, and particularly relates to a method for manufacturing a semiconductor device in which an electrode is formed using a polysilicon layer, and in particular, reducing the influence of impurity diffusion on the impurity profile of a main diffusion layer. Regarding.
従来、ダイオードなど、ポリシリコン層を電極材料に用
いる半導体装置が実用化されているが、このようなポリ
シリコン層を電極材料に用いる半導体装置では、その抵
抗値を低減するため、ポリシリコン層を堆積後、ポリシ
リコン層に不純物を高濃度に添加する必要があり、その
添加には簡単な方法として熱拡散がよく用いられている
。″第４図のＡに示すように、たとえば、Ｎ型の半導体
ウェハ２に主拡散層であるＰ型の拡散領域４が形成され
ている。このような半導体装置において、半導体ウェハ
２および拡散領域４の表面を覆う酸化膜６の拡散領域４
に対応する位置に選択的に開口８が形成され、この開口
８から露出する拡散領域４の表面には開口８を塞ぐ形で
ポリシリコン層１０が堆積される。Conventionally, semiconductor devices such as diodes that use a polysilicon layer as an electrode material have been put into practical use. After deposition, it is necessary to add impurities to the polysilicon layer at a high concentration, and thermal diffusion is often used as a simple method for this addition. "As shown in FIG. 4A, for example, a P-type diffusion region 4, which is a main diffusion layer, is formed in an N-type semiconductor wafer 2. In such a semiconductor device, the semiconductor wafer 2 and the diffusion region Diffusion region 4 of oxide film 6 covering the surface of 4
An opening 8 is selectively formed at a position corresponding to , and a polysilicon layer 10 is deposited on the surface of the diffusion region 4 exposed from the opening 8 so as to close the opening 8 .
そして、このポリシリコン層１０には、次の工程で熱拡
散によって不純物を添加する。この場合、ポリシリコン
層ｌＯを電極としての適当な低抵抗値に下げるためには
、ポリシリコン層１０の奥底 ゛まで十分に不純物
を浸透させる必要がある。Then, impurities are added to this polysilicon layer 10 by thermal diffusion in the next step. In this case, in order to lower the resistance of the polysilicon layer 10 to an appropriate low value for use as an electrode, it is necessary to penetrate the impurity sufficiently deep into the polysilicon layer 10.
このように主拡散層の表面にポリシリコン層１０を設置
し、このポリシリコン層１０に熱拡散によって不純物を
その表面からその奥底まで浸透させるには、高温下で長
時間の拡散処理を必要としている。In order to install the polysilicon layer 10 on the surface of the main diffusion layer in this way and to infiltrate the impurity from the surface to the depths of the polysilicon layer 10 by thermal diffusion, a long-time diffusion process is required at high temperature. There is.
そして、このような高温下、長時間の熱処理を行った場
合、第４図のＢに示すように、拡散領域４が破線４′に
示すように拡大するなど、主拡散層の不純物プロファイ
ルにも影響を与え、半導体装置の特性に影響を与えるお
それがある。When heat treatment is performed at such a high temperature for a long time, the impurity profile of the main diffusion layer changes, such as the diffusion region 4 expanding as shown by the broken line 4', as shown in FIG. 4B. This may affect the characteristics of the semiconductor device.
第５図はｉ、ｏｏｏ℃下で１５分間の拡散を施した場合
の不純物濃度分布を示し、高温下、長時間の熱拡散にも
かかわらず、その拡散の深さは０．６μｍ程度である。Figure 5 shows the impurity concentration distribution when diffusion is performed for 15 minutes at i, ooo degrees Celsius, and the depth of the diffusion is about 0.6 μm despite the long time thermal diffusion at high temperatures. .
また、半導体装置の特性に対する影響を考えにいれると
、十分な熱処理を行うことが不可能となり、ポリシリコ
ン層による電極の抵抗値の低減が不十分になる欠点があ
った。Moreover, when considering the influence on the characteristics of the semiconductor device, it becomes impossible to perform sufficient heat treatment, and there is a drawback that the resistance value of the electrode is insufficiently reduced by the polysilicon layer.
そこで、この発明は、ポリシリコン層による電極に対し
て十分に不純物を拡散させてその１肢抗値を低減すると
ともに、主拡散領域の不純物プロファイルに対する影響
を除いた半導体装置の製造方法を提供しようとするもの
である。Therefore, the present invention aims to provide a method for manufacturing a semiconductor device in which the impurity is sufficiently diffused into an electrode made of a polysilicon layer to reduce the resistivity of one limb thereof, and the influence on the impurity profile of the main diffusion region is eliminated. That is.
すなわち、この発明は、ポリシリコン層で電極を形成し
、その電極に不純物を添加する半導体装置の製造方法に
おいて、ポリシリコン層を薄く堆積した後、そのポリシ
リコン層に対して不純物を添加し、そのポリシリコン層
に再びポリシリコン層を堆積させた後、不純物を添加す
ることを特徴とする。That is, the present invention provides a method for manufacturing a semiconductor device in which an electrode is formed from a polysilicon layer and an impurity is added to the electrode, in which a polysilicon layer is deposited thinly, and then an impurity is added to the polysilicon layer. The method is characterized in that after a polysilicon layer is deposited again on the polysilicon layer, impurities are added thereto.
したがって、この発明は、ポリシリコン層の堆積と不純
物の熱拡散とを交互に繰り返すので、熱処理時間の短縮
化とともに、ポリシリコン層の奥底まで不純物拡散を行
うことができる。Therefore, in the present invention, since the deposition of the polysilicon layer and the thermal diffusion of impurities are repeated alternately, the heat treatment time can be shortened and the impurities can be diffused deep into the polysilicon layer.
以下、この発明あ実施例を図面を参照して詳細に説明す
る。Hereinafter, embodiments of this invention will be described in detail with reference to the drawings.
第１図はこの発明の半導体装置の製造方法の一実施例で
あるダイオードの製造方法を示している。FIG. 1 shows a method for manufacturing a diode, which is an embodiment of the method for manufacturing a semiconductor device of the present invention.
第１図のＡに示すように、たとえば、Ｎ型の半導体ウェ
ハ１２の表面層には、半導体ウェハ１２とは反対導電型
のＰ型の拡散領域１４が形成されている。半導体ウェハ
１２および拡散領域１４の表面には、酸化膜１６が形成
されているとともに、その酸化膜１６の拡散領域１４を
露出する位置には開口１８が形成され、この開口１８か
ら露出する拡散領域１４には、その周辺部の酸化膜１６
に跨って従来のポリシリコン層より薄い第１のポリシリ
コン層２０が形成される。As shown in FIG. 1A, for example, a P-type diffusion region 14 having a conductivity type opposite to that of the semiconductor wafer 12 is formed in the surface layer of an N-type semiconductor wafer 12. An oxide film 16 is formed on the surfaces of the semiconductor wafer 12 and the diffusion region 14, and an opening 18 is formed in the oxide film 16 at a position exposing the diffusion region 14. 14 has an oxide film 16 around it.
A first polysilicon layer 20, which is thinner than a conventional polysilicon layer, is formed over the polysilicon layer.
次に、第１図のＢに示すように、第１のポリシリコン層
２０にその抵抗値を低減するための不純物を熱拡散によ
って添加する。Next, as shown in FIG. 1B, impurities are added to the first polysilicon layer 20 by thermal diffusion to reduce its resistance value.
次に、不純物が添加されたポリシリコン層２０の表面に
、第１図のＣに示すように、第２のポリシリコン層２２
を堆積した後、第１図のＤに示すように、そのポリシリ
コン層２２に対し、その抵抗値を低減するために、第１
のポリシリコン層２０と同様に不純物を熱拡散によって
添加する。Next, a second polysilicon layer 22 is applied to the surface of the polysilicon layer 20 doped with impurities, as shown in
After depositing the polysilicon layer 22, as shown in FIG.
Similarly to the polysilicon layer 20, impurities are added by thermal diffusion.
すなわち、拡散領域１４の表面に、第１および第２のポ
リシリコン層２０．２２で電極を形成し、それぞれのポ
リシリコン層２０，２２に個別に不純物がドープされる
。That is, electrodes are formed on the surface of the diffusion region 14 using the first and second polysilicon layers 20 and 22, and impurities are doped into each of the polysilicon layers 20 and 22 individually.
次に、第１図のＥに示すように、第２のポリシリコン層
２２の表面に外部電極に電気的に接続するための銀電極
２４をメッキによって形成し、ダイオード用の半導体素
子が形成される。Next, as shown in FIG. 1E, a silver electrode 24 for electrical connection to an external electrode is formed on the surface of the second polysilicon layer 22 by plating, and a semiconductor element for a diode is formed. Ru.
そして、この半導体素子は、ガラス管の内部に設置され
、ガラス管の両端から挿入した端子と半導体ウェハ１２
または銀電極２４とを加圧しつつ電気的に接続してダイ
オードを得る。This semiconductor element is installed inside a glass tube, and terminals inserted from both ends of the glass tube and a semiconductor wafer 12 are placed inside the glass tube.
Alternatively, a diode is obtained by electrically connecting with the silver electrode 24 while applying pressure.
このような製造方法において、第１のポリシリコン層２
０に対して不純物を１ 、０００℃下で１５分間の熱拡
散を行った場合、第２図に示すように、その拡散の深、
さは０．４μｍまで到達し、しかもその不純物濃度をほ
ぼ一様にすることができる。In such a manufacturing method, the first polysilicon layer 2
When thermal diffusion is performed for 15 minutes at 1,000°C with an impurity of 1% compared to 0%, as shown in Figure 2, the depth of the diffusion,
The thickness can reach up to 0.4 μm, and the impurity concentration can be made almost uniform.
そして、２回目の不純物拡散では、第２のポリシリコン
層２２に対して同様に不純物の熱拡散を行うことができ
、第１および第２のポリシリコン層２０．２２では、第
３図に示すように、拡散の深さを０．８μｍまで到達さ
せ、しかもその不純物濃度を一様にすることができる。Then, in the second impurity diffusion, the impurity can be thermally diffused into the second polysilicon layer 22 in the same way, and the first and second polysilicon layers 20 and 22 are heated as shown in FIG. Thus, the depth of diffusion can reach up to 0.8 μm, and the impurity concentration can be made uniform.
したがって、このような２段階のポリシリコン層２０．
２２の堆積、不純物の熱拡散を施すことにより、第３図
および第５図の特性の比較から明らかなように、ポリシ
リコン層２０．２２の奥底まで不純物を均一に浸透させ
ることができ、その抵抗値を低減させることができる。Therefore, such a two-stage polysilicon layer 20.
By depositing the polysilicon layer 20 and thermally diffusing the impurity, it is possible to uniformly infiltrate the impurity deep into the polysilicon layer 20 and 22, as is clear from the comparison of the characteristics in FIGS. 3 and 5. The resistance value can be reduced.
実施例では、比較のために、従来例と実施例の拡散温度
およびその拡散時間を同一に設定したが、このような２
段階ないし３段階以上のポリシリコン層の堆積および不
純物の熱拡散を繰り返すことにより、高温下、長時間の
熱処理を軽減でき、主拡散層に対する不純物プロファイ
ルに対する影響を低減させることができる。In the example, for comparison, the diffusion temperature and the diffusion time were set to be the same for the conventional example and the example.
By repeating the deposition of the polysilicon layer in three or more stages and the thermal diffusion of impurities, it is possible to reduce the need for long-term heat treatment at high temperatures, and to reduce the influence on the impurity profile of the main diffusion layer.
また、実施例では、ダイオードの製造を例に採って説明
したが、この発明はダイオード以外のポリシリコン層を
電極に用いる半導体装置に適用できる。Further, although the embodiments have been described using the manufacturing of diodes as an example, the present invention can be applied to semiconductor devices other than diodes that use polysilicon layers as electrodes.
以上説明したように、この発明によれば、ポリシリコン
層の形成およびポリシリコン層に対する不純物の添加処
理を複数回に分けて行うので、高温下の熱処理時間を短
縮できるとともに、ポリシリコン層の奥底まで不純物を
浸透させ、ポリシリコン層の抵抗値を電極として適当な
値に低減でき、主拡散層の不純物プロファイルへの悪影
響を防止できる。As described above, according to the present invention, the formation of the polysilicon layer and the addition of impurities to the polysilicon layer are performed in multiple steps, so it is possible to shorten the heat treatment time at high temperatures, and to deeply penetrate the polysilicon layer. It is possible to reduce the resistance value of the polysilicon layer to a value suitable for use as an electrode by penetrating the impurity up to the point where it can be used as an electrode, and to prevent an adverse effect on the impurity profile of the main diffusion layer.
第１図はこの発明の半導体装置の製造方法を示す工程説
明図、第２図および第３図は不純物濃度と拡散の深さを
示す説明図、第４図は従来の半導体装置の製造方法を示
す説明図、第５図は不純物濃度と拡散の深さを示す説明
図である。
１２・・・半導体ウェハ、２０・・・第１のポリシリコ
ン層、２２・・・第２のポリシリコン層。
特許出願人 口 −ム 株 式 会 社代理人 弁理士
畝 本 正 −図
１２・・・半導体ウェハ
２０・・・Ｍｌのポリシリコン層
２２・・・第２のポリシリコン層
第２図
第３図
拡散の深さ （μｍ）
第４図
第５図
拡散のＨさ （μｍ）FIG. 1 is a process explanatory diagram showing the method of manufacturing a semiconductor device of the present invention, FIGS. 2 and 3 are explanatory diagrams showing impurity concentration and diffusion depth, and FIG. 4 is a diagram showing the conventional method of manufacturing a semiconductor device. FIG. 5 is an explanatory diagram showing impurity concentration and diffusion depth. 12... Semiconductor wafer, 20... First polysilicon layer, 22... Second polysilicon layer. Patent applicant population - M Co., Ltd. Company agent Patent attorney Tadashi Unemoto - Figure 12...Semiconductor wafer 20...Ml polysilicon layer 22...Second polysilicon layer Fig. 2 Fig. 3 Diffusion depth (μm) Figure 4 Figure 5 Diffusion height (μm)
Claims (1)
加する半導体装置の製造方法において、ポリシリコン層
を薄く堆積した後、そのポリシリコン層に対して不純物
を添加し、そのポリシリコン層に再びポリシリコン層を
堆積させた後、不純物を添加することを特徴とする半導
体装置の製造方法。In a method of manufacturing a semiconductor device in which an electrode is formed from a polysilicon layer and an impurity is added to the electrode, a thin polysilicon layer is deposited, an impurity is added to the polysilicon layer, and the polysilicon layer is re-doped. A method for manufacturing a semiconductor device, comprising adding impurities after depositing a polysilicon layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6292485A JPS61222125A (en) | 1985-03-27 | 1985-03-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6292485A JPS61222125A (en) | 1985-03-27 | 1985-03-27 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61222125A true JPS61222125A (en) | 1986-10-02 |
Family
ID=13214303
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6292485A Pending JPS61222125A (en) | 1985-03-27 | 1985-03-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61222125A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63204763A (en) * | 1987-02-20 | 1988-08-24 | Nec Corp | Manufacturing method of semiconductor device |
| US4829024A (en) * | 1988-09-02 | 1989-05-09 | Motorola, Inc. | Method of forming layered polysilicon filled contact by doping sensitive endpoint etching |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5368165A (en) * | 1976-11-30 | 1978-06-17 | Nec Corp | Production of semiconductor device |
| JPS58135669A (en) * | 1982-02-08 | 1983-08-12 | Toshiba Corp | Manufacture of semiconductor device |
| JPS6180862A (en) * | 1984-09-27 | 1986-04-24 | Toshiba Corp | Manufacturing method of semiconductor device |
-
1985
- 1985-03-27 JP JP6292485A patent/JPS61222125A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5368165A (en) * | 1976-11-30 | 1978-06-17 | Nec Corp | Production of semiconductor device |
| JPS58135669A (en) * | 1982-02-08 | 1983-08-12 | Toshiba Corp | Manufacture of semiconductor device |
| JPS6180862A (en) * | 1984-09-27 | 1986-04-24 | Toshiba Corp | Manufacturing method of semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63204763A (en) * | 1987-02-20 | 1988-08-24 | Nec Corp | Manufacturing method of semiconductor device |
| US4829024A (en) * | 1988-09-02 | 1989-05-09 | Motorola, Inc. | Method of forming layered polysilicon filled contact by doping sensitive endpoint etching |
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