JPH0518470B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improved method for manufacturing a high reverse voltage mesa type semiconductor device having a channel stopper.

[Technical Background of the Invention] In mesa-type semiconductor devices, the surface of the device is coated with a protective film in order to stabilize the characteristics of the device and improve reliability. One of the methods is to coat the surface with a protective film. There are surface protection methods. Thermal oxide films provide a stable surface and are suitable for mass production, but
Positive mobile ions exist in the oxide film, which adversely affects reliability, especially high temperature reverse bias characteristics.

Conventionally, for example, in a mesa diode with an N ⁺ -N ^- -P structure, as shown in Fig. 2, the channel stopper 6 is a P ⁺ having an acceptor impurity concentration of 10 ¹⁹ cm ^-3 or more near the bottom of the mesa groove. Set up an area,
A structure is adopted to prevent the formation of an inversion layer on the surface of P region 2 due to positive charges in oxide film 9 when high temperature reverse bias is applied. Note that 10 is an electrode, and 5 is a P ⁺ region for taking out the electrode.

[Problems in the Background Art] Conventionally, as a method for providing the channel stopper P ⁺ region 6, for example, the method shown in the process diagrams of FIGS. 3 a to d and the method shown in the process diagrams of FIGS. 4 a to d are known. There is.

The method shown in FIG. 3 is a method in which a mesa groove is provided and then a channel stopper P ⁺ region is diffused at the bottom of the groove. That is, first, acceptor impurities are diffused from the entire lower surface ^of the N ^- type silicon substrate 11 ^shown in FIG. and provide a P region 12 and an N ⁺ region 13 respectively (third
Figure b). Next, from the N ⁺ region 13 side surface, P region 1
Dig holes reaching 2, N ⁺ area 13, N ^- area 14
and a mesa groove 15 spanning the P region 12 (FIG. 3c). Thereafter, an acceptor impurity of 10 ¹⁹ cm ^-3 or more is introduced into the bottom of the mesa groove 15 to form the P ⁺ region 16 of the channel stopper (FIG. 3d).

The method shown in FIG. 4 is a method in which a deep P ⁺ region is diffused and then a mesa groove is formed. That is,
First, take the N ^- type silicon substrate 21 shown in FIG. 4a,
The acceptor impurity is diffused from the entire surface on the bottom surface of the figure and from the position where the mesa groove is provided on the top surface of the figure, so that the surface concentration is 10 ²⁰ cm ^-3 and 10 ²¹ cm ^-3 , respectively.
10 ¹⁹ cm ^-3 at the P region 22 and the bottom of the mesa groove
A P ⁺ region 27 having the above concentration is formed (FIG. 4b). Next, a donor impurity is diffused from the upper surface of the figure to form an N ⁺ region 23 (FIG. 4c). Thereafter, a mesa groove 25 is dug, leaving the bottom of the P ⁺ region 27 as a channel stopper 26, resulting in the structure shown in FIG. 4d, which is the same as that shown in FIG. 3d.

Then, an oxide film and an electrode are formed on the substrate on which the regions shown in FIG. 3 d and FIG. 4 d are formed, and the structure shown in FIG. diode is obtained.

However, in the conventional method shown in FIG. 3, the P ⁺ region is diffused at the bottom of the mesa groove after it is formed, so it is difficult to accurately control the diffusion position.On the other hand, in the conventional method shown in FIG. , it is necessary to diffuse deeper than the depth of the mesa groove, so the diffusion time becomes longer and the channel stopper 26
The disadvantage is that the P ⁺ concentration is significantly lower than the diffusion surface concentration, and the P ⁺ concentration is also difficult to control.

[Object of the Invention] An object of the present invention is to place the channel stopper at the bottom of the mesa groove in a more accurate position, at a higher concentration, and to control the concentration, thereby achieving high reverse withstand voltage, etc. An object of the present invention is to provide a method for manufacturing a mesa-type semiconductor device having characteristics. Another object of the present invention is to provide a method for manufacturing a mesa-type semiconductor device that contributes to shortening the overall process time by shortening the diffusion time of the channel stopper region.

[Summary of the Invention] The present invention forms a channel stopper region by using a technique of bonding two semiconductor substrates by direct thermocompression bonding without the intervention of a brazing material such as a metal or an organic material or an adhesive. It is something to do. That is, a channel stopper region is provided on the main surface of one semiconductor substrate at a position that will become the bottom of the mesa groove, and the other semiconductor substrate is adhered to this, forming a mesa such that the channel stopper appears at the bottom of the groove. A method of forming a groove in the other semiconductor substrate. The advantage of this method is that the channel stopper can be formed at a precise location at the bottom of the mesa groove, in a controlled high concentration, and in a short time.

[Embodiments of the Invention] The present invention will be specifically explained below with reference to the process diagram of a mesa diode shown in FIG. Figure 1 a1-a2
are steps related to the first semiconductor substrate, FIG. 1 b1 to b
2 is a step of providing a channel stopper region etc. on the second semiconductor substrate, and FIGS. 1c to 1d are steps of bonding the first and second semiconductor substrates to form a mesa groove.

31 in Figure 1 a1 has an impurity concentration of 10 ¹⁴
cm ^-3 N ^- type silicon substrate. Next, as shown in FIG. 1 a2, the surface concentration is 10 ²⁰ cm ^-3 from the entire upper surface of this N ^- type silicon substrate 31 in the figure.
The donor impurity is diffused so as to form an N ⁺ type high concentration layer 33.

On the other hand, 32 in FIG. 1b1 is another P-type silicon substrate with an impurity concentration of 10 ¹⁸ cm ^-3 .
Next, as shown in FIG. 1 b2, this silicon substrate 3
The acceptor impurity was selectively added to the bottom of the mesa groove on the upper surface of Figure 2 to increase the surface concentration.
10 ²⁰ cm ^-3 to form a channel stopper P ⁺ region 36, and at the same time, acceptor impurities are diffused from the entire lower surface of the silicon substrate 32 to form a contact P ⁺ region 38. will be established.

After that, as shown in Figure 1 c, Figure 1 a2
and the substrate in FIG. 1b2 are bonded together so that the N ^- area 34 of the substrate a2 in FIG. 1 and the channel stopper P ⁺ area 36 side of the substrate b2 in FIG. . For this bonding, after forming mirror surfaces on both substrates, the mirror surfaces are cleaned, and the silicon substrates are directly pressed together in a clean atmosphere without intervening a metal or organic brazing material or adhesive. with 400℃ or more preferably 1100℃
heat treatment for several hours to strengthen the bond. This adhesion forms a diode PN junction between N ^- region 34 and P region 32.

Finally, as shown in FIG ^. 1d, a mesa groove 35 is dug from the N ⁺ side surface of the bonded substrate so that the P ⁺ region 36 is located at the bottom of the mesa groove 35. A structure in which the channel stopper is formed is formed.

A mesa diode with a channel stopper having the structure shown in FIG. 2 can be obtained by forming an oxide film and an electrode on the substrate shown in FIG. In FIG. 2, 9 is the oxide film and 10 is the electrode.

[Effects of the Invention] According to the manufacturing method of the present invention, since the channel stopper region is formed by selective diffusion on the flat substrate of the second semiconductor substrate, the channel stopper region is formed at the bottom of the groove after forming the mesa groove. Compared to the conventional method (the method shown in FIG. 3), the channel stopper region can be provided at a more accurate position.

Furthermore, according to the manufacturing method of the present invention, since the diffusion for the channel stopper region only needs to be performed shallowly on the second semiconductor substrate, the depth of the mesa groove is adjusted to the depth of the channel stopper region before forming the mesa groove. Compared to the conventional method (method shown in Figure 4), which required deep diffusion with added depth, the diffusion time can be significantly shortened, and the high concentration region required as a channel stopper can be controlled in an extremely controlled manner. can be provided.

If the channel stopper region can be formed in a controlled manner at a high concentration at the precise position of the trench bottom, a mesa-type semiconductor device with high reverse breakdown voltage can be realized, and the diffusion time can be shortened. It only takes time,
The entire process time can be significantly shortened.

[Brief explanation of the drawing]

1 is a process diagram illustrating the main steps of a method for manufacturing a mesa semiconductor device according to an embodiment of the present invention using a cross section of a semiconductor substrate, FIG. 2 is a sectional view of a mesa semiconductor device to which the present invention relates, and FIGS. FIG. 4 is a process diagram illustrating the main steps of the conventional manufacturing method using a cross section of a semiconductor substrate. 31... First semiconductor substrate of one conductivity type, 32...
a second semiconductor substrate of opposite conductivity type; 33...a high concentration layer of one conductivity type; 34...a low concentration layer of the first semiconductor substrate;
35...Mesa groove, 36...High concentration layer of opposite conductivity type (channel stopper), 37...Adhesive surface, 9...
Oxide film.

Claims (1)

[Claims] 1. A step of providing a high concentration layer of the same conductivity type on one main surface of a first semiconductor substrate of one conductivity type, and a step of providing a high concentration layer of the same conductivity type on one main surface of a second semiconductor substrate of an opposite conductivity type at a position that will be the bottom of the mesa groove, a step of selectively providing a high concentration layer of opposite conductivity type; and the other exposed main surface of the low concentration layer of the first semiconductor substrate and one main surface of the second semiconductor substrate on which the high concentration layer is selectively provided. A mesa-type semiconductor device comprising the steps of: adhering by thermocompression bonding; and providing a mesa groove in the adhered substrate such that the selectively provided high concentration layer of the second semiconductor substrate is located at the bottom of the mesa groove. manufacturing method.