JPS61222091A - Dynamic memory refresh method - Google Patents

Abstract

PURPOSE:To make it possible to refresh memory without stopping a microprocessor by utilizing an idle time until next access. CONSTITUTION:Specified number is preset at every time when a microprocessor 2 outputs a timing signal ALE for starting execution of bus cycle and accesses a dynamic memory to a refreshing circuit 7 that counts basic clocks MCLK and outputs a refreshing signal at every time specified number is reached. When counted value of clocks MCLK reaches specified number, a refreshing signal is outputted through the circuit 7, and a memory 6 is refreshed by utilizing spare time of access period until next access, and it is not necessary to stop the processor 2 for refreshing. Accordingly, refreshing is made without stopping the microprocessor, and the increase of loss time of the memory system is prevented, and processing speed can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary of the Invention] According to the present invention, a dynamic memory is refreshed using idle time of a bus cycle. There is no need to stop the processing, and the processing speed of the memory circuit can be increased.

[Industrial application field]

The present invention relates to dynamic memory refresh.

[Technology background]

BACKGROUND ART In current office automation equipment and the like, large-capacity memories are used to improve system performance and functionality.

When selecting this memory, there are two types of memory that can be considered: static memory and dynamic memory. However, dynamic memory has a higher degree of integration than static memory (higher density, Things have become more frequent.

By the way, in dynamic memory, the stored information corresponds to the presence or absence of charge on the capacitor, so in order to retain the stored information, a so-called refresh operation that injects charge must be performed a predetermined number of times within a predetermined time. Specifically, this refresh is performed by detecting the stored information (usually voltage level) held by each memory in the memory cell matrix and writing it again. In general, in a dynamic memory, stored information disappears after approximately 2 ms has passed after the storage information is given, so it must be refreshed a predetermined number of times (for example, 128 times for a 64-bit type) within this Z m s. It is necessary to do so.

[Conventional technology]

A dynamic memory refresh method has conventionally been carried out, for example, as shown in FIGS. 5 and 6. The conventional refresh method will be explained using a 64-bit chip as an example.

That is, for a 64-bit chip, Z m
Since it is necessary to refresh all bits at least 128 times within s, if the time required for one refresh is, for example, 400 ns, the time required for one refresh cycle is 400 ns x 128 = 51
．． It will be 2ts.

Conventionally, the time required for this refresh is 51.2 ps, as shown in Figure 4, and 12
Two methods have been adopted: one is to perform refresh eight times, and the other is to perform refresh by dispersing the refresh time of 400 ns into 128 times within 2 ms, as shown in FIG.

[Problem that the invention seeks to solve]

However, the conventional refresh method has a problem in that the memory cannot be used and the processing speed of the memory circuit becomes slow.

For example, a 64-bit dynamic memory must be refreshed for at least 128 cycles within Zms, so if the refresh cycle time is, for example, 51°2 ILs, the loss time TJL due to refreshing is T1 = (51, 2X10-6/
2X10-3) XIGO! = 2.58%, and the refresh cycle increases as the capacity of the memory chip increases. Therefore, with the conventional refresh method, the loss time of the memory system increases as the capacity of the memory chip increases. This increases the processing speed and reduces the processing speed.

[Means for solving problems]

The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to provide a dynamic memory refresh method that can perform refresh without stopping the microprocessor. In a memory circuit using a dynamic memory, the means forms the timing of a memory access based on a timing signal from a microprocessor that starts execution of a bus cycle consisting of a predetermined number of basic clocks, while This is done by a dynamic memory refresh method that refreshes the dynamic memory using the free time in the memory access period before the memory access in the cycle.

〔Example〕

Hereinafter, the present invention will be described in detail based on the accompanying drawings.

1 to 4 show a dynamic memory refresh method according to an embodiment of the present invention.

Figure 3 shows a memory circuit using dynamic memory, where 1 is a basic clock (1) using crystal oscillation, etc.
MCLK), and 2 a microprocessor that issues a timing signal (ALE signal) for starting execution of a bus cycle.

3 is a latch circuit that latches the basic clock and the ALE signal, 4 is a decoder, 5 is a gate, and 6 is a dynamic memory. 7 counts the basic clock from the clock circuit l and also counts the basic clock from the microprocessor.
After inputting the LE signal, a refresh signal (RF
This is a refresh circuit that outputs S H). Furthermore, 8,9
is an inverting circuit that inverts the input signal.

By the way, the dynamic memory 6 in this embodiment is, for example, Intel's 8086 CPU,
5 MHZ basics ri a +7 ri o 4 ri o +7
Tl, T2. T3. It is assumed that T4 is used for one bus cycle for memory access. Therefore, the time for one basic clock is 200 ns, and the time for one bus cycle is 800 ns.

On the other hand, the refresh circuit 7 has <o, as shown in FIG.
4 bits 16 from o, o, o> to (1, 1, 1, 1)
Count the basic clock in decimal, (1, l, 1,
It outputs a refresh signal when counting up to 1). Also, upon receiving the ALE signal from the microprocessor 2, the refresh circuit 7 changes the count to <1.
．． It shall be preset to 1,0°0).

Next, a refresh method in such a memory circuit will be explained based on FIG.

First, there is a case where the microprocessor 2 issues an ALE signal to start executing a bus cycle.

In this case, the first clock TI of the bus cycle occurs when the ALE signal is output, and the memory access timing signal (T2cy) is output to the dynamic 2-clock memory 6 two stages later than the ALEi signal. This timing signal (T2cy) is a conflict that continues from the rising edge of the second clock T2 to the falling edge of the third clock T3, as shown in FIG. Therefore, since there is an idle time in the bus cycle between the final fourth clock T4 and the first clock TI of the next bus cycle, a refresh signal can be issued during this period without stopping the microprocessor 2.

The timing is as follows. That is, when the ALE signal is output from the microprocessor 2.

The refresh circuit 7 sets the count to <t, i, o.

Preset to O>. And (i, t, o.

0> to <t, t, i, t> and outputs a refresh signal at (1, l, 1, 1). (1,1,0,0)
is the first basic clock, so (1゜1, 1
, 1) corresponds to the fourth basic clock, and the refresh signal is output at the time of this fourth basic clock, which is the idle time of the bus cycle. Then, when the refresh circuit 7 receives the next ALE signal, it starts counting (t, i.

1.1> to (1, 1, 0, 0>).Then, a refresh signal is issued again at the fourth basic clock.The time required for the bus cycle is 8
00 ns, it is quite possible to secure 128 refresh signals for the l bus in 2 ms.

On the other hand, the counter of the refresh circuit 7 is (1°1,
l, 1) and outputs a refresh signal, if the next ALE signal does not come in, the counter returns to (0, 0, 0, 0) at the next basic clock. If no ALE signal is received during that time, as shown in Figure 4 (
Counts from 0, O, O, O) to the 16th basic clock, and when it reaches (1, 1, 1, 1), the second
As shown in the figure, it outputs a refresh signal. Also, when counting starts from (0, 0, 0, 0) and the ALE signal is input during that time, the counter will start at (1, 1,
0, 0), and becomes (1, l, 1, 1) at the 4th basic tarock to issue a refresh signal. still.

When a refresh signal is issued every 16 counts, the time interval between one refresh signal and the next refresh signal is 3 + 2 JLs, so in this case, 's r
& ? m cs M咄 1 9 Q
rFn n) II -y c, -, S7
This can be secured in 1trjL+↓↓ minutes.

〔Effect of the invention〕

As explained above, the refresh method of the present invention refreshes the memory during the idle time of the bus cycle even when the microprocessor is operating and the bus cycle is being executed. Therefore, according to the present invention, even if the memory chip has a large capacity,
Since there is no loss time for refreshing, processing speed can be significantly increased compared to conventional refresh methods.

[Brief explanation of drawings]

FIG. 1 is a time chart showing a refresh method according to an embodiment of the present invention during execution of a bus cycle, and FIG. 2 is a time chart showing a refresh method according to an embodiment of the present invention when no bus cycle is being executed. FIG. 3 is a block diagram showing a memory circuit according to an embodiment of the present invention;
FIG. 4 is a chart for explaining the timing of refresh signal generation by the refresh circuit according to the embodiment of the present invention, and FIGS. 5 and 6 are time charts showing a conventional dynamic memory refresh method. l...Clock circuit 2...Microprocessor 3...Latch circuit 4...Decoder 5...Gate 6...Dynamic memory 7...Refresh circuit MCLK...Basic clock signal 111 Figure 00ns TOH J2rIJ

Claims (1)

[Claims] 1) In a memory circuit using a dynamic memory, the timing of memory access is formed based on a timing signal from a microprocessor that starts execution of a bus cycle consisting of a predetermined number of basic clocks. , a dynamic memory refresh method characterized in that the dynamic memory is refreshed using the free time in the memory access period from memory access to memory access in the next bus cycle. 2) If the execution of the bus cycle is stopped until a predetermined number of basic clocks are reached, the dynamic memory is refreshed every time the number of basic clocks reaches the predetermined number. A refresh method in the dynamic memory described in Section 1.