JPS61216555A - Demodulating device for msk signal - Google Patents

Abstract

PURPOSE:To enable to discriminate the center of demodulated data at all times irrespective of phase of a signal of frequency 1/2 of reproduction clock by extracting modulated component of MSK signals, reproducing reproduced clock signals, taking out low band component of output of two synchronism detectors intersecting at right angles by a low pass filter, and making proper measure successively. CONSTITUTION:A synchronism detector 52c, a voltage control oscillator 52e and a low pass filter 52d form a phase locked loop 52, and regenerate reproduced clock signals f(t) synchronized to modulated clock component of inputted signals S(t), and take out low band component of output of two synchronism detectors intersecting at right angles by a low pass filter. After making multiplication by 1/4 frequency of a reproduction clock signal and two signals intersecting at right angles, product of the two multiplication output is taken, and the product of the output and the reproduction clock signal is obtained. Thereby, signal component that becomes function of phase error between the input signal and reproduction carrier is generated, and reproduction carrier is generated by controlling the phase of oscillation output of a voltage controlling oscillator making the component that becomes function of phase error controlling voltage.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention provides a method for demodulating a signal using M8, which makes it possible to always identify the center of demodulated data, regardless of the phase of the signal at the frequency of the reproduced clock. Regarding equipment.

[Technical background of the invention and its problems]

The MSK signal is a phase modulation method for one singel (T seconds), and the carrier phase between each singel is continuous, so it is known as a method with a constant envelope and a high degree of concentration of the signal spectrum. There is.

As demodulation methods for MSK signals, (a) a method of demodulating using an FM detector, since MSK signals can also be considered a type of FSK signal, (b) a method of demodulating using an FM detector;
A simple method is a delayed detection method in which the preceding signal is delayed by one signal time T, shifted by 90', and multiplied by taking advantage of the fact that the phase changes by 10 or - 17 times. Although the above two methods have a simple demodulator, they have the disadvantage that the bit error rate for the same 0/H is worse than the synchronous detection method in which the demodulator regenerates the carrier wave and performs synchronous detection.

As a method for regenerating carrier waves on the demodulator side, QPSK (Quadratur@Phas) is used as shown in Figure 4.
eShift Keying) Similar to the demodulator, a method can be considered in which the input signal is multiplied by 4 and the influence of the modulated signal is removed.

That is, the input signal 1 is input to the clock regeneration circuit 2 circuit 3, which divides the frequency by τ and sends the output 3& with no phase shift to the integral discrimination circuit 4, and output 3b with the phase shifted by 90°. It is sent to the integral identification circuit 5.

In addition, the input signal 1 is input to a quadruple multiplier 6 in the carrier regeneration circuit 6.
a and is input to multiplication circuits 7 and 8. The input signal 1 input to the quadruple multiplier 6& is multiplied by four in frequency and sent to the multiplication circuit 6b.

The multiplication circuit 6b multiplies the signal by the output signal of the oscillator 6d and inputs the result to the low-pass filter 6c.The low-pass filter 6c passes a low frequency region component, and the frequency division circuit 6 divides the frequency to 1. The output 6.1 of the frequency dividing circuit 6. is sent as it is to the multiplication circuit 7, and is also outputted to the multiplication circuit 8 after having its phase shifted by 90° through a 90' phase shifter 9.

The multiplier circuit 7 multiplies the input signal 1 by the output of the i frequency divider 6 and outputs it to the integral discrimination circuit 4, and the multiplier circuit 8 multiplies the input signal 1 and the output of the 90° phase shifter 9. is multiplied and output to the integral identification circuit 5.

The integral identification circuit 4 connects the output 3a of the τ frequency dividing circuit 3 and the multiplication circuit 1.
The integral state is identified from the output of , and demodulated data is output. Similarly, the integral identifying circuit 5 identifies the integral state from the output of the multiplication circuit 8 and the output 3b of the i frequency dividing circuit 3, and outputs demodulated data.

The MSK demodulation method shown in FIG. 4 has the disadvantage that the singel timing of the two-axis synchronous detection output and the identification clock timing are not synchronized because the reproduced carrier and the reproduced clock are generated independently.

That is, as shown in the signal generation process of FIG. 6, the MsK signal is
The data timings of the I and Q axes shown in FIG. 6(b) and FIG. 6(c), respectively, are shifted by Ts@c. I on the sending side,
Which of the Q-axis data appears on the demodulation axis 1.2 cannot be determined because it is determined by the phase of the reproduced carrier wave (Fig. 6 (d), Fig. 6 (e)). The demodulation method shown has a drawback in that the timing relationship between the demodulated data and the identification clock cannot be limited to 1:1.

As a method for eliminating this drawback, a method can be considered in which a clock component is extracted from the synchronous detection output, as shown in FIG.

In the case of FIG. 5, the input signal 1 is the output of the divide-by-1 circuit 6 of the carrier regeneration circuit 6 similar to that of FIG.
It is also sent to the multiplication circuit 8 through the 900 phase shifter 9. The multiplication circuit 2 multiplies the output of the T frequency division circuit 6 and the input signal 1 and sends the result to the integral identification circuit 4.

The multiplication circuit 8 multiplies the input signal 1 and the output of the 90' phase shifter 9 and sends the result to the integral discrimination circuit 5.

Further, the output of the multiplication circuit 2 is input to the amplitude identification circuit 10h of the clock recovery circuit 10, where the amplitude is determined and outputted to the multiplication circuit 1ob.

The multiplication circuit 10b divides the output of the oscillator 10d by 1.
．． Multiply the frequency-divided signal by using the low-pass filter 0c.
The output of the oscillator 10d is sent to the integral discrimination circuit 4 as it is, and the output with a 90° phase shift is sent to the integral discrimination circuit 5 through the oscillator 10d. The integral identification circuit 4 identifies the integral state depending on the output of the multiplication circuit 7 and the output of the multiplication circuit 7, respectively.

In this case, if the recovered carrier wave causes a cycle slip due to the influence of noise, the demodulated data timing shifts by Ta@e, causing the clock recovery circuit 10 to be out of synchronization, and a burst error occurs during this time.

Therefore, as a MsK signal demodulator, (a)
(b) A method in which the phase of the regenerated carrier is controlled depending on the phase of the regenerated clock.

A typical example of the former is shown in FIG. This demodulation method is known as an application of the demodulation method devised by 5und. as a demodulation method for FSX signals with a modulation index l.

In FIG. 7, the input signal is input to the multiplier circuit 12 and multipliers 13 and 14, and the frequency of the input signal is doubled in the multiplier circuit 12 to obtain (2π/c+t)HzT phase-locked circuit 1s, ( 2π/e−...)Hz Input to the phase synchronization circuit 16 and (2π/c + 2T) H
After z, adder 19, 20 and multiplier 21, respectively.
Output to.

The frequency dividing circuit 12 outputs signals of the same phase, and the frequency dividing circuit 18 outputs signals of mutually opposite phases. Thereby, the adder 19 is connected to the frequency divider circuit 17. The adder 20 adds the outputs of the frequency dividing circuit 17 and outputs it to the multiplier 13.
8 is subtracted and output to the multiplier 14.

The multiplier 13 multiplies the output of the adder 19 and the input signal and outputs the result to the integration, sampling and dump circuit 22, and the multiplier 14 multiplies the output of the adder 20 and the input signal to perform integration, sampling and dumping. Output to circuit 23.

On the other hand, the multiplier 21 adds the outputs of both the frequency dividing circuits 17 and 180, and then inputs the result to the loaf 4 filter 24, where the low frequency component is extracted. The integration, sampling and dumping circuit 2 uses the inverted signal of the loaf 4 filter 24 as a clock.
Outputs 21fC.

The integration, sampling and dump circuits 22 and 23 integrate the outputs of the multipliers 13 and 140 based on the clock, respectively.
The signal is sampled, dumped, sent to differential amplification and decoding circuits 26 and 27, and decoded there, after which a serial demodulated signal is obtained from parallel-serial conversion circuit 28.

This carrier-dependent MSK demodulation method requires two phase-locked loops at high frequency, and double multiplication at the high frequency stage.
Since a frequency divider circuit is required, the device is complicated and expensive.

[Purpose of the invention]

The present invention has been made to eliminate the drawbacks of the conventional methods described above, and it is an object of the present invention to provide a signal demodulation device for M8 with a simple configuration and high performance.

[Summary of the invention]

The MSK signal demodulation device of the present invention extracts the modulation component of the MsK signal to regenerate a recovered clock signal, extracts the low-frequency components of the outputs of two orthogonal synchronous detectors using a low-pass filter, and extracts the modulation component of the MSK signal to reproduce the recovered clock signal. After multiplying by two signals having a frequency of 174 and orthogonal to each other, taking the product of these two multiplication outputs and multiplying that output by the recovered clock signal, the phase error between the input signal and the recovered carrier wave can be calculated. A signal component that is a function of the phase error is generated, and the phase of the oscillation output of the voltage controlled oscillator is controlled using the signal component that is a function of the phase error as a control voltage to generate a regenerated carrier wave, and the two multiplication outputs are The digital data of each orthogonal axis of the MSK signal is demodulated by identifying clock signals having different polarities at the frequency W of the reproduced clock signal.

[Embodiments of the invention]

Embodiments of the MSK signal demodulation device of the present invention will be described below with reference to the drawings. FIG. 8 shows an MSK modulator that extracts a modulation component of an MSK signal input to the MSK signal demodulation device of the present invention.Before explaining the demodulation device of the present invention, the MSK modulator will be briefly described.

In FIG. 8, when an input signal is input to a serial/parallel converter 31, serial data is converted into parallel data and sent to differential encoders 32 and 33. Differential encoder 3
2. Encode the parallel data in step 3 and add the orthogonal I-axis and Q-axis digital data I(t) and Q(t) to the multiplier 3.
Output on 4.35.

Further, a clock signal is input to the phase synchronized oscillator 36,
This phase synchronized oscillator 36 generates a clock signal synchronized with this clock signal, which is sent to the multiplier 34, and is also input to the 9o0 phase shifter 37fC, where the 900
'The clock signal -2T is sent to the multiplier 35 with the phase shifted.

The multiplier 34 multiplies the output 1(t) of the differential encoder 32 by the clock signal corridor, and the result! (t)・”2T
is output to the multiplier 38. Similarly, the multiplier 35 multiplies the output Q(i) of the differential encoder 33 by one clock signal alI, and outputs the result Q(t)·al12T to the multiplier 39.

The multiplier 38 receives a carrier wave (hereinafter referred to as carrier) ωot with an angular frequency ω0 from the carrier oscillator 40.
At the same time, the carrier (2) aos is outputted to the multiplier 39.

The multiplier 39 calculates the carrier blood ωat and the output I of the multiplier 34.
Multiply by (t) ・tiba 2T and get 1
Adder 4211 calculates (t)-gm1d-blood ωat
C output.

Similarly, the multiplier 39 is the carrier billion ωot and the multiplier 3
5 is multiplied by the output Q(t)·all−i in row 9T to calculate I(t)·”2T−(2) aos and add it to the adder 42.

An adder 42 adds the outputs of both multipliers 38 and 39, and calculates M of a predetermined frequency band to a bandpass filter 43.
Modulation signal of SK signal 1(t)-m-juice・tnωo t
+ Q(t) aos )1ωot is output.

Q(t)·Cogπ·(2)aos becomes the input signal 5(t) of the MSK signal input to the demodulator of the first embodiment of the present invention shown in FIG.

This input signal 5(t) is expressed as the following equation (1) similar to the above.

S(t)=I(t)−mωo t −dn sho+Q(t
)・asωgt6cm,.

... (1) In this equation (1), ωG is the carrier angular frequency (ra
d/see ), and T is the data length (aec). This input signal 5(t) is input to the multiplier so in FIG.
, 51. and the band pass filter 52a of the carrier phase locked loop 52 (clock signal generation circuit).The output of the band pass filter 52 & of the carrier phase locked loop 52 is subjected to envelope detection by an envelope detector 52b. The modulation component of the MSK signal is extracted and the output thereof is sent to the synchronous detector 52c. This synchronous detector 52a includes a voltage controlled oscillator 52e (
The synchronous detector 52e synchronously detects the output of the envelope detector 52b using the output of the low-nosage filter 524. and output the output to VCO5
2.

The oscillation frequency is controlled by the output of the VCO 52 and the synchronous detector 52c.

The output of the VCO 52e is a multiplier srs”12 frequency divider circuit 53
It is designed to be sent to The output of the A frequency divider circuit 53 is passed through a timing determiner 56 (consisting of a D-7 rip-frog) and a polarity inverter 55 to a timing determiner 57 (consisting of a D-7 rip-frog). It is a trap to send out

Further, the output of the A frequency dividing circuit 53 is passed through the A frequency dividing circuit 58.
The signal is sent to a 90° phase shifter 59 and a multiplier 60.

The output of the 90' phase shifter 59 is sent to a multiplier 62.

The multiplier 61 multiplies the output of the vco s z · by the output of the multiplier 63 and outputs the resultant voltage through the low/4 filter 4.
It is designed to output to CO65.

The VCo 65 controls the oscillation frequency (based on the output voltage of this rotary filter 4) and outputs it to the synchronous detector 50.
It is designed to output to 1.

The synchronous detector 50 receives the input signal 8 at the output of vcoss.
(t) is synchronously detected and its output is sent to the low/mother filter 1, and the output of the low 4X filter 67 is sent to the multiplier 60.

The synchronous detector 51 synchronously detects the input signal 5(t) using the output of the 906 phase shifter 66, and outputs the output to the low 14 filter 8. The output of this rotary filter 8 is sent to a multiplier 62flC.

The multiplier 60 multiplies the output of the low/4 filter 1 and the output of the A frequency dividing circuit 58, and outputs the result to the multiplier 63 and timing judger 52. The output of the Q-/S filter 8 is multiplied by a 90° phase shifter 59, and the result is output to a multiplier 63 and a timing determiner 56.

The multiplier 63 multiplies the output of the multiplier 60 and the output of the multiplier 62 and outputs the result to the multiplier 61.

The timing determiner 51 determines the timing of the output of the multiplier 66 based on the output of the polarity inverter 55, and makes the output orthogonal to the MSK signal! It is designed to output a demodulated signal of digital data of the axis.

Similarly, the timing determiner 51 determines the timing of the output of the multiplier 62 based on the output of the A frequency dividing circuit 53, and outputs a demodulated signal of Q-axis digital data orthogonal to the MSK signal. It has become.

Next, the operation of the MSK signal demodulation apparatus of the present invention constructed as described above will be explained.

In the input signal 5(t) shown in equation (1), I(t)
.

Q(t) is a coefficient determined depending on the state of the data signal on the transmitting side, and takes a value of "+1" or "-1".

πt πt The timing relationship between x(t), Q(t), and blood−0 possibleπ is shown in FIG.

As shown in Fig. 2, I(t) (W, Fig. 2 (a)) has symbol change points at 0, 2T, 4T, ... 2NT (N is an integer)], and the second As shown in figure (b), Q(t) is T, 3T, ... (2N-)-1)T
(N is an integer) has a symbol change point.

Input signal 5(t) is distributed to three outputs by a distributor (not shown). One of the outputs is supplied to a narrowband bandpass filter 52h. Narrowband bandpass filter 52
m is a bandpass filter whose passband width is narrower than the transmission bandwidth of the input signal 5(t). Therefore, nine envelope changes occur in the output of the bandpass filter 52m corresponding to the modulation components. The envelope detector jjb is a circuit that detects the changing component, and its output is supplied to the synchronous detector 52e.

Synchronous detector 52 c, VCOS j @ 10-pass filter 5. ? d forms a phase-locked loop 52 to generate a reproduced clock signal f(t) (FIG. 2(e)) synchronized with the modulated clock component of the input signal 5(i).

According to equation (1), the recovered clock signal f(t) is expressed as follows.

f(t) = spontaneous -(2) This phase-locked loop 52 operates as a clock signal regeneration circuit. The reproduced clock signal f(t) is supplied to the A frequency divider circuit 53. In the case of a digital signal, the W frequency divider circuit 53 can be easily constructed with a flip-flop circuit.

The output signal g(t) of this W frequency dividing circuit 53 (Fig. 2(f)
), Figure 2 (g) λ family, depending on the initial operating state of the circuit) takes the following two states as shown in equations (3) and (4) (that is, with an uncertainty of 180°) ).

g(t)=Juji-or-dego...(3)T
T Furthermore, by passing the output g(t) of the opportunity frequency circuit 53 through the 90' phase shifter 54, the output h(t) becomes as shown in equation (4).

h(t) =+(2)- or -(2)-...(4
) T T Therefore, the circuit operating states will be described below for the two states.

Prisoner g(t) =+ghI” (h(t) = “Nodo @ vCo 65 (r)T
T output R1(t) is defined as follows R, (t) = m (ωat+ψ) ...(
5) In this equation (5), ψ is the phase difference between the carrier of the input signal 5(t) and the output R1(t) of vcot;s.

At this time, the output am (tL, ,
(1) is given by the following equation.

al(t)=S(t)Xm(ωot+w)=(6
) a z (t) = 8(t) X(X1g (ωa
t+ψ) - (7) Output signal a□(t) of this synchronous detector 50.51.

a s (t) C'f-tL each low-pass filter 6
7.68 is applied. Low pass filter; 7/, 6
B is used to remove high-frequency carriers and their harmonic components, and their outputs bt (t) and bs (t) are expressed by the following equations, respectively.

b 5(t) = (1(t)・Blood−・(2)ψ+Q
(t)・Machi “Blood ψ)2 2T ・−(8) 1 πt πt bs(t)= (I(t)sfn−・Yu ψ+Q(j)
(XST” bunch ψ) 2 Correction... (9) The output signal bs (t) of the low/4 filter rotor 2 is sent to the multiplier 60, and the output signal b of the row 14 filter rotor 8 is
z(t) is sent to multiplier 62. The multiplier 60 outputs the product Ls (t) of the output g(t) of the W frequency dividing circuit 58 and the output bl(t) of the low-pass filter 61. Similarly, the multiplier 62 outputs the output No. 71 k(t) obtained by shifting the W frequency divider circuit 58o' output g(t,) by 90' phase with the 90' phase shifter 59 and the output bx(t,) of the low/4 filter 8. Product L *
(t) is output.

The output signal g(t) of the A frequency dividing circuit 58 is expressed as g(
t) = 11 2T '' (2). Therefore, the output signal k(t) of the 90° phase shifter 59 becomes k(t) = ±cx1M-i 2T . . . αυ. Therefore, the multiplier 60 Output 21(1) of .62.

tz (t) is given by the following equation.

AI(t) = bt(t) X g(t)1
πt = ±−I(t) (−possible←iMψ)+(2)ψ)...
a3 (t) ” bs (t) X k(t)1
πt =±-Q(t)(a+5(-y+Mψ)+mψ)...
Sumitomo However, α3, <13 In the formula, M is a newly introduced coefficient and is the following α4. Defined by α9 formula.

M = I(t) x Q(t)=+1 (I(t)
=Q(t)...I g=I(t)xQ(t)= -i (1(t) lol q(
t) )・−(Is The output of this multiplier 60.62 tl (t) −tz (
t) are each sent to a multiplier 63 and multiplied. The multipliers 60, 62, and 63 may be analog multipliers, or the respective output signals b1(t) and bs(t
) is converted into a digital signal, it can also be realized with an exclusive OR circuit.

The output a(t) of this multiplier 63 is given by a quadratic equation similar to the α2,03 equation above.

c(t)=M(asp cas2(-i+M9!'
)) 16 T = YuM (ax 2ψ-ctxz (T + 2Mψ)
) ...αe2πt The output signal c(t) of the multiplier 63 is applied to the multiplier 61 and multiplied by the output signal /(1) of the VCO 52e. Like the multipliers 60, 62, and 63, the multiplier 61 may be either an analog type or a digital type. The output signal d(t) of this multiplier 61 is expressed by the equation (2) above, (from the US equation -iMdn (%'+2Mψ)4dn29...αη.The output signal d(t) of this multiplier 61 is ) is sent to the low-pass filter 4.C!-a# The filter 4 removes high frequency components, and its output,
(1) is given by α9 formula as follows.

e(t) = -g-4ghx29
"""Output signal of low-pass filter 4/ct)
Ha vc.

65 and is supplied as a control voltage for this VCo 6 B. As a result, the portion (portion 52) surrounded by the dashed line in FIG. 1 operates as a carrier phase locked loop.

The stable point of this carrier phase locked loop 520 is 5(t)=O
So 1. This is the point at which the differential coefficient e'(t) of (1) becomes positive.

Therefore, I formula 29) = O, fNawachi f = Nff (N = 0, 1
, 2.) (19.

That is, this carrier phase locked loop 52 is a 4-phase PSK
has four stable points, whereas it has two stable points (
O1π). This is because the carrier phase synchronization loop f52 is controlled by the reproduced clock signal.

Substituting the above α9 formula into (8) and (9)2, the output signal bt (t) * of Loaf 4 filter Taro 1.68 is obtained.
bm(t) can be tl as follows.

bm(t)=±-Q(t)・(2)−・・・(to)2
2T On the other hand, the output signal J(t) of the A frequency dividing circuit 58 is expressed by the formula (3)%
The formula %(2) is obtained. Therefore, the output signal k(t
) becomes k(t) = ±"2T-... (to). Therefore, the output signal t1(t)(
(Fig. 2 (h)), tt (t) (Fig. 2 C1)) C4 formula.

(c) Equation, ii) Equation: Lx (t) = ±-I(t) 2 ft = ±-! −
I(t) (1-(2)-)2 2r4 T...) 1x (t) =±-Q(t)(2)2!1=±"Q(
tX1+Equipment ()2 2T 4 T...(c).

The output signal 4 (t) pta of this multiplier 60.62
As shown in Figure 2, the timing relationship of (t) is that the output signal 11 (t) is at the center of the data at t=T, 3T...(2N-1)T, while the output signal Lx (t) is t =
0.2 T...2NT is the center of the data.

Similarly to the case (4), the output signal j(
t) is j (t) = fdn (----) = Kamimachi "・
...(a) 2T 2 . Also, the output signal k(t) of the 90° phase shifter 59 is k
(t)=shibei←−−−)engineering+da......to)T
It becomes 2. Hence the multiplier 60,6! The output jt(t)−tt
(t) is given by the following equation.

1-t (t)=bt (t) X g(t)=±LQ
(t) (-skin Mψ) pongee ψ)... (b) 1s (t)
= bs (t) X k(t)=-1--I(t)(-
(2) (go+Mψ)transport ψ)... (to) Therefore, the output a(t) of the multiplier 61 is expressed as follows.

d(t)=-m-(ya+29)-64'blood(sato-29)
+Upper Mdn (” +2Mψ)-1 Blood 291 =-@
4 T Therefore, the output signal e(t) of the low-pass filter 64 is given as follows.

l ... (to) @ (t)
=1 s * 2ψ Therefore, in case (B), carrier phase synchronization Rouzoro 2
From equation (2), the 0 stable point is ψ=(N+-)π(N=0.1.2...)...
・(31) becomes. .

That is, in case (2), it becomes a carrier phase locked loop.

Substituting equation (31) into equations (8) and (9), 1
tt bx (t)=±-Q(t)・Maki■...
(32) b-tou(t)=±-x(t)・IIkLπ
...-(33).

On the other hand, the output signal j(t) of the frequency circuit 58 and the output signal k(t) obtained by shifting the phase of this output signal j(t) by 90° by the 90° phase shifter 59 are expressed by the following equation (34), ( 35)
Expressed as an expression.

0 ・−(34) j(t)−±(2)7r k(t) = origin π ・・・(35
) These output signals j(t) and k(t) are multiplied by multipliers go and 62 with output signals bx(t) and bx(t) of the ronos filter 611, respectively, to produce an output signal Ax(t ) ((4) in FIG. 2, tx(t) (in FIG. 2)) are output to timing determiners 57 and 56, respectively.

The output signals ts (t) - tt (t) are expressed by the following equations (36) and (37), respectively.

tx(t) Fuji-I(t) (1-(2)-) ・
...(37)4 As can be seen from equations (36) and (37), (B
), the output signal tt(t) of the multiplier 60.62.

tt(t) is exactly the opposite of ). However, the identification timing signal -g(
t) (Fig. 2 (ω), the identification timing signal 0 g (t) obtained from the A frequency divider circuit 53 (Fig. 2 (1)) is also exactly the opposite of the case (4), so the The data timing and identification/4th pulse timing are the same combination to identify the center of the data.

As explained above, the embodiment shown in FIG. 1 can always identify the center of demodulated data regardless of the phase of the A-period signal of the reproduced clock.

Note that the I-axis data and Q-axis data on the transmitting side are
Whether the axis data is demodulated is not an important issue. In other words, like the QPSK signal demodulator, there is a temporal order relationship between I-axis data and Q-axis data, so
At the time of parallel-serial exchange, it is only necessary to sequentially switch and transmit the data of the two axes in synchronization with T seconds.

Furthermore, as described above, the demodulated data remains with (±) polar ambiguity, which is explained in (7) below.

0) can be solved using either method.

(7) A method in which I and Q axes are differentially encoded on the transmitting side and differentially decoded after demodulation on the receiving side (differential encoding method); (f) Inserting specific 74 turns into the transmitting code in advance A method of determining the polarity of the demodulated data from the shape of the demodulated specific i4 turn on the receiving side (coherent method)
, The above method is the same method as used in the offline QPSK signal demodulation device. This is because the MSK signal is obtained by balanced modulating the signals of each axis of the offset QPSK signal at 2T'-2T, as is clear from the signal generation process described above, so after demodulating the MSK signal and identifying the timing, It is clear that the format of the signal is the same as the offset QPSK.

Next, a second embodiment of the MSK signal demodulation device of the present invention will be described. FIG. 3 is a block diagram showing this second embodiment. In FIG. 3, parts that are the same as those in FIG. I will focus on this.

As shown in FIG. 3, the means for reproducing a clock signal from demodulated data is also different from the above embodiment. That is, in the carrier phase locked loop 52, the exclusive logic circuit 52f takes the exclusive OR of the output of the amplitude discriminator '10.71 and outputs it to the synchronous detector 52e. The output of the VCO 52 is input to the . The output of the synchronous detector 52c is Rono J? The signal is input to the vCO through a filter.

Amplitude discriminators 70.71 discriminate the amplitudes of the outputs of the multipliers 60 and 620, respectively, and output them to the exclusive OR circuit 52f1 and timing discriminator 51.56.

1 in that the output of the W frequency divider circuit 58 is applied to the multiplier 61 through a 90° phase shifter 54.

In the case of FIG. 3, there is no need for a narrow band filter and an envelope detector in the high frequency stage, and the advantage is that the clock recovery circuit can be constructed entirely from digital circuits.

In addition, in the case of Figure 1, the sequence is that carrier synchronization is established after clock synchronization is established, so the clock regeneration circuit is not affected by the carrier synchronization circuit and is an extremely stable circuit, but in this Figure 3, the demodulated data Since the clock signal is recovered from the carrier, the clock recovery circuit is affected by the carrier synchronization state.

However, if the transmission clock signal is extremely stable compared to the carrier, the VCO of the clock recovery circuit can be made highly stable. Therefore, since the loop band of the clock synchronized loop can be made sufficiently narrower than that of the carrier synchronized loop, clock synchronization can be maintained for a sufficient period of time for carriers to be resynchronized even when carrier synchronization is lost.

Therefore, a modification can be realized as a signal demodulator using M8, which has a sufficiently high stability of the clock compared to the carrier.

〔Effect of the invention〕

As described above, according to the M8 signal demodulation device of the present invention, the modulation component of the MSK signal is extracted to regenerate the recovered clock signal, and the low frequency components of the outputs of two orthogonal synchronous detectors are converted into low frequency components. 17 of the regenerated clock signal extracted by the filter
between the input signal and the regenerated carrier wave (by multiplying by two orthogonal signals with a frequency of A signal component that is a function of the phase error is generated, and the phase of the oscillation output of the voltage controlled oscillator is controlled using the component that is a function of the phase error as a control voltage to generate a regenerated carrier wave, and the two multiplied outputs are Since the digital data of each orthogonal axis of the MSK signal is identified by a clock signal with a frequency of 1/12 of the reproduced clock signal and a different polarity, the digital data of each orthogonal axis of the MSK signal is demodulated. It has the advantage that the center of demodulated data can always be identified regardless of the

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the MSK signal demodulation device of the present invention, FIG. 2 is a time chart for explaining the operation of the signal demodulation device M8 in FIG. 1, and FIG. 3 is the present invention. Figure 5 is a block diagram of a conventional MSK signal demodulation system, Figure 6 is a time chart for explaining the operation of the demodulation system of Figure 5, and Figure 7 is a conventional carrier dependent type demodulation system. A block diagram of the MSK demodulation method, FIG. 8 shows the MSK applied to the MSK signal demodulation device of the invention of
FIG. 2 is a block diagram of an MSK modulator that creates a modulated signal. 50.51, 52a... Synchronous detector, 52... Carrier phase locked loop, 52 e, 65 ・-VCOl
sort...exclusive OR circuit, 53.58...opportunity frequency circuit, 59.60...90' phase shifter, 55...
Polarity inverter, 56.5'i...timing judge, 6
0 to 63... Multiplier, 70.11... Amplitude discriminator.

Claims (1)

[Claims] A circuit that extracts the modulation component of the MSK signal and regenerates the recovered clock signal, and a circuit that extracts the low-frequency components of the outputs of two orthogonal synchronous detectors using a low-pass filter, then connects the two orthogonal synchronous detectors. Multiplying the output of 2 by two signals having a frequency of 1/4 of the reproduced clock and orthogonal to each other.
A multiplication circuit that takes the product of the outputs of these two multiplier circuits, and a multiplier circuit that takes the product of the outputs of the two multiplier circuits, and the product of the output of the multiplier circuit and the recovered clock. means for generating a signal component that is a function of the phase error; a carrier synchronization circuit that obtains a recovered carrier wave by controlling the oscillation output phase of a voltage controlled oscillator using a component that is a function of this phase error as a control voltage; 2
1. A demodulating device for an MSK signal, comprising means for identifying the outputs of the two multipliers using a clock signal having a frequency and a different polarity, and demodulating digital data on each orthogonal axis of the MSK signal.