JPS61208692A - First write first read memory device - Google Patents

Abstract

PURPOSE:To enable writing and reading to be performed independently by providing a multiplexer for selectively sending to a memory one of the outputs of writing and reading address counters and a controller executing writing and reading independently. CONSTITUTION:The writing address counter 20 and the reading address counter 30 generate a writing address WRADR and reading address RDADR from clock signals VCLK and RCLK from the controller 60. An up/down counter 40 counts up when a mode signal RW is in the write mode and counts down when it is in the read mode. The multiplexer 50 supplies the output WRADR of the write address counter 20 to the memory 10 and supplies the output RDADR of the read address counter 30 when in the read mode. The controller 60 is formed by using sequential circuit and fuse logic. In such a manner reading and writing can be performed independently.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to a first-in-first reading method.
The information below stOut is simply referred to as FIFO. ) relates to storage devices.

[Conventional technology]

FIFO storage devices have the advantage of being able to read and write data at high speed, so they can be used for CRs that require high-speed display functions.
It is used in T display devices, etc.

Conventionally, such FIFO storage devices have been available, for example, using easily available commercially available FIFG memory chips, FIFO controllers, and RAM.

(The problem that J! Ming is trying to solve) However, commercially available FIFO memory chips, for example,
There was a problem that the capacity was small like that of G4x4 bit. Moreover, the unit cost of such memory chips themselves is high, and if multiple chips are used to increase capacity, the cost becomes quite high.

Furthermore, commercially available FIFD controllers have problems in that write and read timings are not completely independent, are expensive, and require peripheral circuits.

For these reasons, it has been difficult to realize a FIFO storage device that can be easily used.

The present invention has been made in view of these points,
The object of the present invention is to realize a monthly FO storage device in which writing and reading are performed independently, has a large storage capacity, and is inexpensive.

[Means for solving problems]

The present invention provides a memory in which data can be read and written, a write address counter and a read address counter that generate write addresses and read addresses of the memory, and a memory that performs up-counting or down-counting in accordance with writing or reading. an up/down counter that outputs a signal according to the data storage state of the memory; a multiplexer that selectively sends one of the outputs of the write address counter and the read address counter to the memory in response to writing and reading; and a read/write mode for the multiplexer. a controller that sends signals to allocate write time and read time on a time-sharing basis, and performs memory write and read by handshaking signals in response to external access while referring to the output of the up-down counter; [Example] The present invention will be explained below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a FIFO storage device according to the present invention.

In Figure 1, 1 is a memory, 2 is a write address counter, 3 is a continuous address counter, 41 is an up/down counter, 5 is a multiplexer, ■ is a controller, 7 is a buffer, and ■ is a register It is.

Memory ■ is Sugamu M. This memory (2) is read and written in response to a read/write mode signal RW and signals from the multiplexer 5e and controller (2).

The write address counter 2 and the read address counter 3- receive a clock signal WCLI from the controller ①.
and IcLK to generate a write address WIAIII and a read address Di.

Up/down counter 4 is a mode signal! When W is in write mode, it counts up, and when it is in read mode, it counts down, and when the contents of memory 1e become full when writing, or when the contents of memory become empty when reading. At times, the IC (ripple carry) signal is changed to Tr, u. (old GH state) and output. Further, the up/down counter 4- receives clock signals CC and LE from the controller (2) and is reset by a reset signal R1S.

The multiplexer 51 outputs the output of the write address counter WIAD when the mode signal t1 is in the write mode.
When t is given to memory 1 and it is in the read mode, the output DR of continuous address counter 3 is given to memory 1.
Give to 1.

The controller ■ converts sequential circuits into fuse logic (FU
By using SE LOGIC), for example! This can be realized with a 1-pin L package.

The controller (2) is supplied with a clock signal CLI, a mode signal tW, and a reset signal IEs. This controller ■ receives the signal 1 from the up/down counter 4.
c detects the storage state of the memory II.

Further, the controller 6- sends and receives signals by handshaking in response to external access, and performs writing and reading in the memory l. The signals used for handshaking are II, IACE, OUT and 0mC1.

Among these signals, ■ and IACE are used for writing,
OUT and 0ACI are used for reading, respectively.

Buffer 1- receives input data D in response to mode signal tW.
Temporarily store IN. This buffer 1 is memory 1.
This is not necessary if the input/output is separated type.

Further, the output of the buffer 7 is controlled by the mode signal RW.

Register I receives write signal 5T from controller 1.
In response to tl, the data read from memory +e is temporarily stored. The output of register (2) is given to the outside as data output DOUT.

Next, the operation of such a FIFO storage device will be explained.

FIG. 2 is a time chart for explaining the operation of the apparatus shown in FIG.

In Figure 2, (a) is the reset signal US, (b) is the mode signal, (C) is the ripple carry signal 1c1 (d) and (e) is the handshake signal in the case of writing ■ and I
IIACI.

(f) is a write signal wx, (g) and Ch) are a write clock signal WCLI and a read clock signal RCLE,
(1) is the controller clock signal CCII, (J
) is the address signal MDI, and (g) and (j) are the write address signal W! M■ and read address signal MDI,
ii is a strobe signal ST2 for instructing writing to the register 8, (b) and (c) are handshake signals 0 (IT and 0m Cl) for reading.

First, at time [, the write address counter 2 and the read address counter 31 are reset by the reset signal lll5.
The counter value of is set to 0, and the controller (2) is set to its initial state.

The output of the write address counter 2. represents the address of the memory I. at the time of writing, and the output of the read address counter 3. represents the address of the memory I. at the time of reading. The clock WCL from the controller ■ is output every time writing and reading are completed.
It is counted up by one by I and ICI4.

By the operation of the multiplexer 5-, the output WRADR of the write address counter 2- is selected during writing, and the output ``M'' of the read address counter 3- is selected during reading, and becomes the address ``I'' of the memory 1.

Up/down counter 4 indicates that memory 1 is full (FU
LL) or empty (EMPTY). That is, during writing, the up/down counter 4I is placed in an up-count mode by the mode signal I, and each time data is written into the memory 1-, the count value is incremented by one by the clock CCLI from the controller (2). When all the count values are l, that is, the memory l
When ・ becomes FULL, output 1c becomes Tru・(H
IGH state) and notifies controller ■ of this.

On the other hand, at the time of reading, the up/down counter 4.
The down count mode is set and the data is stored in the memory.
Clock C from controller ■ every time it is read from
The count value decreases by one by CL[. Up-down counter! When all the outputs of 1 become 0, that is, when the memory (2) becomes IMFTT, the output 1c becomes True (H'lGH state) again and notifies the controller (2) of this.

Memory 1e is 2'Xm bits (l, 11 are arbitrary integers)
In the case of the configuration, counters 2 and 3 have n bits.

The mode signal tW is a signal that determines write and read modes, and also serves as a signal for determining the write and read modes.
It also serves as the count mode (up-count or down-count), selection signal for multiplexer s1, and output control signal for buffer 1.

Now, when all counters are cleared by the reset signal S at time t, the output tC of the up/down counter 4 becomes F@1g@ (LOW state) in the write mode and True (HIGH state) in the read mode. , the controller ■ has memory!・I know that is empty.

Here, time 1. When a write request ■ is input from the outside, the controller ■ outputs a write signal WE to the memory I in the next write mode (time ts), and writes the data to the address of the memory 1 at this time. ADt is 0 indicated by the write address WIADI. Furthermore, at time t when writing is completed, the write address counter 2 and the up/down counter 4e are counted up.

When the up/down counter 4- counts up,
The output IC is in the LOW state even in read mode (IIOTEM
PTV '), the controller ■ writes the data in the memory l to the register I using the strobe pulse signal ST■ at time t4, and sends the read request signal OUT to Tr.
ue (LO state), and further, the controller 6e
At time t, the read address counter 36 is counted up using the clock IcLK, and at the same time, the clock (:CLK) is used to count down the 7-up-down counter 40.The read mode continues until the signal 0ACK is returned (until time t). will be held.

Writing and reading are performed in this way, but if the write operation continues and the count value of the up/down counter 4 reaches the maximum, the signal RC becomes true in the write mode.
e(HIGH state m>), the controller ■ stops the next write. This corresponds to time t, the throat. After this, when the data in memory 1 is written to the register ■ at time t1, , the write stop is released.

【effect〕

According to such a FIFO storage device, the following effects can be obtained.

That is, address counters 2Il and 3. and memory I
By changing II, a large-capacity storage device can be realized in a package.

Further, since the time for reading and writing to the memory II is allocated in a time-sharing manner, reading and writing are independent, and the timing of reading is not affected by the write operation at all. This effect is effective when a FIFO storage device is used in the display device shown in FIG. That is, in the device shown in FIG. 3, when data from the vector generator Ill is written to the HAM (Video RAM) 2, writing to the buffer 3 occurs randomly, but reading is performed from the VRAM 2 in between refreshes of the CRT 4. The access timing must be performed at high speed, so it is not allowed that the read timing deviates during this write. FI according to the present invention
Using an FO device for the buffer 3 satisfies the above requirements.

Furthermore, a FIFO storage device can be realized using inexpensive elements.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the structure of an embodiment of the FIFO storage device according to the present invention, FIG. 2 is a time chart for explaining the operation of the device in FIG. 1, and FIG. 3 is an example of the use of the device according to the present invention. FIG. ■-...Memory, 2...Write counter, 3...
・・Reading counter, ■・・Up/down counter,
5... Multiplexer, ■... Controller.

Claims (1)

[Scope of Claims] A memory in which data can be read and written, a write address counter and a read address counter that generate write addresses and read addresses of the memory, and that performs up-counting or down-counting according to writing or reading, an up/down counter that outputs a signal according to the data storage state of the memory; a multiplexer that selectively sends one of the outputs of the write address counter and the read address counter to the memory in response to writing and reading; A mode signal is sent to allocate write time and read time in a time-sharing manner, and while referring to the output of the up/down counter, data is sent and received by handshaking in response to external access, and data is written and read from the memory. A read-ahead storage device comprising: a controller;