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JPS61198738A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS61198738A
JPS61198738A JP60039183A JP3918385A JPS61198738A JP S61198738 A JPS61198738 A JP S61198738A JP 60039183 A JP60039183 A JP 60039183A JP 3918385 A JP3918385 A JP 3918385A JP S61198738 A JPS61198738 A JP S61198738A
Authority
JP
Japan
Prior art keywords
semiconductor element
substrate
electrodes
resin
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60039183A
Other languages
Japanese (ja)
Inventor
Hiroaki Fujimoto
博昭 藤本
Kenzo Hatada
畑田　賢造
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP60039183A priority Critical patent/JPS61198738A/en
Publication of JPS61198738A publication Critical patent/JPS61198738A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the bump preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To conduct connections electrically through pressure-welding by bonding an electrode for a semiconductor element and a wiring for a wiring substrate by a resin between the element and the substrate through a projecting electrode. CONSTITUTION:Cr 2 is evaporated to a substrate 1 such as a Teflon film, an insulating film 3 having inferior adhesive properties with a Teflon resin, etc. is superposed, and openings are bored 5, and projecting electrodes 4 in Au, etc. are formed. Electrodes 7 for a semiconductor element 6 and the projecting electrodes 4 are conformed, and the element 6 is pressed 9 and pressure-welded. The dispersion of the thickness of the projecting electrodes 4 is absorbed by the substrate 1 having the soft quality of materials. A resin 8 such as acrylic resin is injected between the element 6 and the substrate 1, and cured at the normal temperature or under heating by heat, beams, etc. The substrate 1 is peeled on the interface between the insulating film 3 and the resin 8, and the electrodes 4 are transferred to the electrodes 7 for the element 6. Projecting electrodes are shaped to the transfer substrate 1 again, and the substrate is used repeatedly. The projecting electrodes 4 for the element 6 are pressed 9' to a wiring 12 for a wiring substrate 11, a resin 8' is injected into a clearance and cured, and pressing 9' is removed. According to the constitution, the semiconductor element can be mounted to the wiring substrate at a low temperature.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は１半導体素子を直接、配線基板上に搭載し、ワ
イヤレスで電気的な接続を行う半導体装置の製造方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor device in which one semiconductor element is directly mounted on a wiring board and electrical connection is made wirelessly.

従来の技術 従来の方法を、第３図を用いて説明する。この方法は、
フリップチップ法と称し、まず、半導体素子３６の電極
３７上に、Ｃｒ　、　Ｃｕ　、ムＵ等の下地金属４３を
順次蒸着し、エツチングにより、半導体素子３６の電極
３７０部分以外の下地金属を除去する。その後、メタル
マスクを用いて、半導体素子３６の電極３７０部分のみ
に、半田を蒸着し、加熱溶融させ半田バンブ３４を形成
する。その後、セラミック等よりなる配線基板４１にフ
ラックスを塗布した後、配線基板４１上に設けた配線４
２と、半導体素子３６の半田バンブ３４を位置合わせし
、半導体素子３６を配線基板４１上に設置する。その後
、２００°Ｃ〜２６０°Ｃ程度に加熱し、半田バンプ３
４を再溶融させて、半導体素子３６の電極３７と配線４
２と全電気的に接続するものである。Prior Art A conventional method will be explained with reference to FIG. This method is
It is called a flip-chip method, and first, a base metal 43 such as Cr, Cu, Mu, etc. is sequentially deposited on the electrode 37 of the semiconductor element 36, and the base metal other than the electrode 370 portion of the semiconductor element 36 is removed by etching. . Thereafter, using a metal mask, solder is deposited only on the electrode 370 portion of the semiconductor element 36 and melted by heating to form the solder bump 34. After that, after applying flux to the wiring board 41 made of ceramic or the like, the wiring 4 provided on the wiring board 41 is
2 and the solder bumps 34 of the semiconductor element 36 are aligned, and the semiconductor element 36 is installed on the wiring board 41. After that, heat to about 200°C to 260°C and solder bump 3
4 is remelted to form the electrode 37 of the semiconductor element 36 and the wiring 4.
2 and is fully electrically connected.

発明が解決しようとする問題点 このような従来の方法では、次のような問題点がある。The problem that the invention aims to solve Such conventional methods have the following problems.

（１）突起電極を有した半導体素子を使用する必要があ
るため、通常の半導体素子が使用できず、汎用性に欠け
る。(1) Since it is necessary to use a semiconductor element having a protruding electrode, a normal semiconductor element cannot be used, resulting in lack of versatility.

（２）半導体素子上に蒸着、エツチング等の特殊な処理
が必要なため、半導体素子のコストが高い。(2) Since special processing such as vapor deposition and etching is required on the semiconductor element, the cost of the semiconductor element is high.

Ｃ３）配線基板への接続時に、フシックスを用いるため
、半導体素子の配線の腐食の原因となり信頼性が低い。C3) Since fusion is used when connecting to the wiring board, it causes corrosion of the wiring of the semiconductor element, resulting in low reliability.

（４）配線基板の配線材料は、半田付けが可能なものに
限られるため、配線基板の選択の自由度が小さく、液晶
ディスプレイパネル等によく用いられるｉＴｏによる透
明配線等への接続は困難である。(4) Since the wiring materials of the wiring board are limited to those that can be soldered, there is little freedom in selecting the wiring board, and it is difficult to connect to transparent wiring etc. using iTo, which is often used in liquid crystal display panels. be.

（５）半導体素子と配線基板との接続に半田付けを用い
るため、配線基板は２００°Ｃ程度以上の耐熱性が必要
となり、液晶ディスプレイノ＜不／Ｌ４、耐熱性の低い
ものに接続するのが困難である。(5) Since soldering is used to connect the semiconductor element and the wiring board, the wiring board needs to be heat resistant to about 200°C or higher, and it is difficult to connect it to an LCD display with low heat resistance. is difficult.

問題点を解決するための手段 本発明は上記問題点を解決するため、転写用基板に、形
成した突起電極を、半導体素子の電極に圧接し、転写用
基板と半導体素子の間隙に樹脂を注入し、硬化させた後
、転写用基板を剥がし、突起電極を半導体素子の電極に
転写する。その後、半導体素子の突起電極を配線基板の
配線に、圧接させた状態で、半導体素子と配線基板の間
隙に樹脂を注入、硬化し、半導体素子の電極と配線基板
の配線とを電気的に接続するものである。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention presses a protruding electrode formed on a transfer substrate to an electrode of a semiconductor element, and injects a resin into the gap between the transfer substrate and the semiconductor element. After curing, the transfer substrate is peeled off and the protruding electrodes are transferred to the electrodes of the semiconductor element. After that, with the protruding electrodes of the semiconductor element pressed into contact with the wiring of the wiring board, resin is injected into the gap between the semiconductor element and the wiring board and cured to electrically connect the electrodes of the semiconductor element and the wiring of the wiring board. It is something to do.

作用 本発明は上記した構成により、半導体素子の電極と、配
線基板の配線とを、突起電極を介して、半導体素子と配
線基板の間隙に形成した樹脂の接着力により、圧接で電
気的な接続が得られるものである。According to the above-described structure, the present invention electrically connects the electrode of the semiconductor element and the wiring of the wiring board through the protruding electrode by pressure welding by the adhesive force of the resin formed in the gap between the semiconductor element and the wiring board. is obtained.

実施例 本発明の一実施例における半導体装置の製造方法を第１
図と共に説明する。Embodiment A method for manufacturing a semiconductor device according to an embodiment of the present invention is described in a first embodiment.
This will be explained with figures.

まず、第１図（＆）に示す様に、ガラス、セラミック、
ポリイミドフィルム、テフロンフィルム等の転写用基板
１上に、蒸着、メッキ等により、ｉＴｏ　。First, as shown in Figure 1 (&), glass, ceramic,
iTo is deposited on a transfer substrate 1 such as a polyimide film or a Teflon film by vapor deposition, plating, or the like.

Ｏｒ等の金属膜２を形成する。その後、金属膜２上に、
テフロン、シリコーン等の樹脂との密着の悪い絶縁膜３
ｆ、形成し、後に設置する半導体素子の電極と一致する
部分の絶縁膜３をエツチング等により除去し、開孔部６
を形成する。絶縁膜３の厚みは、２〜２０μｍ程度であ
る。その後、電気メッキを行い、開孔部６の部分に突起
電極４を形成する。突起電極４は、ムｕ、Ｃｕ等であり
、厚みは、２０〜４０μｍ１寸法は６０〜１ｏｏμｍ０
である。突起電極４の材質をＣｕ　とする場合は、表面
にムＵ　メッキを行う。A metal film 2 such as Or is formed. After that, on the metal film 2,
Insulating film 3 with poor adhesion to resins such as Teflon and silicone
f. The portion of the insulating film 3 that corresponds to the electrode of the semiconductor element to be formed and installed later is removed by etching etc., and the opening 6 is removed.
form. The thickness of the insulating film 3 is approximately 2 to 20 μm. Thereafter, electroplating is performed to form protruding electrodes 4 in the openings 6. The protruding electrode 4 is made of Mu, Cu, etc., and has a thickness of 20 to 40 μm and a dimension of 60 to 10 μm.
It is. When the material of the protruding electrode 4 is Cu, the surface is plated with Cu.

次に、第１図（ｂ）に示す様に、半導体素子６の電極７
と突起電極４とを一致させ、半導体素子６を加・圧９し
、電極７と突起電極４を圧接する。この時、突起電極４
の厚みのバラツキを吸収するためには、転写用基板１は
、ポリイミドフィルム、テフロンフィルム等のやわらか
い材質を用いる。次に、半導体素子６と転写用基板１の
間隙に樹脂８を注入し、硬化する。樹脂８は、エポキシ
、ミリコーン、アクリル等であり、硬化は、光硬化、常
温硬化、加熱硬化のいずれの方法でもよい。光硬化を用
いる場合の転写基板１は、ガラス、ボリイｉドフィルム
、テフロンフィルムｓ、光ｉ透過ｔ。Next, as shown in FIG. 1(b), the electrode 7 of the semiconductor element 6 is
and the protruding electrode 4 are aligned, and the semiconductor element 6 is applied with pressure 9 to press the electrode 7 and the protruding electrode 4 into contact with each other. At this time, the protruding electrode 4
In order to absorb variations in thickness, the transfer substrate 1 is made of a soft material such as polyimide film or Teflon film. Next, resin 8 is injected into the gap between semiconductor element 6 and transfer substrate 1 and hardened. The resin 8 is epoxy, millicone, acrylic, or the like, and the resin 8 may be cured by any of photocuring, room temperature curing, and heat curing. The transfer substrate 1 in the case of using photocuring may be glass, Bolioid film, Teflon film, or light-transmissive film.

やすい材質を選択し、転写用基板１側から光照射１ｏす
る。また、光硬化を用いた場合の硬化時間は、２〜１０
秒と非常に短く、生産性の良い方法である。硬化終了後
、加圧９を取り除く。Select a material that is easy to use, and irradiate light 1o from the transfer substrate 1 side. In addition, the curing time when using photocuring is 2 to 10
It is very short, only seconds, and is a highly productive method. After curing is completed, the pressure 9 is removed.

次に、第１図（ｄ）に示す様に、転写用基板１を、絶縁
膜３と樹脂８の界面で剥がし、突起電極４を半導体素子
６の電極７側に、転写する。この時、絶縁膜３にテフロ
ン樹脂已にアクリルを用いれば、テフロンとアクリルの
接着強度は弱く、容易に剥がすことができる。また、転
写用基板１に、フィルム状のものを用いれば、第１図（
Ｃ）に示す様に、ビーリングにより容易に剥がすことが
できる・また、この時、突起電極４は、転写用基板１に
、接している部分の面積より、樹脂８と接着されている
部分の面積のほうが十分に大きい為、突起電極４は、金
属膜２との界面で剥がれる。また、金属膜２に、ｉＴｏ
やＯｒ　ｆ用いれば、Ａｕ　、　Ｃｕ等の突起電極との
密着が悪く、でらに、突起電極４の剥離性は良好になる
。また、突起電極４を半導体素子６側へ転写した、転写
用基板１は、再度、メッキすることにより、突起電極を
形成することができ、一度、金属膜２及び絶縁膜３を形
成しておくことにより、メッキをくり返すことにより、
半永久的に使用できる。このように、本発明によれば、
従来のように、半導体素子上への蒸着や、エツチングの
特殊な処理を施すことなく容易に突起電極を形成するこ
とができ、転写用基板がメッキ工程のみのくり返しで半
永久的に使用できる為、非常にコストの安いものになる
。Next, as shown in FIG. 1(d), the transfer substrate 1 is peeled off at the interface between the insulating film 3 and the resin 8, and the protruding electrodes 4 are transferred to the electrode 7 side of the semiconductor element 6. At this time, if acrylic is used instead of Teflon resin for the insulating film 3, the adhesive strength between Teflon and acrylic is weak and can be easily peeled off. Furthermore, if a film-like material is used as the transfer substrate 1, it is possible to use the transfer substrate 1 as shown in FIG.
As shown in C), it can be easily peeled off by beading. At this time, the area of the protruding electrode 4 that is bonded to the resin 8 is larger than the area of the area that is in contact with the transfer substrate 1. Since the area is sufficiently large, the protruding electrode 4 is peeled off at the interface with the metal film 2. In addition, iTo is added to the metal film 2.
If or Or f is used, the adhesion with the protruding electrodes made of Au, Cu, etc. will be poor, and the releasability of the protruding electrodes 4 will be improved. In addition, the transfer substrate 1 on which the protruding electrodes 4 have been transferred to the semiconductor element 6 side can be plated again to form the protruding electrodes, and the metal film 2 and the insulating film 3 are once formed. By repeating plating,
Can be used semi-permanently. Thus, according to the present invention,
Protruding electrodes can be easily formed without special processing such as vapor deposition or etching on semiconductor elements as in the past, and the transfer substrate can be used semi-permanently by repeating the plating process only. The cost will be extremely low.

次に、第１図ｅ）に示す様に、セラばツク、ガラス、樹
脂等よりなる配線基板１１の配線１２に、半導体素子ら
の突起電極４を加圧σにより圧接する。その後、配線基
板１１と、半導体素子６の間隙に樹脂８′を注入し硬化
させ、加圧９′ヲ取り除く。Next, as shown in FIG. 1e), the protruding electrodes 4 of the semiconductor elements are pressed against the wiring 12 of the wiring board 11 made of ceramic bag, glass, resin, etc. by applying pressure σ. Thereafter, resin 8' is injected into the gap between wiring board 11 and semiconductor element 6 and cured, and pressure 9' is removed.

この時、半導体素子６の電極７と、配線１２は、突起電
極４を介して樹脂８，８′の接着力により圧接きれた状
態となり電気的に接続する。この時、樹脂８′の注入は
、半導体素子ａｆｔ配線基板に設置してから行ったが、
設置する前に、半導体素子６又は、配線基板１１に塗布
しておいてもよい。樹脂８′は、エポキシ、シリコーン
、アクリル等であり、硬化は、光硬化、常温硬化、加熱
硬化のいずれの方法でもよい。この様に、半導体素子６
と配線基板１１との接続は、突起電極４を介して圧接で
行う為、配線１２の材質の選択の自由度が大きく、樹脂
８′に、光硬化、常温硬化タイプを用いれば、低温で配
線基板への実装が可能となり、液晶ディスプレイパネル
等、耐熱性の、低いものへの直接実装が容易に行える。At this time, the electrode 7 of the semiconductor element 6 and the wiring 12 are brought into pressure contact with each other by the adhesive force of the resins 8 and 8' via the protruding electrode 4, and are electrically connected. At this time, the resin 8' was injected after the semiconductor element was installed on the aft wiring board.
It may be applied to the semiconductor element 6 or the wiring board 11 before installation. The resin 8' is made of epoxy, silicone, acrylic, etc., and may be cured by any of photocuring, room temperature curing, and heat curing. In this way, the semiconductor element 6
Since the connection with the wiring board 11 is made by pressure contact via the protruding electrode 4, there is a great degree of freedom in selecting the material for the wiring 12. If a photo-curing or room-temperature curing type is used for the resin 8', the wiring can be made at low temperatures. It can be mounted on a substrate, and it can be easily mounted directly on something with low heat resistance, such as a liquid crystal display panel.

液晶ディスプレイパネルへの応用例を図２に示す。液晶
ディスプレイパネル１３の基板１４は通常ガラスであり
、また、配線１６は、ｉＴＯ等の透明導電膜である為、
樹脂１８′は、光硬化型を用いることにより、短時間で
かつ、常温で、半導体素子上することができる。An example of application to a liquid crystal display panel is shown in Figure 2. The substrate 14 of the liquid crystal display panel 13 is usually glass, and the wiring 16 is a transparent conductive film such as iTO.
By using a photocurable resin, the resin 18' can be applied onto the semiconductor element in a short time and at room temperature.

発明の詳細 な説明したように本発明によれば次のような効果を得る
ことができる。As described in detail, according to the present invention, the following effects can be obtained.

（１）半導体素子上に、蒸着やエツチング等の処理を施
す必要がなく、通常の半導体素子が使用できるため、コ
ストが安く、汎用性が高い〇（２）転写用基板は、メッ
キ工程をくり返すだけで、半永久的に使用できるため、
非常にコストが安くなる。(1) There is no need to perform processes such as vapor deposition or etching on the semiconductor element, and ordinary semiconductor elements can be used, resulting in low cost and high versatility. (2) The transfer substrate does not require a plating process. You can use it semi-permanently just by returning it.
The cost will be very low.

（３）配線基板との接続は、圧接により行うため、配線
基板の配線材料の選択の自由度が大きく、適用範囲が広
い。したがって、液晶ディスプレイパネル等によく用い
られる半田付けが困難なｉＴＯの配線への接続も容易に
行うことができ、半導体素子を直接、液晶ディスプレイ
パネルへ実装することができ、低コストの液晶ディスプ
レイを提供することができる。(3) Since the connection with the wiring board is made by pressure bonding, there is a large degree of freedom in selecting the wiring material of the wiring board, and the range of application is wide. Therefore, it is possible to easily connect iTO wiring, which is difficult to solder, which is often used in liquid crystal display panels, etc., and semiconductor elements can be directly mounted on liquid crystal display panels, making it possible to create low-cost liquid crystal displays. can be provided.

（４）半導体素子を配線基板に固着するときの樹脂に、
光硬化型、あるいは常温硬化型を用いることにより、液
晶ディスプレイパネル等の耐熱性の低いものへの適用が
容易となる。(4) In the resin used to fix semiconductor elements to wiring boards,
By using a photo-curing type or a room-temperature curing type, it becomes easy to apply to items with low heat resistance such as liquid crystal display panels.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例における半導体装置の製造方
法を説明するための断面図、第２図は本発明の他の実施
例方法を説明するための断面図、第３図は従来の方法を
説明するための断面図である。 １・・・・・・転写用基板、４，２４・・・・・・突起
電極、８゜８’、２８．２８’・・・・・・樹脂、６，
２８．３８・・・・・・半導体素子、１１．ａｌ・・・
・・・配線基板、１４・・・・・・基板ＯFIG. 1 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to another embodiment of the present invention, and FIG. FIG. 3 is a cross-sectional view for explaining the method. 1... Transfer substrate, 4, 24... Projection electrode, 8°8', 28.28'... Resin, 6,
28.38... Semiconductor element, 11. al...
...Wiring board, 14... Board O

Claims (2)

【特許請求の範囲】[Claims] （１）片面に導電性膜が形成されるとともに、該導電性
膜上に部分的に開孔された絶縁膜が形成された絶縁基板
上の導電性膜が露出した部分に突起電極を形成する第１
の工程と、前記突起電極に半導体素子の電極を加圧接触
させ、半導体素子と前記絶縁基板の間隙に配した樹脂を
硬化する第２の工程と、前記絶縁基板を、前記樹脂と絶
縁基板の絶縁膜との界面で剥がし、前記突起電極を半導
体素子の電極に転写する第３の工程と、前記半導体素子
の電極上の突起電極を配線基板の電極に加圧接触させ半
導体素子と配線基板の間隙に配した樹脂を硬化させるこ
とにより、半導体素子の電極と配線基板の電極とを電気
的に接続する第４の工程よりなる半導体装置の製造方法
。(1) A protruding electrode is formed on the exposed part of the conductive film on an insulating substrate which has a conductive film formed on one side and an insulating film with holes partially formed on the conductive film. 1st
a second step of bringing an electrode of a semiconductor element into pressure contact with the protruding electrode and curing the resin placed in the gap between the semiconductor element and the insulating substrate; A third step of peeling off at the interface with the insulating film and transferring the protruding electrodes to the electrodes of the semiconductor element, and contacting the protruding electrodes on the electrodes of the semiconductor element with pressure to the electrodes of the wiring board to separate the semiconductor element and the wiring board. A method for manufacturing a semiconductor device comprising a fourth step of electrically connecting an electrode of a semiconductor element and an electrode of a wiring board by curing resin placed in a gap. （２）絶縁基板が可撓性フィルムよりなる特許請求の範
囲第１項記載の半導体装置の製造方法。(2) A method for manufacturing a semiconductor device according to claim 1, wherein the insulating substrate is made of a flexible film.
JP60039183A 1985-02-28 1985-02-28 Manufacture of semiconductor device Pending JPS61198738A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60039183A JPS61198738A (en) 1985-02-28 1985-02-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60039183A JPS61198738A (en) 1985-02-28 1985-02-28 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61198738A true JPS61198738A (en) 1986-09-03

Family

ID=12545996

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60039183A Pending JPS61198738A (en) 1985-02-28 1985-02-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61198738A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5071787A (en) * 1989-03-14 1991-12-10 Kabushiki Kaisha Toshiba Semiconductor device utilizing a face-down bonding and a method for manufacturing the same
US5567648A (en) * 1994-08-29 1996-10-22 Motorola, Inc. Process for providing interconnect bumps on a bonding pad by application of a sheet of conductive discs
JPH11297750A (en) * 1998-04-08 1999-10-29 Matsushita Electron Corp Semiconductor device, manufacture thereof, and mounting of the semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5071787A (en) * 1989-03-14 1991-12-10 Kabushiki Kaisha Toshiba Semiconductor device utilizing a face-down bonding and a method for manufacturing the same
US5567648A (en) * 1994-08-29 1996-10-22 Motorola, Inc. Process for providing interconnect bumps on a bonding pad by application of a sheet of conductive discs
JPH11297750A (en) * 1998-04-08 1999-10-29 Matsushita Electron Corp Semiconductor device, manufacture thereof, and mounting of the semiconductor device

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