JPS61194744A - Semiconductor device - Google Patents

Abstract

PURPOSE:To achieve high speed operation, by spreading the low-melting metal layer all over the selected portions of the wiring layer formed with thin conductive film. CONSTITUTION:On the silicon substrate, the lower insulative film 15, the Al1 wiring layer 16, the protection film 17, the interlaminar insulating film 18, the Al2 wiring layer 19 and the passivation film 20 are formed. This passivation film 20 is subjected to etching by applying the photoresist 40 to the mask corresponding to the output signal wire 19A. On the whole surface, Cr, Cu and Au are thinly deposited in turn to form a metal film 42. A portion of this metal film is stuck to the upper surface of the output signal wire 19A, on which the photoresist forms a pattern. By applying this pattern to the mask, the metal film 42 is subjected to etching, and the lower film 32 is formed. The metal mask 44 provided with a window 46 facing to the lower film 32 is set right over the silicon substrate 1, and the soldering layer 45 is deposited on and near the lower film 32. By heating, the soldering layer 45 melts and sticks to the surface of the lower film 32 to form the low-melting metal layer 30 whose vertical cross section is a half-circle. Thus, the electric resistance of wiring can be reduced without widening the wiring layer, so that the voltage drop is restrained and the operation margin can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device with improved signal characteristics in a wiring structure.

[Background technology]

As one of the recent ultra-integrated semiconductor devices (ultra LSI),
Multiple LSIs on a silicon substrate called a mother chip
A module-type semiconductor device in which a chip is integrally mounted has been proposed. That is, a CCB in which an LSI chip is mounted on the surface of the mother chip described above by the flip-chip method.
Bumps, bonding pads for connecting external leads, and wiring layers for mutually connecting these CCB bumps and bonding pads are formed, and for example, a plurality of memory chips and logic chips are connected using the CCB bumps. By mounting this on the mother chip, it is possible to construct a semiconductor device with an extremely large memory capacity.

By the way, in this type of semiconductor device, the wiring formed on the mother chip adopts a multilayer wiring structure due to the complexity of the circuit and the wiring pattern, and usually the lower aluminum wiring layer (CAl1 wiring layer) is used. And upper aluminum wiring 1! (/1/!2 wiring layer) is formed in a three-dimensional crossing structure with an insulating film between the eyebrows interposed therebetween.

In the case of the above-mentioned two-layer aluminum wiring structure,
The output signal line connected to the bonding pad etc. is formed by the upper A12 wiring layer, and its average thickness is 2.
The line width is approximately 5 μm, and the line width is 10 to 20 μm.

For this reason, if a relatively large current flows in the output signal line, etc. mentioned above, the voltage will drop due to the resistance of the output signal line (
(drop) increases, and the output margin decreases. In order to prevent this, it is sufficient to increase the cross-sectional area of the wiring layer, and therefore it is conceivable to increase the thickness and width of the wiring layer. However, the increase in thickness is unfavorable for the flatness of the mother chip surface, and
There are limitations in terms of Al material deposition and etching (patterning) when forming wiring layers. In addition, measures to increase the width (1
00 to 150 μm) is unfavorable in terms of the integration degree of the wiring structure, and furthermore, as the width increases, the plane area increases and the capacitance (wiring capacitance) between the lower wiring layer and the mother chip substrate increases. This is unfavorable in terms of signal characteristics, such as an increase in circuit delay time (t□).

[Purpose of the invention]

The purpose of the present invention is to reduce the resistance of the wiring without increasing the width of the wiring layer, suppress the drop in signal voltage, etc., and improve the operating margin, and on the other hand, prevent the increase in wiring capacitance and reduce the delay time. It is an object of the present invention to provide a semiconductor device which can achieve improvement in signal characteristics by reducing the speed and increasing the speed.

Another object of the present invention is to achieve the above-mentioned object by significantly reducing wiring resistance only in necessary portions, while at the same time solving problems such as deterioration of flatness and accuracy caused by forming the entire wiring in a thick film. An object of the present invention is to provide a semiconductor device that can prevent such problems.

Furthermore, another object of the present invention is to provide a semiconductor device in which the width of the wiring layer can be reduced more than ever before, and the wiring structure can be further miniaturized and highly integrated.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, by integrally providing a low melting point metal layer along at least a selected part of a wiring layer formed of a thin conductive film, the resistance of the wiring layer can be lowered without increasing the width of the wiring layer. It is possible to suppress the voltage drop of the signal voltage and improve the operating margin, and on the other hand, prevent the increase in wiring capacitance, reduce delay time, and achieve faster operation.

Since the low melting point metal layer is formed only on the required wiring layer, there is no need to increase the thickness of the entire wiring layer, which simplifies the manufacturing process such as deposition and etching of the wiring layer material, and improves the accuracy of the wiring layer. It doesn't lower it either.

The wiring layer is applied to the uppermost wiring layer of a multilayer wiring structure of two or more layers, an upper layer and a lower layer, and therefore does not impede the flatness of the multilayer wiring structure.

The wiring layer is constructed as a wiring structure of at least two layers on a mother chip made of a silicon substrate, and a low melting point metal layer is integrally formed with the wiring layer formed as an output signal line in a part of the upper wiring layer.

Solder can be used for the low melting point metal layer, and the surface tension of the solder itself allows the metal layer to be bulged and integrally placed on the wiring layer.

〔Example〕

1 and 2 show an embodiment in which the present invention is applied to a multi-chip LSI as a RAM module. In particular, FIGS. 3 and 3 show enlarged cross-sectional views along lines AA and BB of the RAM module shown in FIG. It is shown in Figure 4.

The multi-chip LSII has a RAM module 10 built into a ceramic package base 2, and is connected to an internal lead 4 connected to an external lead 3 of the package base 2 using a wire 5. The RAM module 10 is configured to be electrically connectable to the outside. It goes without saying that a cap (not shown) may be attached to the ceramic base 2 to package the RAM module 10 in a hermetically sealed manner.

The RAM module 10 has a plurality of RAM memory chips 12 and logic circuit chips 13 on the surface of a mother chip 11.
are mounted by the flip-chip method and are interconnected by a wiring structure provided on the mother chip 11, forming a so-called hybrid semiconductor device.

The mother chip 11 has C on the surface of the silicon substrate 14.
A thin base insulating film 15 such as VD5 i O Thin plasma SiN protective film 17
is covered with.

Furthermore, on top of that, a glabellar insulating film 18 of sputtered Si0g, etc.
is formed relatively thickly, and a second wiring layer as an upper wiring layer is formed thereon.
Aluminum wiring layer (hereinafter referred to as AJ2 wiring layer) 19
are formed in the required pattern. Furthermore, a passivation film 20 such as a silane film is formed on this A12 wiring layer 19 to cover the A#2' wiring layer 19.

The All wiring layer 16 has a thickness of about 2 μm and a width of about 10 μm.
μm, and the thickness of the Aβ2 wiring layer 19 is 2.5 μm1.
Wiring is performed with a width of about 20 to 50 μm, and a known through hole (not shown) is formed at the intersection of the /411 wiring layer 16 and the Af2 wiring layer 19 as necessary to connect them to each other. ing.

CCB bumps 21 are formed on a portion of the A and G2 wiring layers 19 from the inner end to directly connect with each chip 12.13, and the package is formed at a peripheral position of the silicon substrate 14 from the outer end. A bonding pad 22 for connecting the wire 5 to the base 1 is formed. The CCB bump 21 has a window 23 in the passivation film 20 on the AJ2 wiring layer 19, and Cr, Cu is formed in the window 23.

A BLM electrode 24 made of a three-layer film of Au is formed, and furthermore, solder 25 is formed in a hemispherical shape on this BLM electrode 24. In addition, the bonding pad 22 opens a relatively large window 26 in the passivation film 20, and the A12 wiring layer 19
The structure has a part of the surface exposed.

Furthermore, among the 1st and 12th wiring layers 19, at least a part of the wiring layer through which a relatively large current flows, such as an output signal line, has an upper surface as shown in FIGS. 3 and 4. A low melting point metal layer 30 is integrally provided. That is, in this example, the low melting point metal layer 30 is integrally provided along a part of the output signal line 19A of the AJ2 wiring layer 19. The passivation film 20 on the intermediate straight portion of the output signal line 19A is removed by etching to a width slightly smaller than the wiring layer width of the output signal line 19A to form a window 31. A base film 32 made of three layers of Au is formed along the window 31, in other words, along the output signal line 19A and in close contact with the upper surface of the output signal line 19A. Then, on the base film 32 formed in the shape of a pier, a low melting point metal is heaped up in a semicircular cross section and along its length to form a low melting point metal layer 30, and the output signal line 19A is
It is integrated into. As a result, the substantial cross-sectional area of the output signal line 19A including the low melting point metal layer 30 is significantly increased. Note that in this example, solder is used as the low melting point metal.

The method for forming the low melting point metal 1130 is generally known CCB.
Although the same formation method as the bump may be used, FIGS. 5(A) to (E)
).

First, as shown in the same figure (A), a base insulating film (CVDS iOx) 15 and AI! are formed on a silicon substrate 14. 1 wiring layer 1
6. After forming a protective film (plasma 5iN) 17, an insulating film between eyebrows (sputter 5iot) 18, an A12 wiring layer 19, and a passivation film (silane 1i) 20 by a conventional method,
A photoresist 40 having an opening corresponding to a relative position of the output signal line 19A, which is a part of the wiring layer 19, is patterned on the upper surface, and using this as a mask, the passivation film 20 is formed.
etching. As a result, a part of the upper surface of the output signal line 19A is exposed through the window 31 of the passivation film 20.

Next, Cr and Cu are applied to the entire surface as shown in the same figure (B).

A three-layer metal film 42 is formed by sequentially depositing thin layers of Au, and a portion of the metal film 42 is brought into close contact with the upper surface of the output signal line 19A. On top of that, a photoresist 43 is patterned again with a slightly larger opening than before, and this is used as a mask to form the metal film 43.
Etch 2.

As a result, a base film 32 having a width substantially equal to the width of the output signal line 19A is formed, as shown in FIG.

Next, a metal mask 44 with a window 46 formed in a portion approximately corresponding to the base film 32 is set directly above the silicon substrate 14, and as shown in FIG. A solder layer 45 is deposited on the base film 32 and its vicinity. By heating this solder layer 45 to its melting point, the solder layer 45 is melted and fixed to the base film 32 in a semicircular cross section as shown in FIG. Melting point metal layer 30 can be completed.

Therefore, according to this configuration, the cross-sectional structure of the output signal line 19A includes the base film 32 and the low melting point metal layer 30 in addition to the cross-sectional area of the original A12 wiring layer 19 as shown in FIGS.
, and the cross-sectional area is significantly increased. Therefore, without increasing the thickness or width of the A12 wiring layer 19, the output signal line 19A of this example
Even when the wires are relatively long on the mother chip 11 as shown in FIG. 1, the resistance of the wires can be significantly reduced. Thereby, the voltage drop of the current circulating in the output signal line 19A can be suppressed, and the operating margin can be improved. Also, since there is no need to increase the line width of the output signal line 19A, /1
It is possible to prevent an increase in the capacitance between the 111 wiring 6 and the silicon substrate 14, suppress a decrease in circuit delay time, and achieve high speed.

Furthermore, the low melting point metal layer 30 allows the width dimension to be reduced compared to conventional AJ wiring, which is effective for miniaturization and high integration of wiring layers.

Further, the rating of the output signal vA19A can be increased by the low melting point metal layer 30.

On the other hand, since solder is used for the low melting point metal layer 30 in the previous example, it can be manufactured at the same time as the CCB bump 20.
It is only necessary to change the mask pattern used in the conventional process, and it can be formed extremely easily. Note that since the cross-sectional area of the low-melting point metal layer 30 depends on the amount of solder deposited in the step of FIG. 5(D), the deposited thickness and width may be appropriately controlled.

〔effect〕

(1) Since the low melting point metal layer is integrally formed on the conductive film as the wiring layer, the width of the wiring layer does not need to be increased (
The cross-sectional area can be increased, wiring resistance can be reduced, voltage drop can be suppressed, and operating margin can be improved.

(2) By providing a low melting point metal layer, the wiring capacitance with the underlying layer can be reduced, circuit delay can be suppressed, and high speed can be achieved.

(3) By providing a low melting point metal layer to reduce resistance, it is also possible to reduce the wiring layer width compared to conventional methods.
This makes it possible to achieve finer wiring layers and higher integration.

(4) By providing a low melting point metal layer, the mechanical strength of the wiring layer can be improved and the rating of the wiring layer can be improved.

(5) By forming a low melting point metal layer on signal lines such as output, it is possible to prevent signal voltage reduction and delay, and improve signal characteristics.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, a low melting point metal layer can be similarly applied to a portion of wiring other than the output signal line where a large current flows or a portion of the wiring is long. Moreover, a metal other than solder may be used as the low melting point metal. Furthermore, various methods such as a method of depositing the low melting point metal layer directly on the wiring layer using a photoresist film as a mask, a lift-off method, etc. can be used to manufacture the low melting point metal layer. In this case, the base film may not be necessary depending on the material of the low melting point metal and the manufacturing method.

[Application field]

In the above explanation, the invention made by the present inventor was mainly applied to two-layer wiring of a mother chip in a multi-chip semiconductor device, which is the field of application in which the invention was made, but the invention is not limited thereto. ,
For example, it can be applied to all semiconductor devices that require fine wiring and have an IN or multilayer wiring structure that requires low wiring resistance and low capacitance.

[Brief explanation of the drawing]

FIG. 1 is a plan view of an embodiment in which the present invention is applied to a RAM module of a multi-chip LSI, FIG. 2 is an enlarged plan view of the RAM module, and FIG. 3 is an enlarged sectional view taken along line AA in FIG. FIG. 4 is an enlarged sectional view taken along line BB in FIG. 2, and FIGS. 5(A) to 5(E) are sectional views corresponding to FIG. 4 for explaining the manufacturing method. 1...Multi-chip LSI, 2...Puff cage base, 3...External lead-out lead, 4...Internal lead, 5
...Wire, 10...RAM module, 11...
・Mother chip, 12...RAM memory chip, 13
...Logic circuit chip, 14...Silicon substrate, 15
...Base insulating film, 16.../It'l wiring layer, 17
...protective film, 18...interlayer insulating film, 19...AI
! 2 wiring layer, 19A...output signal line, 20...passivation film, 21...CCB bump, 22...
Ponding pad, 30...Low melting point metal layer, 32.
... Base film. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] 1. A wiring structure in which a wiring layer is formed of a thin conductive film, wherein a low melting point metal layer such as solder is integrally provided on the upper surface of the conductive film of at least selected wiring layers. . A semiconductor device characterized in that the substantial cross-sectional area of the wiring layer is increased. 2. The semiconductor device according to claim 1, wherein the low melting point metal layer is formed by heaping the low melting point metal onto the wiring layer through a window formed in an insulating film provided above the wiring layer and integrating it. 3. The low melting point metal layer is obtained by forming a base metal film through the window of the insulating film on the wiring layer, and then raising the low melting point metal on top of it by using its own surface tension. The semiconductor device described. 4. Forming a two-layer interconnection layer insulated from each other by an interlayer insulating film on the surface of a mother chip made of a silicon substrate, and integrally forming a low-melting point metal layer on the upper surface of at least a portion of the upper interconnection layer. A semiconductor device according to any one of claims 1 to 3. 5. The semiconductor device according to claim 4, wherein a low melting point metal layer is integrally formed on a wiring layer serving as an output signal line through which a relatively large current flows.