JPH04297042A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04297042A JPH04297042A JP3001333A JP133391A JPH04297042A JP H04297042 A JPH04297042 A JP H04297042A JP 3001333 A JP3001333 A JP 3001333A JP 133391 A JP133391 A JP 133391A JP H04297042 A JPH04297042 A JP H04297042A
- Authority
- JP
- Japan
- Prior art keywords
- film
- aluminum
- bonding
- thickness
- electrode wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 18
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910000676 Si alloy Inorganic materials 0.000 claims abstract description 9
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 claims abstract description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052802 copper Inorganic materials 0.000 claims abstract description 8
- 239000010949 copper Substances 0.000 claims abstract description 8
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 4
- 229910000838 Al alloy Inorganic materials 0.000 claims description 3
- -1 aluminum-silicon- copper Chemical compound 0.000 abstract description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 6
- 229910000881 Cu alloy Inorganic materials 0.000 abstract description 5
- 230000005012 migration Effects 0.000 abstract description 4
- 238000013508 migration Methods 0.000 abstract description 4
- 230000004888 barrier function Effects 0.000 abstract description 3
- 229910052751 metal Inorganic materials 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 3
- 239000011347 resin Substances 0.000 abstract description 3
- 229920005989 resin Polymers 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 2
- 238000007789 sealing Methods 0.000 abstract description 2
- 230000010485 coping Effects 0.000 abstract 1
- 238000004299 exfoliation Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 6
- 230000007423 decrease Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 239000005360 phosphosilicate glass Substances 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
- H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
- H01L2224/48624—Aluminium (Al) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
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- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
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- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
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- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は半導体装置に関し、特に
ボンディング電極の構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to the structure of bonding electrodes.
【０００２】0002
【従来の技術】従来の半導体装置のボンディング電極は
、図３（ａ），（ｂ）に示すように、半導体チップ１１
の一主面に、フィールド酸化膜１２及び、半導体素子領
域１３が形成され、層間絶縁膜１４を介して内部電極配
線２０及び外部電極配線２１をボンディング電極１８を
含めて形成し、リンシリケートガラス膜、シリコンナイ
トライド膜等の保護用絶縁膜１９で覆った後、ボンディ
ング電極１８部のみをエッチングして露出させた構造と
なっていた。従来、内部電極配線２０、外部電極配線２
１及びボンディング電極１８はＬＳＩ電極の配線として
最も一般的に使用されているアルミニウム膜、又はアル
ミニウム−シリコン合金膜により形成されていたが、近
年、ＬＳＩの高密度、高集積化が進み、パターン寸法の
微細化に伴い、電極配線においてはエレクトロマイグレ
ーション及び、ストレスマイグレーション寿命の減少が
著しく、その対策として配線膜への銅の添加が行われて
おり、例えばアルミニウム−シリコン銅合金膜が、電極
配線として使用されている。2. Description of the Related Art As shown in FIGS.
A field oxide film 12 and a semiconductor element region 13 are formed on one main surface, internal electrode wiring 20 and external electrode wiring 21 including bonding electrodes 18 are formed via an interlayer insulating film 14, and a phosphosilicate glass film is formed. After covering with a protective insulating film 19 such as a silicon nitride film, only the bonding electrode 18 portion was exposed by etching. Conventionally, internal electrode wiring 20, external electrode wiring 2
1 and the bonding electrode 18 were formed of an aluminum film or an aluminum-silicon alloy film, which is the most commonly used wiring for LSI electrodes, but in recent years, as LSIs have become more dense and highly integrated, pattern dimensions have become smaller. With the miniaturization of electrode wiring, electromigration and stress migration lifespan are significantly reduced in electrode wiring, and as a countermeasure, copper is added to wiring films.For example, aluminum-silicon copper alloy films are used as electrode wiring. It is used.
【０００３】0003
【発明が解決しようとする課題】一般的なボンディング
電極とリードとのワイヤーボンディング方法としては、
金線を用いる場合の熱圧着ボンディング、アルミニウム
線を用いる場合の超音波ボンディングが上げられる。熱
圧着ボンディングは、先端を放電などにより溶融し球状
にした金線をボンディング電極へ接着するが、この接着
構造は金−アルミニウム拡散合金による接着である。[Problems to be Solved by the Invention] A general wire bonding method between a bonding electrode and a lead is as follows.
Examples include thermocompression bonding using gold wire and ultrasonic bonding using aluminum wire. In thermocompression bonding, a spherical gold wire whose tip is melted by electrical discharge or the like is bonded to a bonding electrode, and this bonding structure is based on a gold-aluminum diffusion alloy.
【０００４】アルミニウムは銅を添加することにより、
金との拡散係数が低下する為、必然的に金線との接合強
度は低下する。よって、ボンディング電極をアルミニウ
ム−シリコン−銅合金膜とした場合、金線ボンディング
初期段階での金−電極配線の界面剥離、及び、樹脂封止
時の応力による界面剥離等が発生する問題がある。[0004] By adding copper to aluminum,
Since the diffusion coefficient with gold decreases, the bonding strength with the gold wire inevitably decreases. Therefore, when the bonding electrode is made of an aluminum-silicon-copper alloy film, there are problems such as peeling of the gold-electrode wiring interface at the initial stage of gold wire bonding and peeling of the interface due to stress during resin sealing.
【０００５】また、アルミニウムに銅を添加することに
より膜硬度が高くなり、アルミニウム線の超音波ボンデ
ィングの際、アルミニウム線の超音波による変形量を制
御することが難しく、しかも、銅を添加しないボンディ
ング電極にボンディングすることにより、アルミニウム
線の変形量は増加する傾向にあり、アルミニウム線の破
断強度の低下を招く問題がある。[0005]Additionally, adding copper to aluminum increases the film hardness, making it difficult to control the amount of deformation of the aluminum wire due to ultrasonic waves during ultrasonic bonding of the aluminum wire. By bonding to the electrode, the amount of deformation of the aluminum wire tends to increase, resulting in a problem that the breaking strength of the aluminum wire decreases.
【０００６】[0006]
【課題を解決するための手段】本発明は、銅を成分とし
て含むアルミニウム合金の電極配線を有する半導体装置
において、前記電極配線に接続されるボンディング電極
はその最上層にアルミニウム膜もしくはアルミニウム−
シリコン合金膜を有する多層膜であるというものである
。Means for Solving the Problems The present invention provides a semiconductor device having an electrode wiring made of an aluminum alloy containing copper as a component, in which a bonding electrode connected to the electrode wiring has an aluminum film or an aluminum layer on the uppermost layer.
It is a multilayer film including a silicon alloy film.
【０００７】[0007]
【実施例】次に本発明について図面を参照して説明する
。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.
【０００８】図１（ａ）は本発明の第１の実施例の半導
体チップコーナー部の平面図、図１（ｂ）は図１（ａ）
のＸ−Ｘ線断面図である。まず、半導体チップ１１の一
主面に、例えば膜厚１．０μｍのフィールド酸化膜１２
、及び半導体素子領域１３を形成し、次に、例えば膜厚
０．９μｍの多層膜の内部電極配線１６及び多層膜の外
部電極配線１７をボンディング電極１８を含めて形成す
る。このとき、前述の多層膜は、例えば膜厚０．１μｍ
のバリヤーメタルとして使用されるタングステンシリサ
イド膜２４，各種マイグレーション対策の為銅を添加し
た、例えば膜厚０．４μｍのアルミニウム−シリコン−
銅合金膜２５，及び例えば膜厚０．４μｍのアルミニウ
ム−シリコン合金膜２６から成り、連続スパッタにより
形成されるものである。次に、例えば膜厚１．０μｍの
リンシリケートガラス膜、シリコンナイトライド膜など
の保護用絶縁膜１９で覆った後、ボンディング電極１８
部のみをエッチングして露出させることにより所望の構
造を得るものである。FIG. 1(a) is a plan view of a corner portion of a semiconductor chip according to a first embodiment of the present invention, and FIG. 1(b) is a plan view of a corner portion of a semiconductor chip according to a first embodiment of the present invention.
FIG. First, a field oxide film 12 with a thickness of 1.0 μm, for example, is formed on one main surface of the semiconductor chip 11.
, and semiconductor element region 13 are formed, and then, for example, internal electrode wiring 16 of a multilayer film and external electrode wiring 17 of a multilayer film, including bonding electrodes 18, are formed with a film thickness of 0.9 μm. At this time, the multilayer film described above has a thickness of, for example, 0.1 μm.
A tungsten silicide film 24 used as a barrier metal, for example, an aluminum-silicon film with a thickness of 0.4 μm to which copper is added for various migration countermeasures.
It consists of a copper alloy film 25 and an aluminum-silicon alloy film 26 with a thickness of, for example, 0.4 μm, and is formed by continuous sputtering. Next, the bonding electrode 18 is covered with a protective insulating film 19 such as a phosphosilicate glass film or a silicon nitride film with a film thickness of 1.0 μm, for example.
A desired structure is obtained by etching and exposing only the portion.
【０００９】本実施例のごとく、半導体装置のボンディ
ング電極１８を多層膜により形成し、ボンディングワイ
ヤーがボンディングされる最上層をアルミニウム−シリ
コン合金膜にすることにより、各種マイグレーション対
策として銅を添加したアルミニウム膜を電極配線に使用
しても従来の様な金線ボンディングにおける金−ボンデ
ィング電極界面剥離による不良発生や、アルミニウム線
ボンディングにおける、ワイヤー破断強度の低下を防止
することができる。アルミニウム線の変形量は約１５％
少なくなり、ワイヤー破断強度は約２０％大きくできる
のである。As in this embodiment, the bonding electrode 18 of the semiconductor device is formed of a multilayer film, and the uppermost layer to which the bonding wire is bonded is made of an aluminum-silicon alloy film. Even when the film is used for electrode wiring, it is possible to prevent defects caused by peeling at the gold-bonding electrode interface in conventional gold wire bonding and a decrease in wire breaking strength in aluminum wire bonding. The amount of deformation of aluminum wire is approximately 15%
As a result, the wire breaking strength can be increased by about 20%.
【００１０】図２（ａ）は本発明の第２の実施例の半導
体チップコーナー部の平面図、図２（ｂ）は図２（ａ）
のＸ−Ｘ線断面図である。この実施例は、２層配線構造
の半導体装置に本発明を適用したものである。FIG. 2(a) is a plan view of a corner portion of a semiconductor chip according to a second embodiment of the present invention, and FIG. 2(b) is a plan view of a corner portion of a semiconductor chip according to a second embodiment of the present invention.
FIG. In this embodiment, the present invention is applied to a semiconductor device having a two-layer wiring structure.
【００１１】まず、半導体チップ１１の一主面に、例え
ば膜厚１．０μｍのフィールド酸化膜１２、及び半導体
素子領域１３を形成し、次に、例えば膜厚１．０μｍの
リンシリケートガラス膜などの層間絶縁膜１４を介して
、各種マイグレーション対策の為銅を添加した例えば膜
厚０．５μｍのアルミニウム−シリコン−銅合金膜２７
及び、例えば膜厚０．１μｍのバリヤーメタルとして使
用されるタングステンシリサイド膜２４から成る低層次
の内部電極配線２０を形成する。次に、例えば膜厚１．
０μｍのリンシリケートガラス膜、シリコンナイトライ
ド膜などの保護用絶縁膜１９で覆った後、ボンディング
電極１８部のみをエッチングして露出させることにより
所望の構造を得るものである。First, a field oxide film 12 with a thickness of, for example, 1.0 μm and a semiconductor element region 13 are formed on one main surface of the semiconductor chip 11, and then a phosphosilicate glass film or the like with a thickness of, for example, 1.0 μm is formed. For example, an aluminum-silicon-copper alloy film 27 with a thickness of 0.5 μm to which copper is added for various migration countermeasures is inserted through the interlayer insulating film 14 of
Then, a low-level internal electrode wiring 20 is formed, which is made of, for example, a tungsten silicide film 24 having a film thickness of 0.1 μm and used as a barrier metal. Next, for example, the film thickness is 1.
After covering with a protective insulating film 19 such as a 0 μm phosphosilicate glass film or silicon nitride film, only the bonding electrode 18 portion is exposed by etching to obtain a desired structure.
【００１２】本実施例においても、第１の実施例で説明
した通り、同様の効果が得られる。[0012] In this embodiment as well, similar effects can be obtained as explained in the first embodiment.
【００１３】以上の実施例においてアルミニウム−シリ
コン合金膜の代りにアルミニウム膜を使用してもよい。In the above embodiments, an aluminum film may be used instead of the aluminum-silicon alloy film.
【００１４】[0014]
【発明の効果】以上説明したように本発明はボンディン
グ電極を複数の導体膜を積層した多層膜により形成し、
ボンディングワイヤーがボンディングされる最上層をア
ルミニウム膜もしくはアルミニウム−シリコン合金膜と
することにより、金線ボンディングにおいては良好な金
−アルミニウム合金膜をボンディング線とボンディング
電極界面に形成し、強固な接着状態を得ることができ、
これにより従来散発していた樹脂封入時の金線剥離不良
が大幅に低減できる。また、アルミニウム線ボンディン
グにおいては、アルミニウム線変形量を約１５％縮小で
き、これにより、ワイヤー破断強度は約２０％大きくな
るという効果を有する。[Effects of the Invention] As explained above, the present invention forms a bonding electrode with a multilayer film in which a plurality of conductor films are laminated.
By using an aluminum film or an aluminum-silicon alloy film as the top layer to which the bonding wire is bonded, a good gold-aluminum alloy film is formed at the interface between the bonding wire and the bonding electrode in gold wire bonding, creating a strong bonding state. you can get
As a result, defects in gold wire peeling during resin encapsulation, which have conventionally occurred sporadically, can be significantly reduced. Furthermore, in aluminum wire bonding, the amount of aluminum wire deformation can be reduced by about 15%, which has the effect of increasing the wire breaking strength by about 20%.
【００１５】特に近年は、半導体装置の端子数が増大す
る傾向にありボンディング電極サイズをほぼ５０μｍ□
程度に縮小する必要があり、ボンディング線とボンディ
ング電極の接合面積が小さくなるため、本発明は特に有
効である。[0015] Particularly in recent years, the number of terminals in semiconductor devices has tended to increase, and the bonding electrode size has been reduced to approximately 50 μm□.
The present invention is particularly effective because the bonding area between the bonding line and the bonding electrode is reduced.
【図１】本発明の第１の実施例を示す半導体チップの平
面図（図１（ａ））および断面図（図１（ｂ））である
。FIG. 1 is a plan view (FIG. 1(a)) and a cross-sectional view (FIG. 1(b)) of a semiconductor chip showing a first embodiment of the present invention.
【図２】本発明の第２の実施例を示す半導体チップの平
面図（図２（ａ））および断面図（図２（ｂ））である
。FIG. 2 is a plan view (FIG. 2(a)) and a cross-sectional view (FIG. 2(b)) of a semiconductor chip showing a second embodiment of the present invention.
【図３】従来例を示す半導体チップの平面図（図３（ａ
））および断面図（図３（ｂ））である。[Fig. 3] A plan view of a semiconductor chip showing a conventional example (Fig. 3(a)
)) and a cross-sectional view (FIG. 3(b)).
１１ 半導体チップ １２ フィールド酸化膜 １３ 半導体素子領域 １４ 層間絶縁膜 １５ コンタクトホール １６ 内部電極配線 １７ 外部電極配線 １８ ボンディング電極 １９ 保護用絶縁膜 ２０ 低層次の内部電極配線 ２１ 外部電極配線 ２２ スルーホール ２３ 第２の層間絶縁膜 11 Semiconductor chip 12 Field oxide film 13 Semiconductor element area 14 Interlayer insulation film 15 Contact hole 16 Internal electrode wiring 17 External electrode wiring 18 Bonding electrode 19 Protective insulating film 20 Low layer next internal electrode wiring 21 External electrode wiring 22 Through hole 23 Second interlayer insulating film
Claims (2)
の電極配線を有する半導体装置において、前記電極配線
に接続されるボンディング電極はその最上層にアルミニ
ウム膜もしくはアルミニウム−シリコン合金膜を有する
多層膜であることを特徴とする半導体装置。1. In a semiconductor device having an electrode wiring made of an aluminum alloy containing copper as a component, a bonding electrode connected to the electrode wiring is a multilayer film having an aluminum film or an aluminum-silicon alloy film as its uppermost layer. A semiconductor device characterized by:
イド膜を有している請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the multilayer film has a tungsten silicide film at the bottom layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3001333A JPH04297042A (en) | 1991-01-10 | 1991-01-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3001333A JPH04297042A (en) | 1991-01-10 | 1991-01-10 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04297042A true JPH04297042A (en) | 1992-10-21 |
Family
ID=11498574
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3001333A Pending JPH04297042A (en) | 1991-01-10 | 1991-01-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04297042A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8044521B2 (en) | 2005-02-22 | 2011-10-25 | Renesas Electronics Corporation | Semiconductor device |
-
1991
- 1991-01-10 JP JP3001333A patent/JPH04297042A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8044521B2 (en) | 2005-02-22 | 2011-10-25 | Renesas Electronics Corporation | Semiconductor device |
| US8587133B2 (en) | 2005-02-22 | 2013-11-19 | Renesas Electronics Corporation | Semiconductor device |
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