JPS6118219B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an arithmetic device for data with a decimal point. Generally, when adding or subtracting data with different lengths after the decimal point, digits are aligned prior to the operation, and furthermore, digits are aligned in accordance with the format of the result storage location when storing the results of the operation. For example, in the method described in Japanese Patent Publication No. 44-18345 ``Automatic decimal point alignment method'', the relative relationship of the decimal point positions of two data to be calculated is checked, and one bit of the data of both data is checked. A method is described in which digits are aligned by repeating a shift operation to the left or right. That is, digit alignment is achieved by repeating shift operations, but this is normally done using other devices before and after the operation, which has the disadvantage of increasing the number of instruction steps. Furthermore, this method of performing digit alignment based on the relative relationship of the decimal point positions of the data has the disadvantage that the digit alignment process cannot be started until the two pieces of data to be calculated are prepared. In addition, the program may specify operations such as rounding off the calculation result, special operations when overflow occurs, operations to insert a blank code into the leading zero part, etc. The number of steps increases. SUMMARY OF THE INVENTION An object of the present invention is to provide a device that automatically performs digit alignment in calculations of data with decimal points. Another object of the present invention is to provide a device that automatically performs digit alignment according to the format of the intended storage location when storing the calculation result of data with a decimal point. Another object of the present invention is to automatically process operations such as rounding according to program specifications, control when overflow occurs, and padding of leading zeros with blank codes when storing calculation results of data with decimal points. The goal is to provide equipment. That is, the present invention provides means for displaying the position of the decimal point for each piece of data in calculations of data with a decimal point, means for determining the operation to be performed according to the result of the calculation, and an accumulator with a decimal point. digit alignment means for loading data into the decimal point accumulator according to the decimal point position given by the decimal point position display means;
a decimal point position given by an arithmetic device that calculates the data whose digits have been aligned by the digit alignment means, and a means for displaying the decimal point position when storing the arithmetic result by the arithmetic device in a result storage location; This is an arithmetic device comprising means for storing the same and means for performing an operation specified by means for specifying an operation to be performed in accordance with the result of the operation. Next, one embodiment of the present invention will be described using the drawings. FIG. 1 represents the format of the instructions and descriptors of the embodiment. The OS (operand syllable) refers to a descriptor, and the descriptor includes the operand address and the length of the data after the decimal point. This example is an instruction that adds the data in the addresses pointed to by OS ₁ and OS ₂ and stores the result in the address pointed to by OS ₃ . The instruction control field is a field that specifies data modification when storing the result of an operation. RND is a bit that instructs rounding, and BWZ (Blank When Zere) is
This bit instructs to fill the leading zero with a blank code. Figure 2 shows an example of the data format, which is a decimal 4-digit zone format. The position of each decimal point is in the descriptor.
Specified by the SCALE field. In the figure, Z represents the zone, D represents the data, S represents the code, and P represents the
Indicates the decimal point position given by SCALE. In the following embodiment, the maximum value of data will be explained as 4 decimal digits. FIG. 3 is a block diagram of the embodiment. Since the circuitry for controlling the data flow can be of a conventional type, only the components and their interrelationships necessary for explaining the present invention are shown for the sake of simplicity. In FIG. 3, data is read into a 4-byte memory read register 301 and the decimal length of the data is read into a scale register 302. The data is converted by the conversion circuit 303 into a form suitable for calculation, and after the code is extracted,
The digits are adjusted according to the contents of the scale register 302. The sign of the first operand is the holding circuit 3
08, and the function determining circuit 304 instructs the arithmetic unit 307 to perform addition or subtraction based on the contents thereof, the sign of the second operand, and the operation signal specified by the instruction. The digit-aligned data is loaded in the order of the first operand and second operand into registers 305 and 306, which have a decimal point in the center of the eight digits, and is loaded into the eight-digit decimal adder/subtractor 30.
7 executes the operation and the results are set in registers 305 and 306. When an overflow occurs as a result of the calculation, it is displayed on the overflow display circuit 315 and the entire calculation ends. If it is necessary to take a complement, the constant circuit 313 and the arithmetic unit 307 are used to perform the complement, and at the same time, the sign-inverted signal holding circuit 314 is set. When rounding is instructed by a command, the rounding instruction circuit 312, constant circuit 313, and arithmetic unit 307 are used to execute the rounding operation. The result of the operation is sent from the register 305 to the conversion circuit 309, and the third
Four digits are taken out according to the length of the operand after the decimal point, edited into a result storage format, and set in the result storage register 311. Below, the operation of the circuit shown in FIG. 3 will be explained in more detail using the example data shown in FIG. First, the first operand data is read into the register 301, and its decimal length is set in the scale register 302. Data in register 301 is sent to conversion circuit 303 via bus 320. The sign of the first operand data extracted by the conversion circuit 303 is set in the holding circuit 308 via the signal line 325. Conversion circuit 303
further removes the zones of data and returns D ₁₁ , D ₁₂ ,
Convert to 4-digit pack format data of D ₁₃ and D ₁₄ .
Since this conversion circuit is the same as the conventional method, a detailed explanation of the inside of the circuit will be omitted. The converted data is shifted from scale register 302 by the number of decimal places given via bus 321 and set into register 305 via bus 322. Register 305 is a first operand data register with a decimal point in the center, and in the example of FIG. 2, it is set to 00D ₁₁ D ₁₂ · D ₁₃ D ₁₄ 00 according to the scale value 2 as shown in FIG. 3. Next, the second operand data is in the register 301.
, and its decimal length is read into the scale register 302. The contents of register 301 are sent to conversion circuit 303 via bus 320, and its code is transferred to function circuit 304 via signal line 325. The function circuit 304 is connected to the signal line 3 from the code holding circuit 308.
the sign of the first operand sent via 26;
Either addition or subtraction is determined and held based on the addition or subtraction signal given in the operation part of the instruction and the sign of the second operand sent via the signal line 325. That is, addition is held during addition with the same sign and subtraction with the opposite sign, and subtraction is held during addition with the same sign and subtraction with the same sign.
Sign inversion circuit 314 and overflow display circuit 315
is applied to Similar to the first operand data, the conversion circuit 303 shifts the data by the number of digits given by the scale register 302 and sets the second operand data in the register 306 via the bus 322. In the example of FIG. 2, the contents of register 306 are 000D ₂₁ ·D ₂₂ D ₂₃ D ₂₄ 0. The data set in the registers 305 and 306 are sent to the arithmetic unit via buses 323 and 324, respectively, where addition or subtraction is performed according to the signal applied to the terminal A/S, and the data is sent to the register via the bus 322. 305 and 306. If no overflow occurs as a result of the calculation, it means that the correct calculation result has been set in the register 305.
When an overflow occurs as a result of an operation, the processing is different for addition and subtraction. The overflow of the operation result is the OVF signal of the decimal adder/subtractor 307 in FIG. If an overflow occurs as a result of the addition, the overflow is displayed on the overflow display circuit 315, and the calculation result becomes invalid. If an overflow occurs as a result of subtraction, the following operations are performed to complement the operation result. That is, when the constant circuit 313 is given a subtraction instruction signal via the signal line 327 and an overflow signal via the signal line 330, the constant generation circuit 313 gives a zero value to the register 305 via the bus 322, and at the same time 307 to instruct subtraction. (This instruction method is not shown.) The arithmetic unit 307 is the register 3
The operation result set in the register 306 is subtracted from the zero set in the register 306, and the result is transferred to the bus 3.
22 to the register 305. This result is the complement of the previous operation result. In parallel with the above operation, a subtraction signal and an overflow signal are also sent to the sign inversion circuit 314, which holds that the sign should be inverted. After the above-mentioned work is completed, if rounding is instructed by the command, the following operation is executed.
That is, at this time, the constant circuit 313 includes the instruction circuit 3
12, a rounding instruction is given via a signal line 329, and a decimal length of the third operand is given via a bus 321. The constant circuit sets the value 5 one digit to the right of the length after the decimal point, and connects the bus 322.
At the same time, the value is set in the register 305 via the arithmetic unit 307. The addition result is transferred to register 305 via bus 322. In the example of FIG. 2, the length after the decimal point of the third operand is 2, so the constant circuit 313 generates 0000.0050, which is added to the previous operation result. Assuming that additions of the same sign are performed, the entire operation is as follows.

[Table] When a correct calculation result is stored in the register 305 through the above operations, the result is sent to the conversion circuit 309 via the bus 323. Conversion circuit 309
extracts only four valid digits by a shift operation according to the third operand decimal length sent via bus 321. If an overflow occurs here, the overflow is displayed on the overflow display circuit 315 via the signal line 334. The sign determination circuit 310 determines the sign of the first operand provided via the signal line 328 and the signal 33.
The sign of the operation result is determined according to the presence or absence of sign inversion given through the signal line 332, and the sign is instructed to the conversion circuit 309 through the signal line 332. Conversion circuit 3
09 edits valid calculation results into zone format,
The result is transferred to the result holding register 311 via the bus 333. Although not shown, when a command instructs blank code filling, the conversion circuit 30
9 generates a blank code at the zero position at the beginning of the data and writes it to the register 31 instead of generating a zone.
Set to 1. Although a simple example has been described above to explain the operation of the present invention, this is just an example and does not limit the scope of the present invention. That is, (1) In this example, the data length is 4 digits,
Although the format is a zoned decimal number, any format can be applied as long as it is data with a decimal point.For example, the device may be configured in accordance with the above example regarding the maximum number of digits allowed by the language specifications. be able to. (2) Although two decimal point accumulators are used in this embodiment, the second operand storage accumulator (embodiment register 306) does not need to be a register, and may be directly input to the arithmetic unit input gate. (3) In this example, rounding and blank code filling are shown as operations performed on the calculation results.
It is not limited to these two examples, for example,
This does not preclude the incorporation of special operations when overflow occurs. (4) In this embodiment, the length below the decimal point is displayed using a descriptor, but it may be included in the instruction. (5) In this embodiment, the decimal point position of the decimal point accumulator is fixed, but it may be moved in accordance with the decimal point position of each data during calculation. The present invention has been described in detail using the embodiments above, but the apparatus of the present invention can perform digit alignment processing of decimal data at the time when one data is input, independently of the state of the other data. becomes possible,
An arithmetic device that is effective as a component for parallel processing systems such as pipeline processing can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the instruction format and descriptor format in an embodiment of the present invention. The SCALE field of the descriptor is a field that specifies the length of data after the decimal point, and the control field of the instruction is a field that specifies the length of data after the decimal point. This field specifies the operation to be performed. FIG. 2 is a diagram showing an example of a data format in an embodiment of the present invention. Third
The figure is a block diagram showing an embodiment of the present invention.
5 and 306 are accumulators with decimal point, 3
03 is a digit alignment and data conversion circuit for correctly loading data into an accumulator with a decimal point; 307 is an arithmetic unit; 309 is a conversion circuit for correctly storing calculation results in a result storage position; 3
13 is a constant generation circuit for rounding off.

Claims (1)

[Claims] 1. In the operation of data with a decimal point, means for displaying the position of the decimal point for each data, means for specifying the operation to be performed according to the result of the operation, an accumulator with a decimal point that fixes the position of the decimal point, and means for performing digit alignment when inputting a single data, loading the decimal point position of data according to the decimal point position given by the decimal point position displaying means to match the decimal point position of the decimal point accumulator; an arithmetic device that calculates data whose digits have been aligned by means; and a device that stores the arithmetic results of the arithmetic device in accordance with the decimal point position given by the means for displaying the decimal point position when storing the result in a result storage location. and a means for performing an operation specified by the means for specifying an operation to be performed in accordance with the result of the operation, and independently executing digit alignment processing for each piece of data to be subjected to the operation. A computing device featuring: