JPH0452488B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a store processing method suitable for an arithmetic pipeline data processing device.

[Conventional technology]

FIG. 1 shows a schematic configuration of a data processing device.
2 is an instruction unit that decodes the instruction, 2 is a storage unit that stores instructions and data, and 3 is an arithmetic unit that executes the operation specified by the instruction. In order to improve the processing capacity of the processing unit, the arithmetic pipeline divides the time required to execute an arithmetic operation into a plurality of cycles in the arithmetic unit 3, allocates a plurality of different instruction processes to each cycle, and then This method performs pipeline control on the

When implementing such calculation pipeline control,
Conventionally, when a store instruction appears, processing of the store instruction is started after the operation of the preceding instruction is completed. This means that if the destination register that stores the operation result of the preceding instruction is specified as the source register of the store data in the subsequent store instruction, the store processing is executed before the operation of the preceding instruction is completed. This is because once started, the operation results of the preceding instructions are not reflected in the store data.

An example of the configuration of a conventional arithmetic unit is shown in FIG.
Figure 2 shows an example of a floating point arithmetic unit, 11,
12 is a selector, 13, 14, 16, 17, 19
etc. are work registers, 15 is a preshifter, 18
20 is a parallel adder, 20 is a post-shifter, 21 is an operation result register, 22 is a register group, 23 is a store data register, 30 is an operand wraparound control circuit, and 31 is a memory request control circuit. Here, the execution cycles of the arithmetic units are assumed to be E, F, and N. E stands for Execution cycle.
F is F (next of E) cycle, N is Normalize
It is an abbreviation for cycle. A register storing cycle follows after E, F, and N, and this is called a P (Put Away) cycle. The register group 22 generally has two, a general-purpose register group and a floating-point register group.The floating-point register group is used for floating-point operations, and the general-purpose register group is used for other operations, but in the figure, only one register is used. Shown as a group.

Now, consider a case where the preceding instruction is an addition instruction, followed by a store instruction, and the destination register that stores the operation result of the preceding addition instruction is the same as the source register of the store instruction. A time chart of a conventional calculation pipeline in this case is shown in FIG. In FIG. 3, AD represents an add instruction and STD represents a store instruction.

Referring to FIG. 3, operand data is transferred to selectors 11 and 1 from operand buses 101 and 102.
2 in the registers 13 and 14, in the first cycle, prior to the addition operation, the shifter 15 performs a preshift operation to align the operand with the smaller exponent part with the larger operand. In the second cycle, the digits are aligned and register 1
The parallel adder 18 performs parallel addition on the operand data (mantissa part) set to 6 and 17. The third cycle is a cycle for post-normalization, and an invalid 0 is placed at the beginning of the mantissa for the operation result set in register 19.
The mantissa part is shifted by the shifter 20 so as not to occur, and the exponent part is corrected by the shifted amount. Thereafter, in the fourth cycle, the operation result set in the register 21 is stored in a predetermined register (destination register) in the register group 22 via the operand bus 103.

On the other hand, processing of the next store instruction starts in the fourth cycle. The operand wraparound control circuit 30 monitors the operand parts of successive instructions, and the destination register that stores the operation result of the preceding instruction is used as the source of the next instruction.
If specified as a register, the operation result is sent to the selectors 11 and 12 via the signal line 104 without waiting for it to be stored in the corresponding register of the register 22.
This is a circuit that controls the register 13 or 14 to set target data in the register 13 or 14. From FIG. 3, the addition result of the preceding addition instruction is determined at the end of the third cycle. Therefore, processing of the next store instruction is started in the fourth cycle, and under the control of the operand wraparound control circuit 30, the addition result of the advance addition instruction is sent to the signal line 104 as store data.
It is set in the register 14 via the selector 12. In the next fifth cycle, the store data in the register 14 is transferred to the register 23, and the memory request control circuit 31 issues a store request, thereby writing the store data to the storage unit via the signal line 105. Similarly, if the destination register that stores the operation result of the preceding instruction and the source register that stores the store data of the next store instruction are different,
In the 4th cycle, store data is transferred to operand bus 1.
02, it is set in the register 14 via the selector 12, and written to the storage unit via the register 23 and signal line 105 in the fifth cycle.

Figure 3 shows a case where the store instruction uses the destination of the preceding instruction three cycles before as the source register. , the operation result of the previous instruction is stored in register 2.
1, so this is directly transferred to the selector 12 via line 104'.

As described above, the conventional idea was that the processing of the subsequent store instruction could not be started until the operation of the preceding instruction was completed, which was one of the reasons that hindered speeding up of the operation pipeline. was.

[Purpose of the invention]

An object of the present invention is to improve the performance of an arithmetic pipeline data processing device by processing store instructions at high speed.

[Summary of the invention]

The key point of the present invention is that when a store instruction is issued, processing of the store instruction is immediately started to obtain the store data, and the destination register of the previous instruction and the preceding instruction and the source register of the store instruction are If they match, the store data is sequentially replaced with the operation result of the previous instruction or the preceding instruction and sent to the storage unit.

[Embodiments of the invention]

FIG. 4 shows an embodiment of an arithmetic unit according to the present invention. In FIG. 4, 24 and 26 are selectors, 25 is a buffer register, 32 is a selector control circuit, and the other configurations are the same as in FIG. 2.

In FIG. 4, when a store instruction is issued, processing of the store instruction is immediately started, and the data held in the corresponding register (source register) of the general-purpose register group 22 is used as store data, and the operand bus 101, selector 12 via register 14
Set to . This store data is sequentially transferred to registers 25 and 23 via selectors 24 and 26 at one cycle pitch. During the transfer of this store data, the selector 24 performs
If the destination register of the previous instruction and the source register of the store instruction match,
The operation result of the previous instruction on the signal line 104 is selected and set in the register 25 in place of the old store data. Similarly, in the selector 26, if the destination register of the preceding instruction and the source register of the store instruction match, the signal line 104
The operation result of the preceding instruction above is selected and set in the register 23 instead of the old store data. A selector control circuit 32 controls these selectors 24 and 26.

FIG. 5 shows a detailed diagram of the selector control circuit 32. In FIG. 5, 40, 41, and 42 are registers, and 43, 44 are comparison circuits. At the beginning of the E cycle of the arithmetic pipeline, the register address R1 of the first operand of the instruction to be executed is set in the register 40, and shifted to the register 41 and register 42 in the F cycle and the N cycle. The first operand of an instruction indicates a destination register in which the operation result is stored in the case of an operation instruction, and indicates a source register in which store data is stored in the case of a store instruction. The comparison circuit 43 compares the contents of the register 40 and the register 42 under the condition that a store instruction is being processed at the beginning of the F cycle, and if they match, it outputs "1" to the signal line 106.
Output. At the beginning of the next N cycle, the comparison circuit 44 compares the contents of the register 41 and the register 42 under the condition that the store instruction is being processed, and outputs "1" to the signal line 107 if they match.

Here, the fact that the signal line 106 is "1" means that
This means that the source register of the store instruction and the destination register of the instruction preceding the store instruction match. Also, signal line 1
07 being "1" means that the source register of the store instruction and the destination register of the instruction immediately before the store instruction (preceding instruction) match. Selector 24 in Figure 4
When the signal line 106 is "1", the signal line 104 is stored instead of the old store data in the register 14.
Select the operation result of the next instruction output above,
When the signal line 107 is “1”, the selector 26 selects the signal line 10 instead of the old store data in the register 25.
This selects the operation result of the preceding instruction No. 4.

FIG. 6 shows a time chart of the calculation pipeline when the present invention is applied. This corresponds to Figure 3, and as in the case of Figure 3, the preceding instruction is an addition instruction, followed by a store instruction, and a destination register is used to store the operation result of the preceding addition instruction. This is an example of a case where the register becomes a source register for a subsequent store instruction. In FIG. 6, the relationship between the next-to-last instruction (this is assumed to be a subtraction instruction SUB) and the store instruction STD is also shown by dotted lines.

Execution of the preceding addition instruction AD is the same as before, in which the preshift operation is executed by the shifter 15 in the first cycle, and the parallel adder 18 is executed in the second cycle.
In the third cycle, the shifter 20 performs the addition operation and the post-normalization operation by the shifter 20, respectively. The operation result obtained in this third cycle is stored in a predetermined register (destination register) of the register group 22 in the next fourth cycle.

On the other hand, processing of the next store instruction STD starts immediately in the second cycle. In this second cycle,
The data before the change stored in the corresponding register (source register) of the register group 22 is set as store data (old store data) in the register 14 via the operand bus 102 and the selector 12. This old store data is transferred to the register 25 via the selector 24 in the next third cycle. Until the next fourth cycle, the output signal line 107 of the selector control circuit 32 becomes "1" because the source register of the store instruction and the destination register of the pre-add instruction are the same. The selector 26 selects the signal line 104 instead of the register 25. At this time, the calculation result of the preceding addition instruction is output to the signal line 104. Therefore, in this fourth cycle, register 2
In place of the old store data of No. 5, the calculation result on the signal line 104 is set in the register 23 via the selector 26 and written into the storage unit.

Comparing Figure 3 and Figure 6, in Figure 3 the execution of the instruction following the store instruction starts at the 5th point.
Although it is from the cycle, it is the third cycle in FIG. 6, and a speedup of two cycles is achieved. Note that, as shown by the dotted line in FIG. 6, the destination register of the subtraction instruction SUB, which is the preceding instruction of the addition instruction AD (the next instruction of the store instruction STD), matches the source register of the store instruction STD. If so, it is determined around the third cycle, and the selector 24 selects the operation result of the row-to-row subtraction instruction SUB on the signal line 104 instead of the store data in the register 14, and stores it in the register 2.
It will be moved to 5.

Although the present invention has been described above using an example in which the present invention is applied to a floating point arithmetic unit, it goes without saying that the present invention is not limited to this.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, even if a store instruction is issued, the processing is started immediately in arithmetic pipeline control in which processing of a plurality of different instructions is assigned to each cycle and processed in parallel. , If the operands of the destination register of the next line or the preceding instruction and the source register of the store instruction match and it is necessary to change the store data, the store data is changed during the processing of the store instruction. Since the calculation result of the previous or preceding instruction is sequentially replaced, store instructions can be processed at high speed without any disturbance to pipeline control, and the performance of data processing devices using such calculation pipeline control method can be further improved. achieved.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of a data processing device, FIG. 2 is a diagram showing an example of the configuration of a conventional calculation unit, FIG. 3 is a timing diagram explaining a conventional calculation pipeline, and FIG. 4 is a calculation diagram of the present invention. FIG. 5 is a detailed diagram of the selector control circuit in FIG. 4, and FIG. 6 is a timing diagram illustrating the arithmetic pipeline of the present invention. 11, 12, 24, 26...Selector, 13, 1
4, 16, 17, 19, 21, 25, 26... register, 15, 20... shifter, 18... parallel adder,
22...Register group, 32...Selector control circuit.

Claims (1)

[Claims] 1. In a data processing device using an arithmetic pipeline control method in which processing of a plurality of different instructions is assigned to each cycle and processed in parallel, a first arithmetic instruction, a second arithmetic instruction, In the store processing method when a store instruction is issued, in the first cycle of the store instruction processing, data indicated by the source data address of the store instruction is set in the first register, and in the next second cycle, the Compare the source data address of the store instruction and the destination address of the first operation instruction, and if they do not match, select the data in the first register, and if they match, select the operation result data of the first operation instruction. Well, second
In the next third cycle, the source data address of the store instruction and the destination address of the second operation instruction are compared, and if they do not match, the data in the second register is changed, and if they match, the data in the second register is A store processing method for a data processing apparatus, characterized in that the operation result data of the second operation instruction is selected and used as the final store data of the store instruction.