JP2819733B2 - Information processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus used for an information processing apparatus, and particularly to an information processing apparatus having a preceding control device.

〔Overview〕

The present invention relates to a pipeline type information processing apparatus, which identifies whether an input instruction is a memory access instruction or a non-memory access instruction, and when the cache access unit is busy, the non-memory access instruction The instruction identified as one is intended to improve the processing performance by continuing to execute the preceding control.

[Conventional technology]

Conventionally, when the cache access unit is in a busy state, in order to simplify pipe synchronization control, processing of a cycle before the cache access is stopped until the busy state is released.

[Problems to be solved by the invention]

The conventional prior-art control device described above has a drawback that when the cache access unit is busy, the preceding control unit is in a stopped state, so that the processing performance is reduced when the subsequent instruction is a non-memory access instruction. there were.

The object of the present invention is to eliminate the disadvantages mentioned above,
An information processing apparatus having a precedence control device capable of continuously executing precedence control even when a cache access unit becomes busy when a subsequent instruction is a non-memory access instruction and without reducing processing performance Is to provide.

[Means for solving the problem]

The present invention relates to an information processing apparatus including a cache access unit and having a pipeline in which a series of processing steps is divided into a plurality of cycles and an instruction is executed in each cycle. A memory access identification unit that identifies whether the instruction is an access instruction, and an instruction that, when the cache access unit is busy, causes the memory access identification unit to continue executing the instruction identified as a non-memory access instruction. Means.

Also, in the present invention, the memory access identification means decodes flag information defining an operation attached to the input instruction, identifies whether the instruction is a memory access instruction or a non-memory access instruction, and identifies the instruction by an identification signal. A cache access control unit that detects that the cache access unit is in a busy state and outputs a detection signal; and a cache access control unit that outputs the detection signal during the cycle by the detection signal and the identification signal. And a synchronization control unit for controlling the synchronization of the data.

Further, the present invention provides the cache access control unit,
The access address signal to the cache access unit and a logical OR of the output signal from the cache access unit and the detection signal are output, and the synchronization control unit includes the detection signal and the identification signal. It is preferable that a set instruction and a hold instruction of a register constituting a predetermined cycle are performed by four combinations of the logic levels of the above.

[Action]

The memory access identification means identifies whether or not the input instruction is a memory access instruction by, for example, a flag added to the instruction, and outputs the result. When the cache access unit is in a busy state and the instruction cannot be executed, and when the subsequent instruction is a non-memory access instruction, the execution means continues the preceding control to execute the instruction.

Therefore, even if the cache access unit becomes busy,
It is no longer necessary to stop all instructions until the busy state is released, unlike the related art, and it is possible to improve the processing performance as a whole.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

This embodiment shows a case where a series of processing steps is divided into five cycles (phases) of D, A, T, O, and E, and a pipeline for executing an instruction in each cycle is provided.

And registers 10 to 20, base register (BR) 30,
Index registers (GR) 31, registers 32 with multiple base registers inside, registers 33 with multiple index registers inside, translation table (TLB) 4
0, cache access unit (CACH) 41, decoder 50, 3
Input carry save adder (CSA) 51, 2-input adder (AD) 52, cache access control unit 53, synchronization control unit
54, a selector 55, and an arithmetic unit (ALU) 56 are included.

In D cycle, base register specified after instruction
Index 30 and index register 31 are indexed, and decoder 50 determines whether or not the instruction is a memory access instruction, and outputs “1” to register 11 through signal line 101 when the instruction is a non-memory access signal.

In the A-sile, the displacement specified by the base register 30, the index register 31, and the instruction is added to generate an operand address.

In the T cycle, the operand address generated in the A cycle is converted into a physical address by the conversion table 40.

In the O cycle, the cache access unit 41 is indexed with the physical address of the operand generated in the T cycle to obtain operand data.

In the E cycle, an operation is performed using the operand data indexed in the O cycle, and the base register 30 or the index register 31 is updated.

The cache access control unit 53 controls access to the conversion table 40 and the cache access unit 41, and outputs “1” from the signal line 102 when cache access is possible.

This control is performed by performing a NOR operation on the logic levels of the signal lines 103 and 104, that is, , The logical output of the signal line 102 is determined.

The synchronization control unit 54 receives the signal lines 101 and 102 as inputs,
Taking the logic shown in Table 1, the signal lines 105, 106, 107 and 1
08 to perform cycle control of D cycle and A cycle.

The register 14 is a register used for the operation indicated by the instruction word and has immediate data. Since the registers 16, 18 and 20 carry the above-mentioned values in correspondence with the T cycle, the O cycle and the E cycle, respectively. Register.

The register 10 is a register having an instruction word, and the F field is a field defining the operation of the instruction.

The base register 30 and the index register 31 are a group of registers each having a plurality of registers, and the carry-save adder 51 receives the output of the base register 30, the output of the index register 31, and the displacement portion of the register 10. Then, the addition result is output to the register 12 and the register 13.

The adder 52 inputs the outputs of the register 12 and the register 13 to perform addition, and outputs the addition result to the register 15 as an operand logical address.

The conversion table unit 40 indexes the operand logical address from the register 15 as an address, and outputs the index result to the register 17 as an operand physical address.

Cache access unit 41 indexes the operand physical address from register 17 as an address, and outputs the index result to register 19 as operand data.

Register groups 32 and 33 include registers 19 and
This buffer corresponds to 20 and is a group of registers for buffering data until the data is actually used by the arithmetic unit 56.

A feature of the present invention is that, in FIG. 1, a decoder 50 as a memory access identifying means for identifying whether or not an input instruction is a memory access instruction as a preceding control means.
When the register 11 and the cache access unit 41 are in a busy state, the instruction identified by the decoder 50 as a non-memory access instruction is a cache access control unit 53 and an execution unit for continuously executing the preceding control. That is, the synchronization control unit 54 is provided.

Next, the overall operation of the present embodiment will be described with reference to the timing charts shown in FIG. 2 and FIG. Here, FIG. 2 shows a timing chart for the present embodiment, and FIG. 3 shows the decoder 50 and the register 1 in FIG.
1, a timing chart for a conventional example without a cache access control unit 53 and a synchronization control unit 54.

2 and 3, instructions 0 and 3 are memory access instructions, and instructions 1 and 2 are non-memory access instructions.

FIG. 2 shows an example in which the instruction 0 causes a cache miss in the T2 cycle, but the instructions 1 and 2 are non-memory access instructions, so that the pipes in the D cycle and the A cycle are continuously operated without stopping.

On the other hand, FIG. 3 shows that D0 and A
This is an example in which the pipe of the cycle has stopped.

〔The invention's effect〕

As described above, the present invention discriminates whether an instruction is a memory access instruction or a non-memory access instruction and, even if the cache access unit is in a busy state, performs a pre- Has the effect that instruction processing can be performed at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a time chart showing the operation. FIG. 3 is a time chart of a conventional example. 10 to 20: Register, 30: Base register (BR), 31
Index registers (GR), 32, 33 Register groups, 40 Conversion table section (TLB), 41 Cache access section (CACH), 50 Decoder, 51 Carry save adder ( CSA), 52 adder (AD), 53 cache access control unit, 54 synchronization control unit, 55 selector, 56 arithmetic unit (ALU), 101 to 108 signal lines.

Claims (3)

(57) [Claims] 1. An information processing apparatus including a cache access unit and having a pipeline in which a series of processing steps is divided into a plurality of cycles and executes instructions in each cycle, wherein an input instruction is a memory access instruction. A memory access identification unit for identifying whether the instruction is a non-memory access instruction, and when the cache access unit is in a busy state, the instruction identified as a non-memory access instruction by the memory access identification unit continues to execute the preceding control. An information processing apparatus comprising: an execution unit configured to execute the processing. 2. The memory access identification means decodes flag information defining an operation attached to an input instruction, identifies whether the instruction is a memory access instruction or a non-memory access instruction, and outputs an identification signal. A cache access control unit that detects that the cache access unit has become busy and outputs a detection signal; and a cache access control unit that outputs the detection signal according to the detection signal and the identification signal. The information processing apparatus according to claim 1, further comprising: a synchronization control unit configured to control synchronization. 3. The cache access control unit according to claim 1, wherein the detection signal is output by performing a NOR operation on an access address signal to the cache access unit and a corresponding output signal from the cache access unit. 3. The information processing apparatus according to claim 2, wherein the synchronization control unit is configured to issue a set instruction and a hold instruction of a register constituting a predetermined cycle by four combinations of logic levels of the detection signal and the identification signal.