JPS61176122A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, particularly a method for manufacturing an m-v group compound mixed crystal layer epitaxially grown on the (111}A plane of an indium phosphorus compound (InP) single crystal. A small portion of
The present invention relates to a manufacturing method that selectively removes InP single crystals without depending on the crystal direction.

For example, indium phosphide (InP)/indium gallium arsenide (InGaAs) is used as a semiconductor light receiving device for optical communication.
Or indium gallium arsenide t8 (InGaAsP
) type avalanche photodiode (8PD) has been developed.

When manufacturing this APD, the (111}A plane is often used as a 1nP substrate surface suitable for epitaxial growth, but the ■-■ group compound semiconductor epitaxial growth layer on this surface is selectively etched to create a uniform surface with a circular shape etc. The process of patterning is still unsolved.

[Conventional technology]

As a chemical etching solution for processing an m-v group compound mixed crystal epitaxially grown on the (111}A plane of an InP single crystal, the following configuration, for example, is conventionally known.

+8) Hydrochloric acid (HCI):acetic acid (CHsCOOH):hydrogen peroxide (IhOz)=t:t:t, 1:2:1, etc.

(b) Sulfuric acid (H2SOa): hydrogen peroxide solution (H20□)
: Water (HzO) = 1:1:1.1:2:l, etc.

(C1 phosphoric acid (t13Po,) ? hydrochloric acid (HCI) = 1
:1 etc.

(d) Bromine (Brt): methanol (CI+OH)
= 1:50 etc.

However, with these conventionally known etching solutions, etch pits are generated on the etched surface and the etching rate is not smooth, and the etching rate changes depending on the direction of the crystal. For example, as shown in FIG. 111}
On side A, aluminum indium arsenide (
By epitaxially growing an indium gallium arsenide (InGaAs) layer 2 and an indium gallium arsenide (InGaAs) layer 3 with a thickness of approximately 2 -, a circular mask 4 of silicon nitride (Si3N*) is provided, and an etching solution having the composition (Al) is used. , the planar shape of the resulting epitaxially grown layer changes significantly from a circular shape.

Furthermore, since the side surfaces of the mesa structure formed by etching are sloped as shown in the figure, the shape and dimensions of the heterojunction interface vary as the thickness of the epitaxial growth layer changes, making it difficult to control this. be.

[Problem that the invention seeks to solve]

For example, in semiconductor devices such as APDs, it is necessary to pattern a ■-v group compound mixed crystal layer epitaxially grown on the (111}A plane of an InP single crystal with good reproducibility and to obtain a smooth etched surface. , as mentioned above
This cannot be achieved using conventional chemical etching methods, and improvements in etching methods are desired.

[Means for solving problems]

The above problem is caused by the (11
1} When selectively removing at least a part of the ■-■ group compound mixed crystal epitaxial growth layer on the A-plane with respect to the indium/phosphorus compound single crystal, a solution containing bromine, hydrogen bromide, and water is used. This problem is solved by the method of manufacturing a semiconductor device according to the present invention using an etching solution.

[For production]

In the present invention, the (111}A plane [(
Bromine (Brg) and hydrogen bromide (HBr) were used as an etching solution for patterning the m-v group compound mixed crystal epitaxial growth layer on [111} representing a set of planes equivalent to the A-plane].
A solution containing water (HzO) and water (HzO) is used.

By using this etching solution, this ■-V group compound mixed crystal layer is patterned in a similar shape to the mask pattern and perpendicular to this plane, independent of the direction on the (111}A plane of the InP single crystal, The etched surface will be smooth without any etch pits.

〔Example〕

The present invention will be specifically explained below using examples.

FIG. 1(a) is a plan view showing a first embodiment of the present invention, and FIG. 1(b) is a sectional view thereof.

In this example, an A layer with a thickness of about 1irrn was grown on the (111}A plane of an InP single crystal 1 by a liquid phase epitaxial growth method.
to, 4s Ino, 5tAs layer 2 and Ino of about 2-thickness, 53ca@, 4? The epitaxially grown layer 2.3 is patterned into a circular mesa structure on the semiconductor substrate on which the As layer 3 and the As layer 3 are successively grown.

That is, a St, 3N4 film having a thickness of about 0.21 rm is provided on the InGaAs layer 3 by, for example, plasma chemical vapor deposition (CVO), and a circular mask 4 with a diameter of 140 mm is formed by photolithography.

In this state, etching was performed for about 1.0 seconds in a mixed solution of bromine (Brz), hydrochloric acid (47χHBr), and water (H2O) in a volume ratio of 1:17:34, followed by water washing. I do.

In the sample obtained by this etching process, the amount of side etching is constant regardless of the direction and is about 10 -, and the cross section obtained between the folds has the shape shown in Figure (b), and the side etching amount is constant regardless of the direction. Etched surface is InP
It is perpendicular to the (111}A plane of the single crystal 1. Therefore, the epitaxial growth layer 2.3 is formed into a right circular column shape.

Furthermore, no etch pits were observed on the (111}A plane of the InP single crystal 1 exposed by this etching process.
The mirror surface is maintained.

Next, FIG. 2fa) is a plan view showing a second embodiment of the present invention, and FIG. 2(b) is a sectional view thereof.

In this example, Al is placed on the (111}A plane of InP single crystal 1.
For a semiconductor substrate in which a GaInAs layer 2a and an AlInAs layer 3a are sequentially grown, an epitaxially grown layer 2.3
is patterned into a mesa structure with the shape shown in the figure.

The material and thickness of the mask 4a, the composition of the etching solution, the etching time, etc. of this embodiment are the same as those of the first embodiment.

In this example as well, 1. The amount of side etching is constant regardless of the direction and is about 10 Jrm, and the etched planes of the epitaxial growth layers 2a and 3a are perpendicular to the (111}A plane of the InP single crystal 1. Therefore, The epitaxial growth layers 2a and 3a are formed into an upright column shape similar to the mask 4a.

Further, FIG. 3 (al) and FIG. 4 (a) are plan views showing the third embodiment of the present invention, and each figure (b) is a sectional view of each, and corresponding parts are denoted by the same reference numerals as in FIG. 1. shows.

The semiconductor substrate and mask 4 of this embodiment are similar to those of the first embodiment, but the composition of the etching solution is changed by volume to Br.
FIG. 3 shows the case where z:47χHBr:HzO=1:8:34 and the etching time is about 50 seconds, and FIG. 4 shows the case where the etching time is about 80 seconds.

With this composition of the etching solution, when the etching time is about 50 seconds, the etched plane of the epitaxially grown layer is inclined, but when the etching time is about 80 seconds, the etched plane of the epitaxially grown layer is tilted (111} of InP single crystal 1. It is perpendicular to plane A.

By selecting the composition of the etching solution and the etching time in this way, it is also possible to control the cross-sectional shape of the etched semiconductor layer.

Although the above embodiments are directed to the formation of a mesa structure, the manufacturing method of the present invention is not limited to the mesa structure, and can be generally applied to the manufacturing of semiconductor devices.

〔Effect of the invention〕

As explained above, according to the present invention, (1
11} The ■-■ group compound mixed crystal epitaxial growth layer on the A-plane is patterned in a similar shape to the mask pattern and perpendicular to this plane, regardless of the direction on that plane, and is smooth without etch bits etc. An etched surface can be obtained.

Note that if necessary, the cross section can be tilted, making it easier to realize a complex and fine structure that has been difficult in the past, which has a great effect on the advancement of semiconductor devices.

[Brief explanation of drawings]

1 to 4 show embodiments of the present invention, each figure (a)
is a plan view thereof, each figure (b) is a sectional view thereof, and Fig. 5 (al, (bl) shows a plan view and a sectional view of the conventional example. InP single crystal, 2 is A
1InAs layer, 2a is AlGalnAs layer,
3 is an InGaAs layer, 3a is an AllnAs layer, and 4 and 4a are masks. Rin 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] 1. On the {111}A plane of an indium-phosphorus compound single crystal
When selectively removing at least a portion of the III-V group compound mixed crystal epitaxial growth layer with respect to the indium-phosphorus compound single crystal, a solution containing bromine, hydrogen bromide, and water may be used as an etching solution. A method for manufacturing a featured semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the III-V group compound mixed crystal layer contains an aluminum-indium-arsenic compound mixed crystal. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the III-V group compound mixed crystal layer contains an aluminum-gallium-indium-arsenic compound mixed crystal. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the III-V group compound mixed crystal layer contains an indium-gallium-arsenic compound mixed crystal. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the III-V group compound mixed crystal layer contains an indium-gallium-arsenic-phosphorus compound mixed crystal.