JPS61172347A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the parasitic capacity to be added to the semiconductor parts of a semiconductor integrated circuit device and to contrive to enhance the operating speed of the device to a higher speed by a method wherein the protruded semiconductor parts are formed on the prescribed parts of the main surface of the semiconductor substrate and an insulating film, by which the semiconductor parts are electrically isolated from the semiconductor substrate, is formed under the lower parts of the semiconductor parts. CONSTITUTION:In the semiconductor integrated circuit device having an isolation structure, protruded (bar-shaped) n-type semimconductor parts 5A are provided on the upper part of the main surface of a semiconductor substrate 5 through an insulating film 6. The insulating film 6 is formed into an isolation structure to isolate electrically both of the semiconductor parts 5A and the semiconductor substrate 5. As this isolation structure is constituted of the insulating film 6 having a smaller specific dielectric constant compared to a p-n junction isolation structure, the parasitic capacity to be added to the semiconductor parts 5A can bre reduced. By this constitution, to enhance the operating speed of the semiconductor element to a higher speed can be contrived. Moreover, the n-type semiconductor substrate 5 consisting of single crystal silicon can be constituted at low cost compared to a substrate having insulation properties such as a sapphire substrate.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a semiconductor integrated circuit device, and in particular, a technique that is effective when applied to a semiconductor integrated circuit device having an isolation structure that electrically isolates semiconductor elements. It is related to.

[Background Art] For example, the isolation structure of a semiconductor integrated circuit device having a bipolar transistor uses a pn junction isolation technique as shown in No. 8@. That is, on top of a p-type semiconductor substrate 1, an epitaxially grown n-type semiconductor layer 2 constituting a semiconductor element is provided.

The semiconductor layers 2 are separated by the semiconductor substrate 1 and a p-type semiconductor region 3.

In such an isolation structure, a large parasitic capacitance is formed at the pn junction between the semiconductor layer 2, the semiconductor substrate l, and the semiconductor region 3, making it impossible to increase the operating speed. Since a reverse bias is applied between the semiconductor region 3 and the semiconductor region 3 to ensure electrical isolation, the depletion layer formed at the pn junction portion between them increases.

Therefore, a margin is required to prevent seams between semiconductor elements due to punch-through, which increases the area occupied by the isolation structure and reduces the degree of integration of the semiconductor integrated circuit device.

Therefore, as shown in FIG. 9, an isolation structure is used which is composed of an insulating film 4 formed by selective oxidation of silicon and a semiconductor substrate 1. In this isolation structure, since the dielectric constant of the insulating film 4 is smaller than that of the semiconductor region 3, the parasitic capacitance added to the semiconductor layer 2 can be reduced and the operating speed can be increased. Further, since no depletion layer is formed in the insulating film 4, the area occupied by the isolation structure can be reduced, and a decrease in the degree of integration of the semiconductor integrated circuit device can be suppressed.

However, even in such an isolation structure, a parasitic capacitance is formed at the pn junction between the semiconductor substrate 1 and the semiconductor layer 2, so that the operating speed of the semiconductor integrated circuit device cannot be sufficiently increased.

Therefore, instead of using a semiconductor substrate, an SO5
(Silicon On 5apphire) technology must be used. This makes it possible to reduce the parasitic capacitance between the sapphire substrate and the semiconductor layer, thereby increasing the operating speed of the semiconductor integrated circuit device.

However, as a result of studies conducted by the present inventors, the inventor found a problem in that the sapphire substrate is expensive, making the semiconductor integrated circuit device expensive.

[Object of the Invention] An object of the present invention is to provide a technique that can inexpensively increase the operating speed in a semiconductor integrated circuit device having a one-separation structure.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

In other words, a protruding semiconductor portion is formed on a predetermined main surface of a semiconductor substrate, and an insulating film is formed below the semiconductor portion to electrically isolate it from the semiconductor substrate, thereby forming a semiconductor integrated circuit device with an isolated structure. do.

As a result, it is possible to reduce the parasitic capacitance added to the semiconductor portion in which the semiconductor element is formed using a normal silicon process, so that the operation speed can be increased at low cost.

Hereinafter, the configuration of the present invention will be explained along with examples.

[Embodiment] FIGS. 1 and 2 are sectional views of essential parts of a semiconductor integrated circuit device having an isolation structure for explaining an embodiment of the present invention.

It should be noted that in all the examples, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

In FIGS. 1 and 2, 5 is an n-type semiconductor substrate made of single crystal silicon. The semiconductor substrate 5 can be constructed at a lower cost than an insulating substrate such as a sapphire substrate.

5A is a protruding (rod-shaped) n-type semiconductor portion.

It is provided on the upper main surface of the semiconductor substrate 5 with an insulating film 6 interposed therebetween. The semiconductor section 5A is configured using a part of the semiconductor substrate 5, and is configured to configure a semiconductor element such as a bipolar transistor, for example.

The insulating film 6 forms an isolation structure that electrically isolates the semiconductor portion 5A and the semiconductor substrate 5. This isolation structure is composed of an insulating film 6 whose dielectric constant is smaller than that of pn junction isolation (approximately one third in the case of silicon oxide), so the parasitic capacitance added to the semiconductor portion 5A is reduced. can be reduced. This makes it possible to increase the operating speed of the semiconductor element.

Reference numeral 7 denotes a buried member, which is provided above the insulating film 6 between the semiconductor parts SA. The embedded member 7 is configured to have insulating properties, and forms an isolation structure that electrically isolates the semiconductor portions 5A. Further, the embedded member 7 may be configured to have conductivity, and may constitute a part of a semiconductor element or wiring.

Moreover, compared to the one shown in FIG. 1, the embedded member 7 is designed to reduce the undulations formed by the semiconductor portion 5A and make it flat, thereby suppressing the reduction in resolution of the photoresist film, etc., and the disconnection of the conductive layer. It is composed of

In FIG. 2, the isolation structure that electrically isolates the semiconductor portion 5A is composed of an insulating film 6 and a buried member 7. This isolation structure is also composed of an insulating film 6 and a buried member 7, which have a smaller dielectric constant than pn junction isolation.
The parasitic capacitance added to the semiconductor portion 5A can be reduced.

Next, a specific manufacturing method of this embodiment will be briefly explained using the semiconductor integrated circuit device shown in FIG.

3 to 7 are sectional views of essential parts of a semiconductor integrated circuit device having a separation structure in each manufacturing process for explaining a manufacturing method according to an embodiment of the present invention.

First, as shown in FIG. 3, a heat treatment mask 8 and an etching mask 9 are sequentially laminated on a predetermined main surface of the semiconductor substrate 5. As shown in FIG. For example, the heat treatment mask 8 is made of carbon so that the etching rate is different from that of the silicon nitride film heat treatment mask 8 formed by CVD technology.
A silicon oxide film formed by VD technology is used.

After the step of forming the heat treatment mask 8 and the etching mask 9 shown in FIG. 3, the main surface of the semiconductor substrate 5 is etched using the etching mask 9, and as shown in FIG. form. The semiconductor portion 5A is formed by an anisotropic etching technique using an etching gas such as CCQa=CB r F 3 so that the error in the amount of mask dimension conversion is reduced. By using this anisotropic etching technique, the etching rate between the semiconductor substrate 5 and the etching mask 9 can be increased from 5:1 to 1.
The ratio can be set to about 0:1. Further, by using the anisotropic etching technique, the height of the semiconductor portion 5A can be set relatively freely.

After the step of forming the semiconductor portion 5A shown in FIG. 4, the etching mask 9 is removed using, for example, an isotropic etching technique.

After this, as shown in FIG. 5, on the side of the semiconductor section 5A,
A heat treatment mask 10 is formed. The heat treatment mask 10 is formed, for example, by subjecting a silicon nitride film formed by CVD technology, plasma technology, etc. to an anisotropic etching technology.

After the step of forming the heat treatment mask 10 shown in FIG. 5, the exposed substantial main surface portion of the semiconductor substrate 5 is partially removed using the heat treatment masks 8 and 10 as an etching mask.

After this, as shown in FIG. 6, the heat treatment mask 8.10
An insulating film 6 is formed on the exposed upper part of the main surface of the semiconductor substrate 5 and on the lower part of the semiconductor part 5A.

The insulating film 6 is a silicon oxide film and is formed using high pressure oxidation technology.

After the step of forming the insulating film 6 shown in FIG. 6, the heat treatment masks 8 and 10 are removed.

Then, as shown in FIG. 7, an insulating film 7A is formed to cover the entire surface. For example, a silicon oxide film formed by CVD technology is used as the insulating film 7A.

After the step of forming the insulating film 7A shown in FIG. 7, the insulating film 7A is subjected to an anisotropic etching technique to the extent that the main surface of the semiconductor portion 5A is exposed, and the insulating film 7A is etched as shown in FIG. form 7.

Thereafter, although not shown, semiconductor elements are formed in the semiconductor portion 5A, and wiring for electrically connecting the semiconductor elements, a protective film for protecting the semiconductor elements, etc. are formed. Through these series of manufacturing steps, the semiconductor integrated circuit device of this embodiment is completed.

As explained above, according to this embodiment, the semiconductor substrate 5
A semiconductor portion 5A is formed on a predetermined main surface portion of the semiconductor portion 5.
An insulating film 6 electrically isolated from the semiconductor substrate 5 under A.
By forming this, the parasitic capacitance added to the semiconductor portion 5A can be reduced, so that the operating speed of the semiconductor integrated circuit device can be increased.

In addition, an inexpensive semiconductor substrate 5 is used, and an insulating film 6 for electrically separating the semiconductor substrate 5 and the semiconductor portion 5A is formed in one layer.
It can be formed using a normal silicon process, so
A semiconductor integrated circuit device can be formed at low cost.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the spirit of the invention.

For example, in the embodiment described above, the present invention was applied to an example in which the semiconductor portion 5A was composed of the semiconductor base Fi5, but a semiconductor substrate having epitaxial layers laminated thereon may be used, and the semiconductor layer may be formed from the epitaxial layers.

[Effects] As explained above, according to the present invention, in a semiconductor integrated circuit device, a protruding semiconductor portion is formed on a predetermined main surface portion of a semiconductor substrate, and the lower part of the semiconductor portion is electrically connected to the semiconductor substrate. By forming the separating insulating film, it is possible to reduce the parasitic capacitance added to the semiconductor portion using a normal silicon process, so that the operation speed can be increased at low cost.

[Brief explanation of the drawing]

1 and 2 are cross-sectional views of main parts of a semiconductor integrated circuit device having an isolation structure for explaining one embodiment of the present invention, and FIGS. 8 and 9 are cross-sectional views of main parts of a semiconductor integrated circuit device having a separation structure in each manufacturing process for explaining the manufacturing method, and FIGS. 8 and 9 are cross-sectional views of main parts of a semiconductor integrated circuit device having a conventional separation structure. be. In the figure, 5... semiconductor substrate, 5A... semiconductor part, 6...
. . . Insulating film, 7 . . . Embedded member, 8, 10 . . . Heat treatment mask, 9 . . . Etching mask. Figure 1 5 (n) 6 Figure 6 Figure 8 Figure 9 Figure 1 (P)

Claims (1)

[Claims] 1. A step of sequentially stacking a first heat treatment mask and an etching mask on the upper main surface of the semiconductor substrate, and etching the main surface of the semiconductor substrate using the etching mask to form protruding semiconductor parts. a step of removing the etching mask; a step of forming a second heat treatment mask on the side of the semiconductor portion; and a step of forming the first etching mask.
a step of forming an insulating film on the upper main surface of the semiconductor substrate and the lower part of the semiconductor portion using a heat treatment mask and a second heat treatment mask. .