JP2826405B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure of a capacitor for preventing oscillation.

[0002]

2. Description of the Related Art In designing an electronic circuit of a semiconductor integrated circuit, a capacitor is connected between a collector and a base of a transistor to prevent oscillation of the circuit in order to improve the high frequency characteristics of a common emitter amplifier circuit. ing.

In a conventional bipolar transistor, FIG.
As shown in (1), a characteristic of the PN junction is that a PN junction capacitance element is formed parasitically between the base layer 6 and the N-type epitaxial layer 4 serving as a collector layer.

However, the capacitance value of this PN junction capacitance element is generally about 10 ⁻¹⁵ F / m ² , which is small as a collector-base capacitance element for preventing oscillation. For this reason, a capacitive element is provided on the silicon substrate 1 separately from the transistor, and is connected to the collector layer and the base layer by aluminum wiring or the like.

[0005]

As described above, in a conventional semiconductor integrated circuit, when a capacitor for preventing circuit oscillation is provided between the collector and the base of a bipolar transistor, the transistor and the capacitor are separately provided in a semiconductor device. And are connected by metal wiring. Therefore, there is a problem that the number of elements formed in the semiconductor device increases and the size of the semiconductor device increases.

An object of the present invention is to provide a semiconductor device having an improved degree of integration by forming a capacitor for preventing circuit oscillation in a transistor region.

[0007]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: an N-type epitaxial layer formed on a P-type semiconductor substrate; an element isolation oxide film formed around the N-type epitaxial layer; A base layer formed in the epitaxial layer, a groove close to the epitaxial layer and deeper than the base layer formed in the element isolation oxide film, and a capacitor embedded in the groove and connected to the base layer. And a conductor film.

According to a second aspect of the present invention, there is provided a semiconductor device having an N-type epitaxial layer formed on a P-type semiconductor substrate, and an element isolation oxide film formed around the N-type epitaxial layer. An insulating film for a capacitor and a conductor film are formed on the epitaxial layer at the interface between the epitaxial layer and the element isolation oxide film.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1A to 1C are sectional views of a semiconductor chip for explaining a first embodiment of the present invention. Hereinafter, description will be made in the order of the manufacturing process.

First, as shown in FIG. 1A, an N-type buried layer 2 and an N-type epitaxial layer 4 are formed on a P-type silicon substrate 1.
To form Next, after forming a P-type insulating layer 3 for element isolation in the N-type epitaxial layer 4, a partially thick element isolation (field) oxide film 5 is formed by a selective oxidation method.

Next, as shown in FIG. 1B, after a P-type base layer 6 is formed in the N-type epitaxial layer 4 in the element forming region by an ion implantation method, the base layer 6 and the epitaxial layer 4 are formed. Next, an N-type emitter layer 7 and a base extraction layer 7A are formed. Next, a portion of the field oxide film 5 close to the epitaxial layer is etched by an isotropic etching method to provide a V-shaped groove 8.

Next, as shown in FIG. 1C, after a polycrystalline silicon film 9 is buried in the trench 8 by a selective CVD method, an interlayer insulating film 10 made of an oxide film or a nitride film is formed on the entire surface. To form a protective film. Thereafter, after connecting the polycrystalline silicon film 9 and the base layer 6 by wiring or the like, an electrode connected to each element is formed in the same manner as in the conventional example to complete the NPN transistor.

According to the first embodiment constructed as described above, the capacitive element uses the polycrystalline silicon film 9 and the N-type epitaxial layer 4 as electrodes and the field oxide film 5 between them as a dielectric film. Can be obtained. The capacitance value in this case depends on the thickness of the field oxide film 5 cut by the isotropic etching. For example, when the average thickness of the field oxide film 5 between the polycrystalline silicon film 9 and the epitaxial layer 4 is 1000 nm, the capacitance C _OX per unit area is 3.19 × 10 ^−11. Then, it becomes 3.19 × 10 ⁻⁴ F / m ² . That is, a capacitance element having a capacitance value that is two to three orders of magnitude larger than the capacitance value of the PN junction of the N-type epitaxial layer 4 and the base layer 6 of 10 ⁻¹⁵ F / m ² can be formed in the transistor.

The conductive film embedded in the trench 8 may be made of a high melting point metal such as W or an alloy thereof instead of polycrystalline silicon.

FIGS. 2A and 2B are cross-sectional views of a semiconductor chip for explaining a second embodiment of the present invention.

First, an N-type buried layer 2 and an N-type buried layer 2 are formed on a silicon substrate 1 in the same manner as in the first embodiment shown in FIG.
The epitaxial layer 4 and the field oxide film 5 are formed.

Next, as shown in FIG. 2A, after the field oxide film 5 on the N-type epitaxial layer 4 is entirely removed, a nitride film 1 having a thickness of 10 to 50 nm is formed by a low pressure CVD method.
Form one. Further, a polycrystalline silicon film 9A is formed at the end of the N-type epitaxial layer 4 separated by the P-type insulating layer 3.

Next, as shown in FIG. 2B, a field oxide film 5A for isolation is formed again by using the selective CVD method. Next, a P-type base layer 6, an N-type emitter layer 7, and a base extraction layer 7A are formed in the N-type epitaxial layer 4 by ion implantation. Hereinafter, an NPN transistor is completed by forming an interlayer insulating film, electrodes, and the like.

As described above, according to the second embodiment, similarly to the first embodiment, the polycrystalline silicon film 9A and the N-type epitaxial layer 4 are used as electrodes, and the nitride film 11 located between the two is used as a dielectric. A capacitor formed as a film can be formed in the transistor.

In the second embodiment, the oxide film is
Since a nitride film having a dielectric constant about twice that of the first embodiment can be used, and the nitride film can be formed to be thin with good controllability, a capacitor having a higher capacitance than in the first embodiment can be formed in the transistor.

Although the nitride film is used as the dielectric film in the second embodiment, an oxide film may be used. Although a polycrystalline silicon film is used as the electrode, a high melting point metal such as Al or W and an alloy thereof may be used.

[0022]

As described above, according to the present invention, by providing an insulating film for a capacitor and a conductor film at the interface between an element isolation oxide film and an N-type epitaxial layer, oscillation in a transistor region is prevented. This has an effect that a capacitor can be formed. Therefore, a semiconductor device having an improved degree of integration as compared with the related art can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor chip for explaining a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor chip for explaining a second embodiment of the present invention.

FIG. 3 is a cross-sectional view of an example of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 N-type buried layer 3 P-type insulating layer 4 N-type epitaxial layer 5 Field oxide film 6 Base layer 7 Emitter layer 7A Base extraction layer 8 Groove 9, 9A Polycrystalline silicon film 10 Interlayer insulating film 11 Nitride film

Claims (3)

(57) [Claims] An N-type epitaxial layer formed on a P-type semiconductor substrate; an element isolation oxide film formed around the N-type epitaxial layer; a base layer formed on the epitaxial layer; A semiconductor device comprising: a groove adjacent to a layer and deeper than the base layer formed in the element isolation oxide film; and a conductor film for a capacitor buried in the groove and connected to the base layer. . 2. The semiconductor device according to claim 1, wherein the groove is formed in a V-shape. 3. A semiconductor device having an N-type epitaxial layer formed on a P-type semiconductor substrate and an element isolation oxide film formed around the N-type epitaxial layer. A semiconductor device, wherein an insulating film for a capacitor and a conductor film are formed on an epitaxial layer at an interface of the film.