JPS61159741A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61159741A JPS61159741A JP28144784A JP28144784A JPS61159741A JP S61159741 A JPS61159741 A JP S61159741A JP 28144784 A JP28144784 A JP 28144784A JP 28144784 A JP28144784 A JP 28144784A JP S61159741 A JPS61159741 A JP S61159741A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- insulating film
- semiconductor
- back side
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 238000004519 manufacturing process Methods 0.000 title claims description 32
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 30
- 239000012535 impurity Substances 0.000 claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 229920005591 polysilicon Polymers 0.000 claims abstract description 16
- 238000009792 diffusion process Methods 0.000 claims abstract description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 8
- 229910052698 phosphorus Inorganic materials 0.000 claims description 8
- 239000011574 phosphorus Substances 0.000 claims description 8
- 238000005247 gettering Methods 0.000 abstract description 20
- 230000000694 effects Effects 0.000 abstract description 10
- 238000010438 heat treatment Methods 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910001385 heavy metal Inorganic materials 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 abstract description 2
- 230000002950 deficient Effects 0.000 abstract description 2
- 229910052750 molybdenum Inorganic materials 0.000 abstract description 2
- 239000011733 molybdenum Substances 0.000 abstract description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052721 tungsten Inorganic materials 0.000 abstract description 2
- 239000010937 tungsten Substances 0.000 abstract description 2
- 230000008021 deposition Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical group ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は半導体装置の製造方法に関し、特に、ゲッタリ
ング専用工程が不要な半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device that does not require a step dedicated to gettering.
[従来の技術]
大規模集積回路等の半導体装置、特に、MOS型等の電
界効果を利用した例えばダイナミックRAM等のメモリ
装置や電荷結合素子(COD)等では、接合面における
リーク電流が小さく電荷保持時間が長いことが必須的要
件として要求されている。従って、半導体装置の製造に
あたって、これ等の緒特性を劣化させる主原因となる重
金属汚染の悪影響から回路素子を保護するために、多く
の場合、ゲッタリング工程を設けている。[Prior Art] Semiconductor devices such as large-scale integrated circuits, especially memory devices such as dynamic RAMs and charge-coupled devices (CODs) that use electric field effects such as MOS type, have small leakage current at the junction surface and are free of charge. A long retention time is required as an essential requirement. Therefore, in manufacturing semiconductor devices, a gettering process is often provided in order to protect circuit elements from the adverse effects of heavy metal contamination, which is the main cause of deterioration of these circuit characteristics.
第2図は、シリコン(St)ゲー トMOSデバイスの
従来から採用されている製造方法の一例を示すものであ
る。この製造方法では、先ず、半導体基板lを酸化して
絶縁膜2を形成する0通常、この工程で基板lの表面(
おちてめん−一回路素子を形成する側)と裏面の両面に
絶縁M2が形成される0次に1例えば気相成長法により
ポリシリコンを成長させる。この工程により、表面側の
絶縁膜2と裏面側の絶縁膜2の両方の上にポリシリコン
3と4が夫々形成される。そして、ポリシリコン3.4
にリンを拡散してポリシリコン3.4に導電性を付与し
てゲートを作る。その後、図示は省略するが、表面側に
ソースやドレインを形成する工程、ゲッタリング工程、
熱処理工程等の通常のMOSデバイス製造工程を行なう
。FIG. 2 shows an example of a conventional manufacturing method for silicon (St) gate MOS devices. In this manufacturing method, first, the semiconductor substrate l is oxidized to form the insulating film 2. Usually, in this step, the surface of the substrate l (
Polysilicon is grown by, for example, vapor phase growth, in which an insulating layer M2 is formed on both sides (the side on which a circuit element is formed) and the back side. Through this step, polysilicon 3 and 4 are formed on both the insulating film 2 on the front side and the insulating film 2 on the back side, respectively. And polysilicon 3.4
The polysilicon 3.4 is made conductive by diffusing phosphorus into the polysilicon 3.4 to form a gate. After that, although not shown, a step of forming a source and a drain on the surface side, a gettering step,
A normal MOS device manufacturing process such as a heat treatment process is performed.
ゲッタリング工程としては、例えば次の様なものがある
。Examples of the gettering process include the following.
!゛裏面側にP OCl、 のプレデポジション等に
よりリン拡散を行ない、SiPを形成することによって
歪を生成し、その後の熱処理により基板中に含まれる重
金属をこの歪に捕捉させる。! Phosphorus is diffused on the back side by pre-deposition of POCl, etc. to form SiP to generate strain, and heavy metals contained in the substrate are captured by the strain through subsequent heat treatment.
・り)ス面偏にポリシリコンを成長させ、そのストレス
により基板に格子欠陥領域を形成し、その後の熱処理に
より基板中に含まれる重金属をこの欠陥部分に捕捉させ
る。・Ri) Polysilicon is grown on an uneven surface, the stress of which forms a lattice defect region in the substrate, and the heavy metals contained in the substrate are trapped in this defect region by subsequent heat treatment.
これ等のゲッタリング工程は、いずれも裏面側に選択的
に処理を行なう必要がある為、表面側の回路素子形成後
に、専用の一連の工程が必要になる0例えば、上記■で
は1回路素子が形成しである表面側にリン拡散が行なわ
れないように、少くとも、表面側に酸化シリコン膜等の
マスクを形成する工程と、プレデポジション後にこのマ
スクを除去する工程とが必要である。また、上記(多で
は1回路素子が形成しである表面側にポリシリコンが形
成されないように、少くとも、表面に被覆膜を形成する
工程と、ポリシリコン形成後に該被覆膜を除去する工程
とが必要である。In all of these gettering processes, it is necessary to selectively process the back side, so a series of dedicated processes are required after the formation of the circuit elements on the front side. In order to prevent phosphorus from being diffused on the surface side where phosphorus is formed, at least a step of forming a mask such as a silicon oxide film on the surface side and a step of removing this mask after pre-deposition are required. In addition, in order to prevent polysilicon from being formed on the surface side where one circuit element is formed, at least the step of forming a coating film on the surface and removing the coating film after forming the polysilicon. process is required.
上述したように、半導体装置の製造、特に電界効果型の
半導体装置の製造においては、ゲッタリング工程が不可
欠である。しかも、従来の製造方法では、ゲッタリング
の為の一連の専用工程が必要である為、半導体製造工程
数が多くなり、半導体装置の製造コストを上昇させる原
因になっている。As described above, a gettering process is essential in the manufacture of semiconductor devices, particularly in the manufacture of field-effect semiconductor devices. Moreover, the conventional manufacturing method requires a series of dedicated steps for gettering, which increases the number of semiconductor manufacturing steps, which causes an increase in the manufacturing cost of semiconductor devices.
[発明の目的]
本発明の目的は、ゲッタリング専用工程を廃して他の製
造工程で同時にゲッタリングを行なうようにし、製造工
程数を減少させて製造コストの低廉価を図ることができ
る半導体装置の製造方法を提供することにある。[Object of the Invention] An object of the present invention is to provide a semiconductor device that eliminates a process dedicated to gettering and simultaneously performs gettering in other manufacturing processes, thereby reducing the number of manufacturing processes and reducing manufacturing costs. The purpose of this invention is to provide a method for manufacturing the same.
[発明の構成]
上記目的を達成すべく、本発明の半導体装置の製造方法
では、半導体基板に絶縁膜を形成する工程の後に、半導
体基板の裏面側に形成された絶縁膜を除去する工程を設
ける構成にする。[Structure of the Invention] In order to achieve the above object, the method for manufacturing a semiconductor device of the present invention includes a step of removing an insulating film formed on the back side of the semiconductor substrate after a step of forming an insulating film on a semiconductor substrate. Configure the system to be set up.
[発明の作用]
本発明の半導体装置の製造方法は、上記のように、半導
体基板の裏面側の絶縁膜を製造工程の初期の段階で除去
してしまうので、その後の通常の製造工程で行なわれる
多結晶半導体の成長により、半導体基板にストレスを与
えることができる。つまり、バッファとして作用してし
まう基板裏面側の絶縁膜が無い為、多結晶半導体成長工
程とその後の熱処理工程により同時にゲッタリングがな
される。また、不純物拡散のストッパと1て作用する絶
縁膜が基板の裏側に無い為、多結晶半導体成長工程後の
不純物拡散工程により、不純物が基板の裏側から多結晶
半導体を通して基板内にも拡散し、その後の熱処理工程
によりゲッタリングがなされる。[Operation of the Invention] As described above, in the method for manufacturing a semiconductor device of the present invention, the insulating film on the back side of the semiconductor substrate is removed at an early stage of the manufacturing process, so that it is not removed in the subsequent normal manufacturing process. Stress can be applied to the semiconductor substrate by the growth of the polycrystalline semiconductor. In other words, since there is no insulating film on the back side of the substrate that acts as a buffer, gettering is performed simultaneously during the polycrystalline semiconductor growth process and the subsequent heat treatment process. In addition, since there is no insulating film on the back side of the substrate that acts as a stopper for impurity diffusion, impurities diffuse into the substrate from the back side of the substrate through the polycrystalline semiconductor during the impurity diffusion process after the polycrystalline semiconductor growth process. Gettering is performed by the subsequent heat treatment process.
従って、ゲッタリングの為の専用工程が不要となる。Therefore, a dedicated process for gettering becomes unnecessary.
尚、裏面側に多結晶半導体が成長しない場合は、多結晶
半導体の付着によるゲッタリング効果は無くて不純物に
よるゲッタリング効果のみとなり、裏面側に不純物拡散
ができない場合は、不純物によるゲッタリング効果は無
くて多結晶半導体の付着によるゲッタリング効果のみと
なることは当然である。しかし、一般の半導体装置製造
方法では、基板の両面に多結晶半導体成長と不純物拡散
がなされるので、両方のゲッタリング効果が得られる。Note that if the polycrystalline semiconductor does not grow on the back side, there will be no gettering effect due to the attachment of the polycrystalline semiconductor, but only the gettering effect due to impurities.If the impurity cannot be diffused to the back side, there will be no gettering effect due to the impurities. It is natural that the only gettering effect due to the attachment of the polycrystalline semiconductor will be obtained without it. However, in a general semiconductor device manufacturing method, polycrystalline semiconductor growth and impurity diffusion are performed on both sides of the substrate, so both gettering effects can be obtained.
[発明の実施例]
以下、本発明の半導体装置製造方法の一実施例を第1図
に基づいて説明する。[Embodiments of the Invention] An embodiment of the semiconductor device manufacturing method of the present invention will be described below with reference to FIG.
先ず、絶縁膜形成工程では、半導体、例えばシリコン(
S i)で成る基板lに絶t&膜2を形成する。この絶
縁膜2の形成は、例えば基板lを酸化することにより行
ない、これにより基板lの両面に酸化シリコン(SfO
l)膜が形成される。First, in the insulating film formation step, a semiconductor such as silicon (
An insulation film 2 is formed on a substrate 1 made of Si). The insulating film 2 is formed by, for example, oxidizing the substrate 1, so that silicon oxide (SfO) is formed on both sides of the substrate 1.
l) A film is formed.
次に、本発明に係る裏面絶縁膜除去工程を行なう、この
工程では、前工程で形成された絶縁膜2の内、基板lの
裏面側の絶縁膜2を除去し、半導体基板1を露出させる
。Next, a back insulating film removal step according to the present invention is performed. In this step, of the insulating film 2 formed in the previous step, the insulating film 2 on the back side of the substrate l is removed to expose the semiconductor substrate 1. .
次に、通常の半導体装l製造方法で行なわれる多結晶半
導体成長工程を行なう、これは、例えば、気相成長法に
よりポリシリコンを成長させる。これにより、絶縁膜2
の上に例えばポリシリコンで成るゲート用の膜3が配線
される。また、基板lの裏面側には、直接ポリシリコン
Ill 4が成長し、このポリシリコン膜4が基板1に
ストレスを与える。Next, a polycrystalline semiconductor growth step performed in a normal semiconductor device manufacturing method is performed, which involves growing polysilicon by, for example, a vapor phase growth method. As a result, the insulating film 2
A gate film 3 made of polysilicon, for example, is wired thereon. Further, polysilicon film 4 is directly grown on the back side of substrate 1, and this polysilicon film 4 gives stress to substrate 1.
更に、例えばゲート用の1l13に導電性を付与する為
、不純物を拡散する工程を行なう、これは、例えば、F
oci、のプレデポジションやリンガラス(psc)膜
からの拡散により行なう、このリン等の不純物拡散は裏
面側にもなされ、リン等の不純物は、ポリシリコン膜4
を通して基板l内にも拡散する。Furthermore, in order to impart conductivity to 1l13 for the gate, a process of diffusing impurities is performed, for example, by F
This diffusion of impurities such as phosphorus, which is performed by pre-deposition of oxidation silicon or by diffusion from the phosphorus glass (psc) film, is also carried out on the back side, and the impurities such as phosphorus are
It also diffuses into the substrate l.
その後、通常の半導体装置製造工程である熱処理を行な
うと、前記ストレスに基づいて生成される欠陥領域や、
基板l内にSiP等ができることによって生ずる歪に、
基板l内に含まれているモリブデン(Mo)、タングス
テン(W)等の重金属が捕捉される。After that, when heat treatment, which is a normal semiconductor device manufacturing process, is performed, defective areas generated based on the stress,
Due to the distortion caused by the formation of SiP etc. in the substrate l,
Heavy metals such as molybdenum (Mo) and tungsten (W) contained in the substrate 1 are captured.
このようにして、本実施例では、多結晶半導体成長と不
純物拡散とにより、2重のゲッタリング効果が得られる
。In this way, in this embodiment, a double gettering effect can be obtained by polycrystalline semiconductor growth and impurity diffusion.
なお、当然のことではあるが、本発明は図示の実施例に
のみ限定されるものではない。It should be noted that, as a matter of course, the present invention is not limited to the illustrated embodiment.
[発明の効果]
上述の如く、本発明の半導体装置の製造方法では、製造
工程の初期の段階において、半導体基板裏面側の絶縁膜
を除去する一工程を追加しただけで、ゲッタリング専用
工程が不要となるという優れた効果がある。このため、
半導体装置の製造工程数が減少し、製造コストの低廉価
を達成することができる。[Effects of the Invention] As described above, in the semiconductor device manufacturing method of the present invention, only one step of removing the insulating film on the back side of the semiconductor substrate is added at the initial stage of the manufacturing process, and a gettering-dedicated step is eliminated. This has the excellent effect of making it unnecessary. For this reason,
The number of manufacturing steps for semiconductor devices is reduced, and manufacturing costs can be reduced.
2・・・絶縁膜、 3.4・・・多結晶半導体膜。2... Insulating film, 3.4... Polycrystalline semiconductor film.
特許出願人ニソ ニ −株 式 会 杜氏 理 人
: 弁 理 士 高 月 亨第 1
目Patent applicant Nisoni Co., Ltd. Chief brewer Manager: Patent attorney Toru Takatsuki 1
eye
Claims (1)
を形成した半導体基板に多結晶半導体を成長させる工程
と、前記多結晶半導体に不純物を拡散させる工程とを備
える半導体装置の製造方法において、前記絶縁膜を形成
する工程の後に、半導体基板の裏側に形成された絶縁膜
を除去する工程を設け、該工程の後に前記多結晶半導体
成長工程あるいは不純物拡散工程を行なうことを特徴と
する半導体装置の製造方法。 2、前記多結晶半導体はポリシリコンであることを特徴
とする特許請求の範囲第1項記載の半導体装置の製造方
法。 3、前記不純物はリンであることを特徴とする特許請求
の範囲第1項記載の半導体装置の製造方法。、[Scope of Claims] 1. A method comprising the steps of forming an insulating film on a semiconductor substrate, growing a polycrystalline semiconductor on the semiconductor substrate on which the insulating film is formed, and diffusing impurities into the polycrystalline semiconductor. In the method for manufacturing a semiconductor device, after the step of forming the insulating film, a step of removing the insulating film formed on the back side of the semiconductor substrate is provided, and after the step, the polycrystalline semiconductor growing step or the impurity diffusion step is performed. A method for manufacturing a semiconductor device, characterized in that: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the polycrystalline semiconductor is polysilicon. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity is phosphorus. ,
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28144784A JPS61159741A (en) | 1984-12-31 | 1984-12-31 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28144784A JPS61159741A (en) | 1984-12-31 | 1984-12-31 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61159741A true JPS61159741A (en) | 1986-07-19 |
Family
ID=17639298
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP28144784A Pending JPS61159741A (en) | 1984-12-31 | 1984-12-31 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61159741A (en) |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4935384A (en) * | 1988-12-14 | 1990-06-19 | The United States Of America As Represented By The United States Department Of Energy | Method of passivating semiconductor surfaces |
EP0373723A1 (en) * | 1988-12-16 | 1990-06-20 | STMicroelectronics S.r.l. | Method for manufacturing a MOS semiconductor device making use of a "gettering" treatment with improved characteristics, and MOS semiconductor devices obtained thereby |
US5189508A (en) * | 1988-03-30 | 1993-02-23 | Nippon Steel Corporation | Silicon wafer excelling in gettering ability and method for production thereof |
US5227314A (en) * | 1989-03-22 | 1993-07-13 | At&T Bell Laboratories | Method of making metal conductors having a mobile inn getterer therein |
US5354710A (en) * | 1988-01-14 | 1994-10-11 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor devices using an adsorption enhancement layer |
US5444001A (en) * | 1992-12-25 | 1995-08-22 | Nec Corporation | Method of manufacturing a semiconductor device readily capable of removing contaminants from a silicon substrate |
US5874325A (en) * | 1995-10-25 | 1999-02-23 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device with gettering and isolation |
US5895236A (en) * | 1996-10-18 | 1999-04-20 | Nec Corporation | Semiconductor device fabricating method having a gettering step |
GB2368464A (en) * | 1999-02-02 | 2002-05-01 | Nec Corp | Removing crystal originated particles from Czochralski silicon substrates |
US6448157B1 (en) | 1999-02-02 | 2002-09-10 | Nec Corporation | Fabrication process for a semiconductor device |
US6936897B2 (en) * | 1997-11-18 | 2005-08-30 | Micron Technology, Inc. | Intermediate structure having a silicon barrier layer encapsulating a semiconductor substrate |
JP2006294772A (en) * | 2005-04-08 | 2006-10-26 | Fuji Electric Holdings Co Ltd | Manufacturing method of semiconductor device |
JP2010232539A (en) * | 2009-03-27 | 2010-10-14 | Canon Inc | Method of manufacturing semiconductor device, and method of manufacturing photoelectric conversion device |
-
1984
- 1984-12-31 JP JP28144784A patent/JPS61159741A/en active Pending
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5354710A (en) * | 1988-01-14 | 1994-10-11 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor devices using an adsorption enhancement layer |
US5189508A (en) * | 1988-03-30 | 1993-02-23 | Nippon Steel Corporation | Silicon wafer excelling in gettering ability and method for production thereof |
US4935384A (en) * | 1988-12-14 | 1990-06-19 | The United States Of America As Represented By The United States Department Of Energy | Method of passivating semiconductor surfaces |
EP0373723A1 (en) * | 1988-12-16 | 1990-06-20 | STMicroelectronics S.r.l. | Method for manufacturing a MOS semiconductor device making use of a "gettering" treatment with improved characteristics, and MOS semiconductor devices obtained thereby |
US5227314A (en) * | 1989-03-22 | 1993-07-13 | At&T Bell Laboratories | Method of making metal conductors having a mobile inn getterer therein |
US5444001A (en) * | 1992-12-25 | 1995-08-22 | Nec Corporation | Method of manufacturing a semiconductor device readily capable of removing contaminants from a silicon substrate |
US5874325A (en) * | 1995-10-25 | 1999-02-23 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device with gettering and isolation |
US5895236A (en) * | 1996-10-18 | 1999-04-20 | Nec Corporation | Semiconductor device fabricating method having a gettering step |
US6936897B2 (en) * | 1997-11-18 | 2005-08-30 | Micron Technology, Inc. | Intermediate structure having a silicon barrier layer encapsulating a semiconductor substrate |
GB2368464A (en) * | 1999-02-02 | 2002-05-01 | Nec Corp | Removing crystal originated particles from Czochralski silicon substrates |
US6448157B1 (en) | 1999-02-02 | 2002-09-10 | Nec Corporation | Fabrication process for a semiconductor device |
GB2368464B (en) * | 1999-02-02 | 2002-10-16 | Nec Corp | Semiconductor device and fabrication process therefor |
JP2006294772A (en) * | 2005-04-08 | 2006-10-26 | Fuji Electric Holdings Co Ltd | Manufacturing method of semiconductor device |
JP2010232539A (en) * | 2009-03-27 | 2010-10-14 | Canon Inc | Method of manufacturing semiconductor device, and method of manufacturing photoelectric conversion device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPH05102427A (en) | Manufacture of semiconductor memory element | |
JPS61159741A (en) | Manufacture of semiconductor device | |
JPS63257231A (en) | Manufacture of semiconductor device | |
JPS58138035A (en) | Semiconductor device and manufacture thereof | |
JPH0897172A (en) | Semiconductor device | |
JPH0350730A (en) | Semiconductor device | |
JPH07176742A (en) | Manufacture of semiconductor device and semiconductor device | |
JPH05218072A (en) | Manufacture of semiconductor device | |
JPH01108772A (en) | Manufacture of bipolar transistor | |
JPS61248476A (en) | Manufacture of semiconductor device | |
JPH04142777A (en) | Forming method for gate electrode or wiring | |
JPS61258434A (en) | Manufacture of semiconductor device | |
JPS6262555A (en) | Semiconductor device | |
JPH05109736A (en) | Manufacture of semiconductor device | |
JPH04162519A (en) | Manufacture of mos semiconductor device | |
JP3282265B2 (en) | Method for manufacturing semiconductor device | |
KR0154191B1 (en) | Method of forming non-defect area for semiconductor device | |
JPS61154132A (en) | Manufacture of semiconductor device | |
JPH0380542A (en) | Semiconductor integrated circuit device | |
JPS5895868A (en) | Manufacturing method of semiconductor device | |
JPH04150037A (en) | Semiconductor device and its manufacturing method | |
JPS6118348B2 (en) | ||
JPS59205758A (en) | Transistor manufacturing method | |
JPH0529625A (en) | Method for forming gate oxide film and field effect transistor | |
JPS58153337A (en) | Manufacture of semiconductor device |