KR0154191B1 - Method of forming non-defect area for semiconductor device - Google Patents
Method of forming non-defect area for semiconductor device Download PDFInfo
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- KR0154191B1 KR0154191B1 KR1019940013494A KR19940013494A KR0154191B1 KR 0154191 B1 KR0154191 B1 KR 0154191B1 KR 1019940013494 A KR1019940013494 A KR 1019940013494A KR 19940013494 A KR19940013494 A KR 19940013494A KR 0154191 B1 KR0154191 B1 KR 0154191B1
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- 238000000034 method Methods 0.000 title claims abstract description 47
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 230000007547 defect Effects 0.000 title claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 30
- 229910052710 silicon Inorganic materials 0.000 claims description 30
- 239000010703 silicon Substances 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 30
- 238000010438 heat treatment Methods 0.000 claims description 19
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 13
- 239000001301 oxygen Substances 0.000 claims description 13
- 229910052760 oxygen Inorganic materials 0.000 claims description 13
- 239000007789 gas Substances 0.000 claims description 9
- 239000012298 atmosphere Substances 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 claims 1
- 229910001873 dinitrogen Inorganic materials 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000004904 shortening Methods 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 8
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
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- Formation Of Insulating Films (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
본 발명은 반도체 소자의 제조 공정에 이용되는 무결점 영역 형성방법에 관한 것으로, 소자 형성 공정과 별도로 진행되어 공정 시간이 많이 소요되는 점을 개선하기 위해 웰 영역 형성 공정부터 필드 산화막 형성 공정 사이에 실리콘 기판내에 무결점 영역이 형성되도록 상기 공정 시간 및 온도 조건을 개선하므로서 공정 시간의 단축으로 생산성을 증대시킬 수 있도록 한 반도체 소자의 무결점 영역 형성방법에 관한 것이다.The present invention relates to a method of forming a defect-free region used in a manufacturing process of a semiconductor device, and is performed separately from the device forming process to improve the point of time required for the process. The present invention relates to a method for forming a defect-free region of a semiconductor device in which productivity can be increased by shortening the process time by improving the process time and temperature conditions so that a defect-free region is formed in the same.
Description
제1 내지 제5도는 본 발명에 따른 반도체 소자의 무결점 영역 형성방법을 설명하기 위한 소자의 단면도.1 to 5 are cross-sectional views of devices for explaining a method for forming a defect-free region of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : 패드 산화막1 silicon substrate 2 pad oxide film
3 : 다결정 실리콘층 4 : 질화막3: polycrystalline silicon layer 4: nitride film
5 : 감광막 6 : 필드 산화막5: photosensitive film 6: field oxide film
7 : 무결점 영역 8 : 결점 영역7: defect area 8: defect area
본 발명은 반도체 소자의 무결점 영역 형성방법에 관한 것으로, 특히 반도체 소자의 제조 공정중 웰(well) 영역 형성 공정부터 필드 산화막(field oxide) 형성 공정 사이에 실리콘 기판내에 무결점 영역이 형성되도록 열처리 공정의 시간 및 온도 조건을 개선하므로서 별도의 추가 공정없이 무결점 영역이 형성되도록 한 반도체 소자의 무결점 영역 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a defect free region of a semiconductor device, and more particularly, to a method of forming a defect free region in a silicon substrate between a well region formation process and a field oxide formation process during a semiconductor device manufacturing process. The present invention relates to a method of forming a defect-free region of a semiconductor device in which a defect-free region is formed without improving an additional time and temperature conditions.
일반적으로 실리콘 기판에는 일정 농도의 산소가 포함되어 있으며, 실리콘 기판 전체에 존재하는 이 산소로 인해 공정시 결점(defect)이 형성된다. 이러한 결점을 OISF(Oxidation Induced Stacking Fault)라 하는데, 소자 형성 부위에 존재하게 되면 누설 전류(leakage current)를 증가시키기 때문에 소자 형성전 실리콘 기판내의 산소 농도를 감소시켜 OISF가 형성되지 못하는 무결점 영역을 형성시키고 소정 부위에 불순물(impurity)이 모이도록 하여 결점 영역을 형성시켜야 한다.Generally, a silicon substrate contains a certain concentration of oxygen, and the oxygen present throughout the silicon substrate creates defects in the process. This defect is called Oxidation Induced Stacking Fault (OISF), and when present in the device formation site increases leakage current, it reduces the oxygen concentration in the silicon substrate before device formation to form a defect-free area where OISF cannot be formed. The defect area should be formed by collecting impurities at a predetermined site.
종래 반도체 소자의 무결점 영역 형성방법은 고온에서 실리콘 기판에 존재하는 산소(O2)를 외부 확산(out diffusion)시키고, 저온에서 핵을 생성(nucleation)시킨 다음 다시 고온에서 핵을 성장시키며, 불순물을 모으므로서 실리콘 기판내에 무결점 영역 및 결점 영역이 형성되었다. 그런데 이러한 공정은 소자 형성 공정과는 별도로 이루어지며 그 시간이 많이 소요되었다. 또한, 종래의 공정을 소자 형성공정과 병행하여 진행한다면 공정 시간이 부적당하게 되어 무결점 영역이 형성되지 않는다.In the conventional method of forming a defect-free region of a semiconductor device, oxygen (O 2 ) present in a silicon substrate is out-diffused at a high temperature, nucleated at a low temperature, and then grown at a high temperature, and impurities are removed. As a result, defect and defect regions were formed in the silicon substrate. However, this process is performed separately from the device formation process, and it took a lot of time. In addition, if the conventional process is carried out in parallel with the element formation process, the process time becomes inadequate and a defect free area is not formed.
따라서, 본 발명은 반도체 소자의 제조 공정중 실리콘 기판내에 무결점 영역이 형성되도록 공정 시간 및 온도 조건을 개선하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 무결점 영역 형성방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a defect-free region of a semiconductor device that can solve the above-mentioned disadvantages by improving process time and temperature conditions so that a defect-free region is formed in a silicon substrate during a semiconductor device manufacturing process.
상술한 목적을 달성하기 위한 본 발명은 고온의 가스 분위기에서 실리콘 기판상에 불순물 이온을 주입하고 소정 시간동안 열처리하여 웰 영역을 형성시킴과 동시에 실리콘 기판에 존재하는 산소가 외부 확산되는 단계와, 저온에서 다결정 실리콘층을 상기 실리콘 기판상에 형성된 패드 산화막 상부에 형성시킨 후 소정 시간동안 열처리 공정을 실시하고, 온도를 상승시켜 상기 다결정 실리콘층 상부에 질화막을 형성시키고 열처리 공정을 실시하므로서 상기 실리콘 기판내에 핵이 생성되는 단계와, 상기 질화막의 선택된 영역을 제거하고 고온 산화 공정으로 필드 산화막을 형성시킨 후 소정 시간동안 열처리 공정을 실시하므로서 핵이 성장되어 실리콘 기판내의 불순물이 소정의 영역에 모여 상기 실리콘 기판내에 무결점 영역 및 결점영역이 형성되는 단계를 포함하여 이루어진 것을 특징으로 한다.The present invention for achieving the above object is a step of implanting impurity ions on a silicon substrate in a high temperature gas atmosphere and heat treatment for a predetermined time to form a well region, and at the same time the oxygen existing in the silicon substrate is externally diffused, The polycrystalline silicon layer is formed on the pad oxide film formed on the silicon substrate, and the heat treatment process is performed for a predetermined time, the temperature is raised to form a nitride film on the polycrystalline silicon layer, and the heat treatment process is performed in the silicon substrate. The nucleus is grown by removing the selected region of the nitride film, forming a field oxide film by a high temperature oxidation process, and then performing a heat treatment process for a predetermined time so that impurities in the silicon substrate gather in a predetermined region. Defect area and defect area are formed within Characterized in that it comprises a step.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제1 내지 제5도는 본 발명에 따른 반도체 소자의 무결점 영역 형성방법을 설명하기 위한 소자의 단면도이다.1 to 5 are cross-sectional views of devices for explaining a method of forming a defect-free region of a semiconductor device according to the present invention.
제1도를 참조하면, 실리콘 기판(1)상에 불순물 이온을 주입하고 1000∼1100℃ 온도의 질소(N2) 가스 분위기에서 6∼10 시간동안 열처리하여 웰 영역을 형성시킨다. 이때, 실리콘 기판(1)에 존재하는 산소가 외부 확산되어 무결점 영역의 깊이가 정해지게 된다. 웰 영역이 형성된 실리콘 기판(1) 상부에 열산화막인 패드 산화막(2)을 형성한다.Referring to FIG. 1, impurity ions are implanted onto the silicon substrate 1 and heat-treated for 6 to 10 hours in a nitrogen (N 2 ) gas atmosphere at a temperature of 1000 to 1100 ° C. to form a well region. At this time, the oxygen present in the silicon substrate 1 is diffused outside to determine the depth of the defect-free region. A pad oxide film 2, which is a thermal oxide film, is formed on the silicon substrate 1 on which the well region is formed.
무결점 영역의 깊이는 온도, 시간, 가스 분위기 및 실리콘 기판의 산소 농도 등을 적절히 조정하여 원하는 깊이를 얻는다. 또한, N2가스 분위기 대신 아르곤(Ar) 가스 분위기를 조성하여도 동일한 결과를 얻을 수 있다.The depth of the defect-free region is appropriately adjusted by temperature, time, gas atmosphere and oxygen concentration of the silicon substrate to obtain a desired depth. In addition, the same result can be obtained even if argon (Ar) gas atmosphere is formed instead of N 2 gas atmosphere.
즉, 실리콘 기판에 존재하는 산소의 농도가 옅을수록, 시간 및 온도가 증가할수록 무결점 영역은 깊게 형성된다. 하지만, 실리콘 기판에 존재하는 산소의 농도가 너무 옅으면 무결점 영역이 형성되지 않고, 너무 짙으면 실리콘 기판의 크랙을 발생시킨다. 그러므로, 무결점 영역의 형성 깊이는 대부분 시간 및 온도에 의해 결정되고, N2또는 아르곤 가스는 분위기 조성 역할을 한다.That is, the lighter the concentration of oxygen present in the silicon substrate, the deeper the defect-free region is formed as time and temperature increase. However, if the concentration of oxygen present in the silicon substrate is too light, no defect-free region is formed, and if too high, cracking of the silicon substrate occurs. Therefore, the formation depth of the defect-free region is largely determined by time and temperature, and N 2 or argon gas serves as an atmosphere composition.
예를 들어, 실리콘 기판에 존재하는 산소의 농도가 15ppma이고, 1100℃의 온도와 질소 분위기에서 4시간동안 열처리하면 약 23㎛의 깊이로 무결점 영역이 형성되며, 같은 조건에서 온도만 1200℃로 상승시켜 열처리하면 약 40㎛의 깊이로 무결점 영역이 형성된다. 다른 예로서, 실리콘 기판에 존재하는 산소 농도가 18ppma이고, 1100℃의 온도와 질소 분위기에서 4시간 동안 열처리하면 약 10㎛의 깊이로 무결점 영역이 형성되고, 같은 조건에서 온도만 1200℃로 상승시켜 열처리하면 약 25㎛의 깊이로 무결점 영역이 형성된다.For example, the concentration of oxygen in the silicon substrate is 15ppma, and heat treatment for 4 hours at a temperature of 1100 ° C. and a nitrogen atmosphere forms a defect free area at a depth of about 23 μm, and only the temperature rises to 1200 ° C. under the same conditions. After heat treatment, a defect free area is formed at a depth of about 40 μm. As another example, the oxygen concentration present in the silicon substrate is 18ppma, heat treatment for 4 hours at a temperature of 1100 ℃ and a nitrogen atmosphere to form a defect-free region to a depth of about 10㎛, under the same conditions only raise the temperature to 1200 ℃ The heat treatment results in the formation of a defect free area to a depth of about 25 μm.
제2도를 참조하면, 패드 산화막(2) 상부에 600∼650℃ 온도의 반응로내에서 분리(isolation) 공정으로 변형된 LOCOS 공정중 완충 작용을 하는 다결정 실리콘층(3)을 예를들어 400∼600Å의 두께로 형성시킨다. 4∼6시간동안 열처리한 후 온도를 750∼800℃로 상승시킨 상태에서 질화막(4)을 예를들어 1000∼3000Å의 두께로 형성시킨다. 열처리 공정을 실시한 후 필드 산화막을 형성시키기 위해 감광막(5)을 형성시키고 패터닝한다.Referring to FIG. 2, for example, a polycrystalline silicon layer 3 having a buffering function in a LOCOS process modified by an isolation process in a reactor at a temperature of 600 to 650 ° C. above the pad oxide layer 2 may be, for example, 400. It is formed to a thickness of ˜600 Pa. After the heat treatment for 4 to 6 hours, the nitride film 4 is formed to a thickness of, for example, 1000 to 3000 kPa while the temperature is raised to 750 to 800 ° C. After performing the heat treatment process, the photosensitive film 5 is formed and patterned to form a field oxide film.
이때, 다결정 실리콘층(3) 및 질화막(4) 형성시의 열처리 공정에 의해 핵이 생성되며 핵의 정도가 결정된다.At this time, a nucleus is generated by the heat treatment step in forming the polycrystalline silicon layer 3 and the nitride film 4, and the degree of the nucleus is determined.
제3도는 패터닝된 감광막(5)을 이용한 건식식각 공정에 의해 질화막(4)의 선택된 영역을 식각하고, 패터닝된 감광막(5)을 제거한 단면도이다.3 is a cross-sectional view of etching the selected region of the nitride film 4 by the dry etching process using the patterned photosensitive film 5 and removing the patterned photosensitive film 5.
제4도는 튜브내의 온도를 1000∼1200℃로 상승시켜 산화 공정을 실시하여 필드 산화막(6)을 형성시킨 단면도이다.4 is a sectional view in which the field oxide film 6 is formed by performing an oxidation process by raising the temperature in the tube to 1000 to 1200 ° C.
제5도는 고온 산화 공정으로 필드 산화막(6)을 형성시킨 후 6∼8시간동안 열처리 공정을 실시하면 핵의 성장이 이루어져 실리콘 기판(1)내의 불순물이 소정의 영역에 모이게 되어 무결점 영역(7) 및 결정 영역(8)이 형성된 단면도로서, 이때 결점의 크기가 결정된다.FIG. 5 shows that the field oxide film 6 is formed by a high temperature oxidation process and then subjected to a heat treatment process for 6 to 8 hours, whereby nuclei are grown and impurities in the silicon substrate 1 are collected in a predetermined region. And a sectional view in which the crystal region 8 is formed, wherein the size of the defect is determined.
상술한 바와 같이 본 발명에 의하면 소자의 형성 공정과 동시에 무결점 영역의 형성 공정이 실시되므로 반도체 소자의 제조 공정 및 시간을 줄일 수 있어 생산성을 향상시킬 수 있다. 또한, 소자의 접합(junction) 영역에 결함(defect)이 없으므로 접합 누설(junction leakage)의 감소를 가져오며, 이로 인해 리프레쉬 시간(refresh time)이 증가된다.As described above, according to the present invention, the process of forming the defect-free region is performed at the same time as the process of forming the device, thereby reducing the manufacturing process and time of the semiconductor device and improving productivity. In addition, since there is no defect in the junction region of the device, the junction leakage is reduced, thereby increasing the refresh time.
Claims (4)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940013494A KR0154191B1 (en) | 1994-06-15 | 1994-06-15 | Method of forming non-defect area for semiconductor device |
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| KR1019940013494A KR0154191B1 (en) | 1994-06-15 | 1994-06-15 | Method of forming non-defect area for semiconductor device |
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| Publication Number | Publication Date |
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| KR960002474A KR960002474A (en) | 1996-01-26 |
| KR0154191B1 true KR0154191B1 (en) | 1998-12-01 |
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