JPS6115589B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor integrated circuit in which an opening for taking out an electrode can be provided in a self-aligned manner.

Conventionally, a semiconductor substrate has a high concentration region and a low concentration region (for simplicity, the former will be referred to as a P ⁺ region and the latter as a P region, and we will discuss the P-type conductive region, but the exact same discussion applies to the N-type). The following steps were taken to connect and form the . That is, first, a P region is formed by selectively removing a protective film such as an oxide film on the substrate surface, and then diffusing impurities, and then forming the P region through the opening in the protective film by photolithography.
A P ⁺ region was formed. (This order may be reversed.) Also, the opening for taking out the electrode on the surface of the P ⁺ region was created through a new photolithography process.
Therefore, according to the conventional method, (1) diffusion (or ion implantation) and oxidation steps are required to form P ⁺ and P regions, respectively.
times I needed it. For this reason, it has disadvantages in that the process is long, that it is difficult to form shallow junctions because of the large number of heat treatments, and that it is easy to induce the generation of crystal defects. Furthermore, according to the conventional method, (2) the overlap between P ⁺ and P areas requires consideration of alignment accuracy in the photo ^- etching process;
It has been difficult to reduce the device area, including the accuracy of alignment when providing an opening for taking out the electrode on the region.

An object of the present invention is to provide a method for manufacturing a semiconductor device that eliminates the drawbacks (1) and (2) of the above-mentioned conventional methods.

The present invention is characterized by a method for manufacturing a semiconductor device in which an emitter region of an opposite conductivity type is formed in a low impurity concentration portion of a base region of one conductivity type, and a base electrode is attached to a high impurity concentration portion of the base region. ,
A step of depositing a diffusion source film containing impurities of one conductivity type over the entire area on the surface of the semiconductor substrate where the base region is formed, and forming an oxidation-resistant film such as a Si ₃ N ₄ film on the diffusion source film. a step of introducing an impurity of one conductivity type into the semiconductor substrate from the diffusion source coating by applying a first heat treatment;
A step of leaving a part of the oxidation-resistant film and a part of the diffusion source film thereunder, and removing the other part of the oxidation-resistant film and the diffusion source film, and performing a second heat treatment, A step of reintroducing an impurity of one conductivity type into the semiconductor substrate from the remaining portion of the diffusion source film, and a low impurity concentration portion and a high impurity concentration portion of the base region formed by the first and second heat treatment steps. A process of forming an emitter region of the opposite conductivity type in the low impurity concentration part of the impurity concentration part, and removing the remaining oxidation-resistant film and diffusion source film, thereby removing the high impurity of the exposed base region. A method of manufacturing a semiconductor device includes a step of depositing a base electrode on a surface of a concentrated portion. Here, the semiconductor substrate in the present invention refers to the semiconductor substrate itself or a semiconductor region used for forming elements such as a semiconductor layer provided on this substrate.

According to the present invention, P ⁺ and P regions or
N ⁺ and N regions can be formed, and electrode extraction openings on the P ⁺ region can also be provided without going through the photolithography process. Therefore, the process is short, the heat treatment process is small, and the P ⁺ There is no need for alignment accuracy between the (or N ⁺ ) and P (or N) regions, and between the P ⁺ (or N ⁺ ) regions and the electrode extraction openings.

Hereinafter, the present invention will be explained in detail based on an embodiment using FIG. 1. In this embodiment, a bipolar integrated circuit is used as an example. A buried layer 102 selectively containing arsenic (As) as an impurity in a P-type Si substrate 101
After forming the layer a, an N-type epitaxial layer 103 is formed. After that, silicon nitride film (Si ₃ N ₄ film) 105
Selective oxidation is performed using a and 105b as a mask, and mutual insulation is achieved with a thick SiO ₂ film 104. Next, a photoresist 106 is provided in a photolithography process to provide an opening for collector diffusion. (Fig. 1a) Next, the Si ₃ N ₄ film 105b is removed by plasma etching, and the thin SiO ₂ film 104'' underneath is removed, followed by collector diffusion and oxidation steps to form the collector region 102b. (Fig. 1b) Next, after removing the Si ₃ N ₄ film 105a and the thin SiO ₂ film 104' below it, the Si 3 N 4 film 105a is removed by a normal vapor phase diffusion method.
A B ₂ O ₃ film 107 with a thickness of about 500 Å is formed at 900° C., and a Si ₃ N ₄ film 108 with a thickness of 1000 Å is further formed thereon. Thereafter, heat treatment is performed at 1000° C. in O ₂ for 20 minutes to form a P-type region 109 having a layer resistance of about 100Ω/□.

Thereafter, a photoresist 110 is provided through a photolithography process for the P ⁺ region. (Fig. 1c) Next, the Si ₃ N ₄ film was selectively removed by plasma etching, and the B ₂ O ₃ film 107 was further selectively removed, and then the film was exposed to H 2 O at 1000° C. in O ₂ for ₁ hour. Selective thermal oxidation was performed for 1 hour to remove P ⁺ region 111 and P region 11.
2 is formed simultaneously. As a result, the layer resistance of the P ⁺ region is 30Ω/□ and the junction depth is about 0.7μ, and the layer resistance of the P region is about 1KΩ/□ and the junction depth is 0.5μ. (1st
Figure d) Next, after opening the SiO ₂ film through a photolithography process to further form an emitter region in the P region 112, a P ₂ O ₅ film 113 is formed at 900°C by a normal vapor phase diffusion method. At the same time, N ⁺ type emitter region 11
form 4. The depth of the emitter junction of this cord is approximately
It is 0.3μ. At this time, normally the collector area 102
b is opened again at the same time and diffused. (Fig. 1e) After that, after removing the P ₂ O ₅ film 113, the film was heated to a thickness of 200 Å at a low temperature.
A SiO ₂ film of about 100% is formed on the surfaces of the emitter region 114 and the collector region 102b. (FIG. 1f) Next, the Si ₃ N ₄ film 108 is removed with hot phosphoric acid. At this time, the surfaces of the emitter region and collector region are protected by the SiO ₂ film of about 200 Å. then
At the same time as removing the B ₂ O ₃ film 107, the thin SiO ₂ film on the surface of the emitter region is also removed. Collector electrode 115, base electrode 116, emitter electrode 117
is provided by metal vapor deposition or etching. (Fig. 1g) As described above, according to the present invention, compared to the conventional method, the number of steps can be significantly reduced, and at the same time, all alignment, including the opening for taking out the electrode, can be done by self-alignment in the high-concentration and low-concentration regions. A structure in which the two are connected can be obtained, making it possible to significantly improve yield and significantly reduce the element dimensions required for highly integrated circuits.

In the above explanation, the present invention was applied to the manufacture of NPN bipolar transistors, but the present invention is not limited to the above-mentioned embodiments. It can be widely applied when forming concentration regions in a connected manner.

[Brief explanation of the drawing]

FIGS. 1a to 1g are cross-sectional views at main steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. In the figure, 101... semiconductor substrate, 106, 110... photoresist, 102a... As buried layer, 111
... P ⁺ type diffusion region, 102b ... Collector region, 112 ... P type diffusion region, 103 ... Epitaxial layer, 113 ... P ₂ O ₅ film, 104 ... Insulating oxide film, 114 ... N ⁺ Type emitter area, 10
5,108 _{... Si3N4} film, 115,116,11
7... Electrode, 107... B ₂ O ₃ film, 109... P
type diffusion region.

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor device in which an emitter region of an opposite conductivity type is formed in a low impurity concentration portion of a base region of one conductivity type, and a base electrode is deposited on a high impurity concentration portion of the base region. A step of depositing a diffusion source film containing an impurity of one conductivity type over the entire area where the base region is formed, a step of providing an oxidation-resistant film on the diffusion source film, and a first heat treatment. By introducing impurities of one conductivity type into the semiconductor substrate from the diffusion source coating, and leaving a portion of the oxidation-resistant film and the portion of the diffusion source coating thereunder, the other oxidation-resistant a step of removing the film and a portion of the diffusion source coating, and a step of reintroducing impurities of one conductivity type into the semiconductor re-boarding from the remaining portion of the diffusion source coating by applying a second heat treatment; forming an emitter region of an opposite conductivity type in the low impurity concentration portion of the low impurity concentration portion and the high impurity concentration portion of the base region formed by the first and second heat treatment steps; 1. A method of manufacturing a semiconductor device, comprising the steps of removing a portion of an oxidation-resistant film and a diffusion source film, and depositing a base electrode on the surface of the exposed high impurity concentration portion of the base region.