JPS61154156A - semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit having field effect transistors as constituent elements.

(Prior art) Conventionally, M
Oa type semiconductor integrated circuits require an element isolation region formed by selective oxidation or the like and covered with a thick insulating film such as a silicon dioxide film around the element formation region. For this reason, in the conventional MOa type semiconductor integrated circuit, the degree of integration is reduced by the area of the 13 element isolation regions.

(2) The manufacturing process is complicated and long except for the step of forming the element isolation region, and the yield and productivity are reduced.

(3) Unevenness occurs on the substrate surface due to the element isolation region, making it difficult to form fine patterns.

There were other drawbacks.

An object of the present invention is to solve the above-mentioned drawbacks by combining field-effect transistors whose gate electrodes are closed in an annular shape, and to provide a semiconductor integrated circuit that is easy to manufacture and does not require an element isolation region.

(Next Means for Solving the Problems) The semiconductor integrated circuit of the present invention includes a first gate electrode having a closed annular structure and a first source (or A first (D) field effect transistor is provided, which includes a first drain (source) region provided inside the first gate electrode, and a first drain (source) region provided inside the first gate electrode. a second gate electrode having a closed annular structure and a second gate electrode on the outside of the second gate electrode;
0 source (or drain) region and a second drain (or source) region inside the second gate electrode. n+1 field-effect transistor having an annular gate electrode structure in the drain region of the field-effect transistor (an integer)
The device structure is characterized in that a device structure including field effect transistors is combined as a basic unit, and the source region of the first electrode effect transistor of each basic unit is shared.

(Example) Next, embodiments of the present invention will be described using the drawings.

FIG. 2 is a circuit diagram of a circuit to which an embodiment of the present invention is applied.

In FIG. 2, 5QitQz is an N-channel type degressive MlfJM field effect transistor, Q3°Q4. Q
1g is a double enhancement type field effect transistor, 6 is a power supply line, 7 is a common potential line, 8.9 is an input line, and 10 is an output line.

FIG. 1 is a plan view and a cross-sectional view taken along line xx' of an embodiment of the present invention.

In this embodiment, the circuit shown in FIG. 2 is realized on a semiconductor substrate.

After nine years, a silicon dioxide film 12, which will become a gate insulating film, is formed on one main surface of the P-type semiconductor single crystal substrate 11.

Annular gate electrode l made of polycrystalline silicon film, 2°3.
N-type layers 13, 14, which will become source or drain regions are formed in the substrate 1 by using the polycrystalline silicon 7 film as a mask for ion implantation.
15, 16, 17, and 18 are formed, and then a silicon dioxide film 19 is laminated on the entire surface by vapor phase growth, and then through holes 20 are provided to lead out the gate electrode, source and drain regions to the surface. , finally aluminum plate 4
This is realized by providing 16.7.8.9.21.

□ In this embodiment, the gate electrodes 3, 4.5 are closed in an annular shape, and the outside of the gate electrode ring p is the source region 13°, and the inside 14, 16.18 is the drain region.
A type field effect transistor is an, drain region 1
In 4.16, a deplane type field effect transistor in which the gate electrode 1.2 is closed in an annular shape is formed.
By combining 93 device structures as a basic unit surrounded by gate electrodes 3, 4, 5, the source regions of the field effect transistors of each basic unit are at a common potential 13, and the present invention It can be seen that the characteristics of

As can be seen from FIGS. 1(a) and 1(b), there is no element isolation region in this embodiment. Therefore, since the manufacturing process and area of the butter 7 for forming the element isolation region are not necessary, the semiconductor integrated circuit of the present invention can improve the yield and the degree of integration.

By connecting the gate electrodes 3 and 5 of the enhancement type field effect transistors to a common potential, the transistors Ql and Qz formed inside the electrodes 3 and 5 are connected to the transistors Ql and Qz formed outside the electrodes 3 and 5. Furthermore, the present invention is capable of electrically isolating a semiconductor element from a semiconductor element formed on a compound semiconductor substrate such as gallium arsenide (GaAs).
Needless to say, the present invention can also be applied to integrated circuits that use a Cutkey barrier.

(Effects of the Invention) The present invention provides a semiconductor integrated circuit which eliminates the need for element isolation regions and improves the degree of integration and yield by combining field effect transistors having an annular gate electrode. can be realized.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are a plan view and a sectional view of an embodiment of the present invention, and FIG. 2 is a circuit diagram of an electronic circuit to which the present invention is applied. 1.2, 3, 4.5...gate electrode, 6...
...Power supply line, 7...Common potential line, 8,9...
...Input line, 10...Output line, 11...
... P-type semiconductor single crystal substrate, 12... Silicon dioxide/film, 13, 14, 15, 16° 17.18...
...N-type semiconductor layer %19...Silicon dioxide film, 20...Through hole, 21...
・Aluminum wiring sQt, Qi...Depression 7 type field effect transistor s Q a s Q 4
s Q s... 7 Hanosment type field effect transistor. half position

Claims (1)

[Claims] a first gate electrode having an annular closed structure, a first source (or drain) region provided outside the first gate electrode, and a first source (or drain) region provided inside the first gate electrode. a drain (or source) region of
a field effect transistor, a second gate electrode having an annular closed structure within the first drain region;
A second source (or drain) outside the gate electrode of
A second drain (
A second field effect transistor is provided having a ring gate electrode structure in the drain region of the nth (n is an integer of 2 or more) field effect transistor. 1. A semiconductor integrated circuit characterized in that a device structure including effect transistors is combined as a basic unit, and a source region of a first electrode effect transistor of each basic unit is shared.