JPS61154144A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS61154144A JPS61154144A JP27734584A JP27734584A JPS61154144A JP S61154144 A JPS61154144 A JP S61154144A JP 27734584 A JP27734584 A JP 27734584A JP 27734584 A JP27734584 A JP 27734584A JP S61154144 A JPS61154144 A JP S61154144A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- film
- oxide film
- silicon oxide
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔腫東上の利用分野〕
本発明は半導体装置及びその製造方法に関し、特に埋設
多結晶シリコン膜にて素子分離を行った半導体装置及び
その製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device in which elements are separated by a buried polycrystalline silicon film and a method for manufacturing the same.
従来、素子分離を多結晶シリコン膜にて形成する製造方
法としてはR,D、Rumg等がIEDM(Inter
nationaI Electron Devices
Meeting)82の237頁以呻に発表されて−
る方法が主としして用Vaられて−る。この製法の要点
は、シリコン基板上にシリコン酸化膜とシリコン窒化膜
の三重膜を形成し、この二m膜の上にシリコン溝形成の
マスク材としてCVD法によるシリコン酸化膜又ハレジ
スト編のパターンを形成し、前記マスク材を用−て二m
腰及びシリコン基板を食刻し構を形成し、久−で膜表面
にシリコン欧化膜を形成し、溝を多結晶シリコン膜によ
シ埋設し平担化し、その多結晶シリコン膜表面を酸化す
ると−う工程からなっている。Conventionally, R, D, Rumg, etc. have been used as manufacturing methods for forming element isolation using polycrystalline silicon films using IEDM (Inter
nationaI Electron Devices
Meeting) Published on page 237 of 82-
This method is mainly used. The key point of this manufacturing method is to form a triple film of silicon oxide film and silicon nitride film on a silicon substrate, and then apply a silicon oxide film or halide pattern by CVD method as a mask material for forming silicon grooves on this 2m film. 2 m using the mask material.
A structure is formed by etching the base and silicon substrate, a silicon oxide film is formed on the surface of the film, a trench is filled with a polycrystalline silicon film and the surface is flattened, and the surface of the polycrystalline silicon film is oxidized. - It consists of the following steps.
なお、第2図(a)〜(d)を用いて従来の埋設多結晶
7リコン編による素子分離構造並びにその製造方法を説
明する。第2図(1)は半導体基板11上にシリコン叡
化膜12.シリコン窒化膜13t−形成した後に、フォ
トレジストパターン14を形成し、フォトレジストパタ
ーン14tマスクトシて、シリコン窒化膜13.シリコ
ン欧化膜12およびシリコン基板11を順次食刻し、溝
15を形成したものである。次に第2図(b)に示すよ
うに、フォトレジストを除去し、溝表面に酸化してシリ
コン欧化膜を形成する。次に、第2図(C)に示すよう
に、害を多結晶シリコン膜17にて埋設し平担化する。A conventional element isolation structure based on buried polycrystalline 7-resonance knitting and its manufacturing method will be explained with reference to FIGS. 2(a) to 2(d). FIG. 2(1) shows a silicon oxide film 12 on a semiconductor substrate 11. After forming the silicon nitride film 13t, a photoresist pattern 14 is formed, and the photoresist pattern 14t is masked to form the silicon nitride film 13. A silicon oxide film 12 and a silicon substrate 11 are sequentially etched to form grooves 15. Next, as shown in FIG. 2(b), the photoresist is removed and the groove surface is oxidized to form a silicon oxide film. Next, as shown in FIG. 2(C), the substrate is buried with a polycrystalline silicon film 17 and planarized.
次に、第1図(d)に示すように、シリコン窒化膜13
をマスクとして多結晶ンリコン腰衣面II−選択故化し
てシリコン欧化膜18を形成する。Next, as shown in FIG. 1(d), the silicon nitride film 13
A polycrystalline silicon film 18 is formed by selectively degrading the polycrystalline silicon film 18 using the mask as a mask.
しかるときは埋設多結晶シリコン膜の全周が酸化膜で横
われ次素子分離領域が完成する。In this case, the entire circumference of the buried polycrystalline silicon film is covered with an oxide film to complete the next element isolation region.
上述した埋設多結晶シリコン膜による素子分離方法はシ
リコン簿表面を選択的に酸化する時に使用した激化マス
ク材のシリコン窒化膜を再びIIを埋設した多結晶シリ
コン膜の表面を選択的に欧化する時に使用して−る。そ
のために、これら2回の選択酸化によ多形成された酸化
膜のりなざ目は、選択酸化によるバーズヘッド(bir
d he@d)がつながった形とな9、他所よりも大輪
に欧化膜厚が薄−形となりて−る。この結果、この薄%
1−@化膜の領域を通して、絶縁分離用の多結晶シリコ
ン膜中に電荷の注入が起こり、分@*城下の基板表面に
反転層が形成され、絶縁特性が劣化すると−う欠点t″
Mして−る。In the device isolation method using the buried polycrystalline silicon film described above, the silicon nitride film used as an intensification mask material used when selectively oxidizing the silicon surface is again used to selectively oxidize the surface of the polycrystalline silicon film in which II is buried. I'm using it. For this reason, the oxide film seams formed by these two selective oxidations are removed from the bird's head (bir's head) formed by the selective oxidation.
It has a shape in which d he @ d) are connected9, and the European membrane thickness is thinner in the large ring than in other places. As a result, this thin%
1-Charges are injected into the polycrystalline silicon film for insulation isolation through the region of the dielectric film, and an inversion layer is formed on the surface of the substrate beneath the film, resulting in deterioration of the insulation properties.
I'm doing M.
この対策として溝を多結晶シリコン属にて埋設し、平担
化した後にフォトプロセスを設は選択酸化のマスク材で
あるシリコン窒化膜を部分的に除去した彼に旙出した基
板表面及び多結晶腰衣−を選択的に酸化する方法が提案
されてlzaるが、この方法を用−るとフォトプロセス
工程を余分に行う為に工程が長くなること、及びマスク
合わせマージンが必要とな)分離領域が広くなることお
よび部分的に除去した部分とバーズへ、ラドの211!
!所に弱い部分が形成され均一な酸化膜が形成されにく
V為とりう欠点がある。As a countermeasure, the grooves were filled with polycrystalline silicon, and after planarization, a photo process was performed to partially remove the silicon nitride film, which is a mask material for selective oxidation. A method of selectively oxidizing the waist coat has been proposed, but using this method requires an extra photo process step, making the process longer and requiring a margin for mask alignment. Rad's 211 to wider areas and partially removed parts and birds!
! This method has a serious drawback because weak parts are formed in certain places and it is difficult to form a uniform oxide film.
従って本発明は、上記欠点に対地してなされ九もので、
7オトプaセス工程を増やすことなく、問題となる酸化
膜の薄い領域を除き必要領域まで均一な酸化[を備えた
素子分IIk領域を有する半導体装置及び七のam方法
を提供することを目的とする。Therefore, the present invention has been made in view of the above-mentioned drawbacks.
It is an object of the present invention to provide a semiconductor device having an element IIk region and a method for providing a semiconductor device having an element IIk region, which is uniformly oxidized to necessary regions except for problematic thin oxide film regions without increasing the number of OTO processes. do.
本発明の第1の発明の半導体装rt専委遭7畜は、半導
体基板内に埋設された多結晶シリコン領域と、該多結晶
シリコン領域の全周囲を取囲んで形成されたシリコン廐
化編とを令し、半導体基板表面く形成された該シリコン
酸化膜部分は前記多結晶シリコン側壁のシリコン酸化膜
よシ外方向に一定距離だけ多結晶シリコン領域と相似的
に伸びた形を有することによル構成される。The first aspect of the present invention includes a polycrystalline silicon region buried in a semiconductor substrate, a silicon encapsulant formed around the entire periphery of the polycrystalline silicon region, and The silicon oxide film portion formed on the surface of the semiconductor substrate has a shape extending outward by a certain distance from the silicon oxide film on the polycrystalline silicon sidewall in a manner similar to the polycrystalline silicon region. is configured.
また、本発明の第2の発明の半導体装置の製造方法は、
シリコン半導体基板表面にシリコン酸化11!に、シリ
コン窒化膜、及びシリコン酸化膜の三重膜を形成する工
程と、該三N編上にフォトレジストパターンを形成する
工程と、該レジストをマスクとして前記三重膜を食刻し
除去した後再び前記7オトレジストマスクとして露出し
たシリコン基板表面を食刻し孔又は害を設ける工程と、
その後再びIii記レジストをマスクとして前記シリコ
ン欧化膜を食刻する工程と、前記孔又は溝の表面にシリ
コン欧化膜を形成する工程と、7リコン酸化膜をマスク
としてシリコン窒化膜を食刻する工程と、前記孔又は溝
を多結晶シリコンによシ埋設する工程と、残存シリコン
窒化膜をマスクとして基板表面及び多結晶シリコン表面
を酸化する工程とを含んで11成される◎
〔実施例〕
以下、本発明の実施例につめて、図面を参照して説明す
る。第1図(−〜(d)は本発明の一実施例を説明する
ために工1!順に示した断面図である。本発明の一実施
例は次の工程により製造することができる。Further, the method for manufacturing a semiconductor device according to the second invention of the present invention includes:
Silicon oxide 11 on the surface of a silicon semiconductor substrate! , a step of forming a triple film of a silicon nitride film and a silicon oxide film, a step of forming a photoresist pattern on the 3N layer, and a step of etching and removing the triple layer using the resist as a mask, and then repeating the steps again. etching the surface of the silicon substrate exposed as the photoresist mask to form holes or damage;
Thereafter, a step of etching the silicon oxide film again using the resist described in III as a mask, a step of forming a silicon oxide film on the surface of the hole or groove, and a step of etching the silicon nitride film using the 7-recon oxide film as a mask. ◎ [Example] Below Embodiments of the present invention will be described with reference to the drawings. FIGS. 1--(d) are cross-sectional views shown in order of step 1 to explain an embodiment of the present invention. An embodiment of the present invention can be manufactured by the following steps.
まず、第1図(a)は、シリコン半導体基板11上に熱
酸化にLプ約500人の膜厚の酸化膜12を形成し、仄
にシリコン窒化膜13をCVD@によプ約1100人の
膜厚で形成し、次−でその上KCVD法によプ約200
0人O膜厚のシリコン酸化膜20を形成した後、フォト
プロセス法によシレジストハターン14を形成し、この
レジストパターン14’fi−マスクとして順次シリコ
ン酸化膜20゜シリコン窒化膜13.シリコン酸化j[
12及びシリコン基板11tRIE法によシ食刻し、溝
15金約4μmo深さで形成したものを示してiる。First, as shown in FIG. 1(a), an oxide film 12 with a thickness of about 500 layers is formed on a silicon semiconductor substrate 11 by thermal oxidation, and a silicon nitride film 13 is formed by CVD@ with a thickness of about 1100 layers. The film is formed to a thickness of about 200 mm, and then coated by KCVD to a thickness of about 200 mm.
After forming a silicon oxide film 20 with a thickness of 0.00000, a resist pattern 14 is formed by a photo process method, and this resist pattern 14'fi--a silicon oxide film 20.degree. silicon nitride film 13. Silicon oxide [
12 and silicon substrate 11 are etched by the RIE method to form grooves 15 with a depth of approximately 4 μm.
次に、纂1図(b)に下すように、レジスト膜14tマ
スクとしてシリコン教化膜2(1食刻し、約α5μm
O41I&で側面エッチする。Next, as shown in Figure 1(b), a silicon oxide film 2 (one etched, approximately α5 μm thick) was used as a mask for the resist film 14t.
Etch the sides with O41I&.
次に%I!1図(C)に示すように、レジストを除去し
、シリコン窒化膜13をマスクとして溝表面を選択的に
改化し、シリコン鈑化膜16t−約α2μmの膜厚で形
成する。次−でシリコン酸化[16−。Next %I! As shown in FIG. 1C, the resist is removed and the groove surface is selectively modified using the silicon nitride film 13 as a mask, and a silicon plated film 16t is formed with a thickness of approximately α2 μm. Next - silicon oxidation [16-.
20f:マスクとしてシリコン窒化ml at一部分的
に食刻する。20f: Partially etching silicon nitride ml as a mask.
久に、帛1図(d)に示すように、溝15を多結晶シリ
コンWXKて埋設し、次いで平担化し、シリコン教化膜
20に除去した後、残存シリコン窒化膜13をマスクと
して、基板表面及び多結晶7リコン膜17表伽を寂化し
、シリコン酸化[18を約α6μm(D膜厚で形成する
。しかるとき薄い酸化膜対応領域19aは薄くならず多
結晶シリコン膜上の酸化膜とtlぼ同一厚さである。As shown in FIG. 1(d), the groove 15 is filled with polycrystalline silicon WXK, then planarized, and removed to form a silicon oxide film 20. Using the remaining silicon nitride film 13 as a mask, the substrate surface is Then, the surface of the polycrystalline silicon film 17 is made thinner, and silicon oxide [18] is formed with a thickness of approximately α6 μm (D film thickness. At this time, the thin oxide film corresponding region 19a does not become thinner and is separated from the oxide film on the polycrystalline silicon film. They are almost the same thickness.
以上によMil1図(d)の本発明の構造が得られる。As described above, the structure of the present invention shown in Mil1 diagram (d) is obtained.
以上詳細に説明したように、本発明は従来O選択酸化用
のマスク材である7リコン窒化−上K。As described in detail above, the present invention is directed to a mask material for conventional O selective oxidation.
新たにシリコン絨化瞑層を形成し、このシリコン峡化属
、7リコン窒化膜及びシリコン基板を同一レジストによ
り食刻し、シリコン窒化膜パターンを形成した後、前記
シリコン酸化膜tI11面エツチングし、そのシリ;ン
を化膜パターンと相似で小Iなる味化膜パターンを形成
することにある。これによシ形成した窒化膜パターン及
び酸化膜パターンをそれぞれ溝表面の選択酸化時のマス
クパターン及び多結晶シリコン膜表面の選択酸化時のマ
スクパターンとして使用する。この結果従来法における
多結晶7リコン膜上の酸化膜の薄−領域を無くすことが
可能となり、その結果絶縁特性の改善された素子分離領
域をもつ半導体装置が得られるO
〔発明の効果〕
以上説明し九とお)、本発明によれば、フォトプロセス
法機を増やすことなく、問題となる多結晶シリコン領域
上の酸化膜に薄i領域を発生させることなく必要な領域
まで均一な厚−酸化膜全偏見た素子分離領域を有し、従
りて杷に特性の改善された半導体鉄重が得られる。After forming a new silicon oxide layer and etching the silicon nitride layer, silicon nitride film and silicon substrate using the same resist to form a silicon nitride film pattern, etching the silicon oxide film tI11 surface, The silicon is similar to the silicone film pattern to form a silicone film pattern. The nitride film pattern and oxide film pattern thus formed are used as a mask pattern for selective oxidation of the groove surface and a mask pattern for selective oxidation of the polycrystalline silicon film surface, respectively. As a result, it is possible to eliminate the thin region of the oxide film on the polycrystalline silicon film in the conventional method, and as a result, a semiconductor device having an element isolation region with improved insulation properties can be obtained. According to the present invention, it is possible to achieve uniform thickness oxidation in the necessary area without increasing the number of photoprocessing methods and without creating a thin i-region in the oxide film on the polycrystalline silicon area, which is a problem. It has a device isolation region throughout the film, and therefore a semiconductor iron layer with improved characteristics can be obtained.
第1図(1)〜(d)は本発明の一実施例を説明するた
めに工程類に示した断面図、第2図(1)〜(d)は従
来の埋設多結晶シリコン膜による素子分離領域を有する
半導体装置及びその製造方法を説明するために工程臘に
示した断面図である。
11・・・・・・シリコン半導体基板、12.16,1
8゜20・・・・・・シリコン酸化膜、13・・・・・
・シリコン窒化膜、14・・・・・・フォトレジスト、
15・・・・・・シリコン簿、17・・・・・・多結晶
シリコン膜、19・・・・・・薄−酸化膜領域、19a
・・−・・・薄Vh鍍化膜対応領域。
葛 l 図
賂 2凶Figures 1 (1) to (d) are cross-sectional views showing steps to explain one embodiment of the present invention, and Figures 2 (1) to (d) are elements using conventional buried polycrystalline silicon films. FIG. 2 is a cross-sectional view showing a process step for explaining a semiconductor device having an isolation region and a method for manufacturing the same. 11...Silicon semiconductor substrate, 12.16,1
8゜20...Silicon oxide film, 13...
・Silicon nitride film, 14...photoresist,
15... Silicon book, 17... Polycrystalline silicon film, 19... Thin oxide film region, 19a
...--A region compatible with thin Vh plating film. Kudzu l Charitable bribe 2 evil
Claims (2)
、該多結晶シリコン領域の全周囲を取囲んで形成された
シリコン酸化膜とを有し、半導体基板表面に形成された
該シリコン酸化膜部分は前記多結晶シリコン側壁のシリ
コン酸化膜より外方向に一定距離だけ多結晶シリコン領
域と相似的に伸びた形を有していることを特徴とする半
導体装置。(1) It has a polycrystalline silicon region buried in a semiconductor substrate and a silicon oxide film formed to surround the entire periphery of the polycrystalline silicon region, and the silicon oxide film is formed on the surface of the semiconductor substrate. A semiconductor device characterized in that the portion has a shape extending outward from the silicon oxide film of the polycrystalline silicon sidewall by a certain distance in a similar manner to the polycrystalline silicon region.
コン窒化膜、及びシリコン酸化膜の三重膜を形成する工
程と、該三重膜上にフォトレジストパターンを形成する
工程と、該レジストをマスクとして前記三重膜を食刻し
除去した後再び前記フォトレジストをマスクとして露出
したシリコン基板表面を食刻し孔又は溝を設ける工程と
、その後再び前記レジストをマスクとして前記シリコン
酸化膜を食刻する工程と、前記孔又は溝の表面にシリコ
ン酸化膜を形成する工程と、シリコン酸化膜をマスクと
してシリコン窒化膜を食刻する工程と、前記孔又は溝を
多結晶シリコンにより埋設する工程と、残存シリコン窒
化膜をマスクとして基板表面及び多結晶シリコン表面を
酸化する工程とを含むことを特徴とする半導体装置の製
造方法。(2) A step of forming a triple film of a silicon oxide film, a silicon nitride film, and a silicon oxide film on the surface of a silicon semiconductor substrate, a step of forming a photoresist pattern on the triple film, and a step of forming a photoresist pattern using the resist as a mask. After etching and removing the film, etching the exposed silicon substrate surface again using the photoresist as a mask to provide a hole or groove; and then etching the silicon oxide film again using the resist as a mask; forming a silicon oxide film on the surface of the hole or groove; etching the silicon nitride film using the silicon oxide film as a mask; burying the hole or groove with polycrystalline silicon; and remaining silicon nitride film. oxidizing a substrate surface and a polycrystalline silicon surface using as a mask.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27734584A JPS61154144A (en) | 1984-12-27 | 1984-12-27 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27734584A JPS61154144A (en) | 1984-12-27 | 1984-12-27 | Semiconductor device and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61154144A true JPS61154144A (en) | 1986-07-12 |
Family
ID=17582228
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP27734584A Pending JPS61154144A (en) | 1984-12-27 | 1984-12-27 | Semiconductor device and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61154144A (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4980311A (en) * | 1987-05-05 | 1990-12-25 | Seiko Epson Corporation | Method of fabricating a semiconductor device |
US4994406A (en) * | 1989-11-03 | 1991-02-19 | Motorola Inc. | Method of fabricating semiconductor devices having deep and shallow isolation structures |
US5236861A (en) * | 1991-08-16 | 1993-08-17 | Sony Corporation | Manufacturing method of metal-insulator-semiconductor device using trench isolation technique |
US5254491A (en) * | 1991-09-23 | 1993-10-19 | Motorola, Inc. | Method of making a semiconductor device having improved frequency response |
US5436190A (en) * | 1994-11-23 | 1995-07-25 | United Microelectronics Corporation | Method for fabricating semiconductor device isolation using double oxide spacers |
US5578518A (en) * | 1993-12-20 | 1996-11-26 | Kabushiki Kaisha Toshiba | Method of manufacturing a trench isolation having round corners |
US5877065A (en) * | 1991-11-15 | 1999-03-02 | Analog Devices Incorporated | Process for fabricating insulation-filled deep trenches in semiconductor substrates |
EP0996149A1 (en) * | 1998-10-23 | 2000-04-26 | STMicroelectronics S.r.l. | Manufacturing method for an oxide layer having high thickness |
-
1984
- 1984-12-27 JP JP27734584A patent/JPS61154144A/en active Pending
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4980311A (en) * | 1987-05-05 | 1990-12-25 | Seiko Epson Corporation | Method of fabricating a semiconductor device |
US4994406A (en) * | 1989-11-03 | 1991-02-19 | Motorola Inc. | Method of fabricating semiconductor devices having deep and shallow isolation structures |
US5236861A (en) * | 1991-08-16 | 1993-08-17 | Sony Corporation | Manufacturing method of metal-insulator-semiconductor device using trench isolation technique |
US5254491A (en) * | 1991-09-23 | 1993-10-19 | Motorola, Inc. | Method of making a semiconductor device having improved frequency response |
US5877065A (en) * | 1991-11-15 | 1999-03-02 | Analog Devices Incorporated | Process for fabricating insulation-filled deep trenches in semiconductor substrates |
US5578518A (en) * | 1993-12-20 | 1996-11-26 | Kabushiki Kaisha Toshiba | Method of manufacturing a trench isolation having round corners |
US5436190A (en) * | 1994-11-23 | 1995-07-25 | United Microelectronics Corporation | Method for fabricating semiconductor device isolation using double oxide spacers |
EP0996149A1 (en) * | 1998-10-23 | 2000-04-26 | STMicroelectronics S.r.l. | Manufacturing method for an oxide layer having high thickness |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5047117A (en) | Method of forming a narrow self-aligned, annular opening in a masking layer | |
US5470782A (en) | Method for manufacturing an integrated circuit arrangement | |
JPS61154144A (en) | Semiconductor device and manufacture thereof | |
JPH1145874A (en) | Manufacture of semiconductor device | |
JPS61214446A (en) | Manufacture of semiconductor device | |
JPS6242382B2 (en) | ||
JPH0396249A (en) | Manufacture of semiconductor device | |
JPH05267448A (en) | Method of isolating element of semiconductor device | |
JP2748465B2 (en) | Method for manufacturing semiconductor device | |
JPS61119056A (en) | Manufacture of semiconductor device | |
KR100265177B1 (en) | Semiconductor element isolation method | |
JPH01235245A (en) | Semiconductor device | |
JPH05206263A (en) | Manufacture of semiconductor device | |
US5971768A (en) | Methods of fabricating integrated circuit trench isolation regions | |
JPH0613459A (en) | Element isolating method and semiconductor device | |
JPH065742B2 (en) | Method for manufacturing semiconductor device | |
JPS6148935A (en) | Manufacture of semiconductor device | |
JPS61287233A (en) | Manufacture of semiconductor device | |
JPS61290737A (en) | Manufacture of semiconductor device | |
JPS6398131A (en) | Manufacture of semiconductor device | |
JPH06283597A (en) | Manufacture of semiconductor device | |
JPS61159749A (en) | Manufacture of semiconductor integrated circuit device | |
JPS61196549A (en) | Manufacture of semiconductor integrated circuit device | |
JPS63307756A (en) | Manufacture of semiconductor device | |
JPS6265437A (en) | Manufacture of semiconductor device |