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JPS61196549A - Manufacture of semiconductor integrated circuit device - Google Patents

Manufacture of semiconductor integrated circuit device

Info

Publication number
JPS61196549A
JPS61196549A JP3529085A JP3529085A JPS61196549A JP S61196549 A JPS61196549 A JP S61196549A JP 3529085 A JP3529085 A JP 3529085A JP 3529085 A JP3529085 A JP 3529085A JP S61196549 A JPS61196549 A JP S61196549A
Authority
JP
Japan
Prior art keywords
oxide film
film
nitride film
nitride
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3529085A
Other languages
Japanese (ja)
Other versions
JPH0715937B2 (en
Inventor
Kenichi Suzuki
研一 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP60035290A priority Critical patent/JPH0715937B2/en
Publication of JPS61196549A publication Critical patent/JPS61196549A/en
Publication of JPH0715937B2 publication Critical patent/JPH0715937B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To enable a nitride film to work as an etching mask for a oxide film and to enable to obtain a flat surface for a semiconductor integrated circuit by a method wherein the nitride film is formed on the isolated oxide film alone on the periphery of the element region even after the isolating process ends. CONSTITUTION:A first pad oxide film 22 and a first nitride film 23 are selectively provided on the surface of a silicon substrate 21. An etching is performed on a part of the silicon substrate 21, which is exposing within the part of an opening part 24, and a groove 25 is formed. A second pad oxide film 26 is formed on the inner wall of the groove 25, and a second nitride film 27 and a third oxide film 28 are coated on the whole surface thereof. Parts of the oxide film 28 and the nitride film 27, which are located right under the opening part 24, are selectively removed. An isolated oxide film 31 is formed in the groove part. A part of the nitride film 23 and a part of the rest part of the nitride film 27 are selectively removed and the nitride films 23 and 27 are left on parts only of the isolated oxide film 31, which are located on the peripheral part of the element region. After the oxide film 27 is removed, an oxide film 32 is formed and a resist pattern 34 is formed. An edge 35 is formed in such a way as to locate on the region of the nitride film 27. An etching is performed on the oxide film 32, the element region 36 is made to expose and a diffusion layer 37 is formed.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は半導体集積回路装置の製造方法に関し、特に
素子分離技術に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and particularly to element isolation technology.

(従来の技術) 半導体集積回路装置の集積度は増加の一途をたどり、次
世代の高密度集積回路装置の開発には、素子の微細化と
共に、従来広く用いられてきた選択酸化分離法(LOG
O3)に代わる新たな素子分離となる。そのため、これ
までにも数多くの新分離技術の提案がなされている(例
えば、後藤他I EDM82−58.玉置他I EDM
82−62.竹本他I EDM83−51)。
(Prior art) The degree of integration of semiconductor integrated circuit devices continues to increase, and in the development of next-generation high-density integrated circuit devices, along with miniaturization of elements, the selective oxidation isolation method (LOG), which has been widely used in the past, is required.
This is a new element isolation that replaces O3). Therefore, many new separation technologies have been proposed so far (for example, Goto et al. I EDM82-58; Tamaki et al. I EDM
82-62. Takemoto et al. I EDM83-51).

プロセスも比較的簡単で、従来のLOCO3法との互換
性も良い有力な手段のひとつとして、改良型選択酸化分
離法を挙げることができる(特願昭58−76200)
The improved selective oxidation separation method can be cited as one of the powerful methods that has a relatively simple process and good compatibility with the conventional LOCO3 method (Japanese Patent Application No. 76,200/1982).
.

第2図(A)〜(E)は、特願昭58−76200に開
示された改良型選択酸化分離法の製造工程を説明するた
めの断面図である。以下に示す図では、分離酸化膜形成
に関する部分だけを図示し、拡散層などは省略している
FIGS. 2A to 2E are cross-sectional views for explaining the manufacturing process of the improved selective oxidation separation method disclosed in Japanese Patent Application No. 58-76200. In the figures shown below, only the portion related to the formation of the isolation oxide film is shown, and the diffusion layer and the like are omitted.

まず、第2図(A)のように、シリコン基体1の素子形
成領域の表面に、通常のLOCO3法と同様に、薄いパ
ッド酸化膜(シリコン酸化膜)2と窒化膜(シリコン窒
化膜)3を選択的に設ける。
First, as shown in FIG. 2(A), a thin pad oxide film (silicon oxide film) 2 and a nitride film (silicon nitride film) 3 are coated on the surface of the element formation region of the silicon substrate 1, as in the normal LOCO3 method. be provided selectively.

次いで、第2図(B)のように、酸化による体積の増大
を補償するために上記2層膜3,2をマスクとしてシリ
コン基体1をエツチングし、予定する分離酸化膜のV2
程度の深さの溝4を形成する。
Next, as shown in FIG. 2(B), the silicon substrate 1 is etched using the two-layer films 3, 2 as a mask to compensate for the increase in volume due to oxidation, and the V2 of the planned isolation oxide film is etched.
A groove 4 of a certain depth is formed.

通常のLOCO3法では、この状態で選択酸化を行なう
が、すると、パッド酸化膜2に沿って素子領域表面にく
さび状に酸化が進行し、いわゆるバーズビークが形成さ
れて分離領域幅が拡がり、また素子領域周囲の分離酸化
膜の盛り上り、即ちバーズヘッドが生じて平坦性が損な
われる。
In the normal LOCO3 method, selective oxidation is performed in this state, but then the oxidation progresses in a wedge shape on the surface of the element region along the pad oxide film 2, forming a so-called bird's beak, expanding the width of the isolation region, and increasing the width of the isolation region. A bulge of the isolation oxide film around the region, that is, a bird's head occurs, and the flatness is impaired.

そのため、特願昭58−76200による改良型選択酸
化分離法では、第2図(C)のように、溝4内壁に第2
のパッド酸化膜5を形成し、さらに全面に第2の窒化膜
6を被着する。次に、反応性イオンエッチ(RIE)を
用いて、第1および第2の窒化I#、3.6よりなるア
ンダーカット状の「ひさし」7をマスクとして、第2図
(D)に示すように、溝4の底面の第2の窒化膜6を選
択的に除去する。
Therefore, in the improved selective oxidation separation method disclosed in Japanese Patent Application No. 58-76200, a second layer is formed on the inner wall of the trench 4, as shown in FIG.
A pad oxide film 5 is formed, and a second nitride film 6 is further deposited on the entire surface. Next, using reactive ion etching (RIE), using the undercut-shaped "eaves" 7 made of the first and second nitride I#, 3.6 as a mask, as shown in FIG. 2(D), Next, the second nitride film 6 on the bottom of the trench 4 is selectively removed.

その後、選択酸化を行なうと、バーズビークは、第2の
パッド酸化膜5に沿って溝4側壁に形成されるので、第
2図(E)のような厚い分離酸化膜8による分離構造が
得られる。
After that, when selective oxidation is performed, a bird's beak is formed on the side wall of the trench 4 along the second pad oxide film 5, so that an isolation structure with a thick isolation oxide film 8 as shown in FIG. 2(E) is obtained. .

第2のパッド酸化膜5に沿って伸びろ溝側壁のバーズビ
ーク形成部9は、第2のパッド酸化膜厚。
The bird's beak forming portion 9 on the side wall of the groove extending along the second pad oxide film 5 has the thickness of the second pad oxide film.

第2の窒化膜厚1選択酸化源度などに依存し、したがっ
て処理条件が適切であれば、バーズビークは、素子領域
終端部10で停止し、素子領域内部には侵入しない。
It depends on the second nitride film thickness 1 selective oxidation source degree, etc. Therefore, if the processing conditions are appropriate, the bird's beak stops at the end portion 10 of the device region and does not invade inside the device region.

以上のように、改良型選択酸化分離法l法では、分離工
程終了時点でバーズビーク、バーズヘッドの無い平坦性
の良い表面を得ることができる。
As described above, in the improved selective oxidation separation method I, a surface with good flatness free of bird's beaks and bird's heads can be obtained at the end of the separation process.

一方、従来のLOCO3法の利点として、素子形成工程
において、分離酸化膜を利用した自己整合プロセスが採
用可能である点を挙げることができる。
On the other hand, an advantage of the conventional LOCO3 method is that a self-alignment process using an isolation oxide film can be adopted in the element formation process.

第3図(A)〜(D)に、LOGO8構造における自己
整合プロセスの断面説明図を示す。第3図(A)は、L
OGOSプロセスによる分離工程を終了した時点の断面
図である。通常LOCO5法では、バーズビーク11が
素子領域内に侵入し、さらに、バーズヘッド12が形成
されている。
FIGS. 3A to 3D show cross-sectional explanatory views of the self-alignment process in the LOGO8 structure. Figure 3 (A) is L
FIG. 3 is a cross-sectional view at the time when the separation process by the OGOS process is completed. In the normal LOCO5 method, the bird's beak 11 invades the element region, and the bird's head 12 is further formed.

分離工程終了後、第3図(B)に示すように、形成し、
さらに拡散層を形成すべき素子領域上に開口部14を持
つレジストパターン15を形成する。この時11.レジ
ストパターン15は、素子領域上のみならず、分離酸化
膜上のバーズヘッド12をも包含する広い開口部14を
有するものである。
After the separation process is completed, as shown in FIG. 3(B),
Furthermore, a resist pattern 15 having an opening 14 is formed on the element region where a diffusion layer is to be formed. At this time 11. The resist pattern 15 has a wide opening 14 that covers not only the element region but also the bird's head 12 on the isolation oxide film.

続いて、第3図(C)に示すように、レジストパターン
15をマスクとして酸化膜13のエツチングを行ない、
拡散層を形成すべき素子領域16を露出させる。その後
、レジストパターン15を除去し、素子領域16に拡散
層を形成する。この素子領域上の酸化・エツチング・拡
散工程を必要回数くり返すことにより、第3図(D)に
示す最終分離構造を有する素子が形成されてゆく。
Subsequently, as shown in FIG. 3(C), the oxide film 13 is etched using the resist pattern 15 as a mask.
The element region 16 where the diffusion layer is to be formed is exposed. Thereafter, the resist pattern 15 is removed and a diffusion layer is formed in the element region 16. By repeating the oxidation, etching, and diffusion steps on the device region as many times as necessary, a device having the final isolation structure shown in FIG. 3(D) is formed.

第3図に示した自己整合プロセスの利点は、レジストパ
ターン15を形成する際、正確な位置合わせが必要なく
、確実に所望の素子領域16に開口部を形成できる点で
ある。すなわち、自己整合的に拡散層を形成することが
でき、素子の縮小化にも有利である。さらに、LOGO
8工程で形成さグ工程で小型化、縮小されろ点も好都合
である。
The advantage of the self-alignment process shown in FIG. 3 is that accurate alignment is not required when forming the resist pattern 15, and openings can be reliably formed in desired device regions 16. That is, the diffusion layer can be formed in a self-aligned manner, which is advantageous for downsizing the device. Furthermore, LOGO
It is also advantageous that it can be formed in 8 steps and can be downsized and reduced in size in the 8-step process.

これらの利点は、一般に、酸化膜分離法の利点として指
摘されているものである。
These advantages are generally pointed out as advantages of the oxide film separation method.

ところで、改良型選択酸化分離法に、この自己整合プロ
セスを適用した場合の断面図を第4図(A)〜(D)に
示す。第4図(A)は、改良型選択酸化分離法により分
離工程を終了した時点の断面図であり、素子領域上への
バーズビークの侵入もなく、またバーズヘッドも形成さ
れていない。
Incidentally, cross-sectional views when this self-aligned process is applied to the improved selective oxidation separation method are shown in FIGS. 4(A) to 4(D). FIG. 4(A) is a cross-sectional view at the time when the separation process is completed by the improved selective oxidation separation method, and there is no bird's beak invading the element region, and no bird's head is formed.

分離工程終了後、第4図(B)に示すように、素子領域
上に拡散マスクとなるべき酸化膜13を形成し、さらに
、拡散層を形成すべき素子領域上に開口部14を持つレ
ジストパターン15を形成する。続いて、第4図(C)
に示すように、レジストパターン15をマスクとしてI
n化ff113のエツチングを行ない、拡散層を形成す
べき素子領域16を露出させる。
After the separation step, as shown in FIG. 4(B), an oxide film 13 to serve as a diffusion mask is formed on the element region, and a resist film 13 having an opening 14 is formed over the element region where a diffusion layer is to be formed. A pattern 15 is formed. Next, Figure 4 (C)
As shown in FIG.
The n-oxide FF 113 is etched to expose the element region 16 where a diffusion layer is to be formed.

(発明が解決しようとする問題点) この時、改良型選択酸化分離法で形成された分離酸化膜
には、バーズヘッドが形成されていないため、自己整合
プロセスによる分離酸化膜のエツチングにより、素子領
域周囲の分離酸化膜に深い窪み17が形成されてしまう
。さらに、深い窪みにより素子領域の肩部18が露出す
るため、第4図(D)に示すように、拡散層形成の際、
分離酸化膜側壁に沿って深い拡散層19が形成され易く
なり、接合の逆方向耐圧劣化などが起り、特性上も好ま
しくない。
(Problem to be Solved by the Invention) At this time, since no bird's head is formed in the isolation oxide film formed by the improved selective oxidation separation method, the device is etched by etching the isolation oxide film by the self-alignment process. A deep recess 17 is formed in the isolation oxide film around the region. Furthermore, since the shoulder portion 18 of the element region is exposed due to the deep depression, as shown in FIG. 4(D), when forming the diffusion layer,
A deep diffusion layer 19 is likely to be formed along the sidewall of the isolation oxide film, causing deterioration of the reverse breakdown voltage of the junction, which is also unfavorable in terms of characteristics.

すなわち、改良型選択酸化分離法では、従来の自己整合
プロセスを適用しようとすると、平坦性が損なわれるば
かりでなく、拡散層の形成にも悪影響を及ぼし、素子特
性の変動や不良を誘起する原因となる欠点を有していた
In other words, when using the improved selective oxidation separation method, applying the conventional self-alignment process not only impairs flatness but also adversely affects the formation of the diffusion layer, causing variations in device characteristics and defects. It had the following drawbacks.

(1!IJ題点を解決するための手楡)この発明は上記
問題点を解決するため、改良型選択酸化分離法において
、分離工程終了後も、素子領域周囲の分離酸化膜上に限
り(換言すれば、分離酸化膜の周辺部上にのみ)窒化膜
が形成されているようにする。
(1! Techniques for solving the IJ problem) In order to solve the above problems, the present invention uses an improved selective oxidation isolation method that allows only the ( In other words, the nitride film is formed only on the periphery of the isolation oxide film.

(作 用) このようにすると、後の自己整合プロセスにおいて、前
記窒化膜が酸化膜のエツチングマスクとして働く。
(Function) In this way, the nitride film acts as an etching mask for the oxide film in the later self-alignment process.

(実施例) 以下この発明の実施例を図面を参照して説明する。第1
図(A)〜(1)は、この発明の一実施例を示す工程断
面図である。
(Example) Examples of the present invention will be described below with reference to the drawings. 1st
Figures (A) to (1) are process cross-sectional views showing one embodiment of the present invention.

まず、第1図(A)のように、従来方法と同様に、シリ
コン基体21の素子形成領域の表面に、第1のパッド酸
化膜22と第1の窒化膜23の2層よりなる酸化防止膜
を選択的に設ける。換言すれば、シリコン基体21上に
第1のパッド酸化膜22と第1の窒化膜23を順次形成
した後、これらの膜23.22に、分離酸化膜形成領域
上において開口部24を形成する。ここで、第1のパッ
ド酸化膜22および第1の窒化膜23の膜厚は一例とし
て各々500人、2000人とする。
First, as in the conventional method, as shown in FIG. The membrane is selectively provided. In other words, after the first pad oxide film 22 and the first nitride film 23 are sequentially formed on the silicon substrate 21, the openings 24 are formed in these films 23.22 over the isolation oxide film formation region. . Here, the thicknesses of the first pad oxide film 22 and the first nitride film 23 are assumed to be 500 and 2000, respectively, as an example.

次に、第1図(B)に示すように、酸化による体積の増
大を補償するために、上記2層膜23゜基体21をエツ
チングし、例えば7000人程度0深さの溝25を形成
する。この時、第1の窒化膜23および第1のパッド酸
化膜22の下にアンダーカットが生じ、溝25は、開口
部24より大きい溝となる。なお、このアンダーカット
により露出した第1のパッド酸化膜22は次に除去する
が、そのまま残してもよい。
Next, as shown in FIG. 1(B), in order to compensate for the increase in volume due to oxidation, the two-layer film 23° substrate 21 is etched to form a groove 25 with a zero depth of about 7,000, for example. . At this time, an undercut occurs under the first nitride film 23 and the first pad oxide film 22, and the groove 25 becomes a groove larger than the opening 24. Note that the first pad oxide film 22 exposed by this undercut will be removed next, but may be left as is.

続いて、第1図(C)に示すように、溝25の内壁に熱
酸化により第2のパッド酸化膜26を500〜1500
人厚程度形成し、さらに全面に第2の窒化膜27および
第3の酸化膜28をCVD法により各々500〜100
0人厚、500〜2000人厚程度、順次被着する。
Subsequently, as shown in FIG. 1C, a second pad oxide film 26 is formed on the inner wall of the groove 25 to a thickness of 500 to 1500 mm by thermal oxidation.
A second nitride film 27 and a third oxide film 28 are formed on the entire surface with a film thickness of about 500 to 100% by CVD.
0 thickness, 500 to 2000 thicknesses, and are deposited one after another.

次に、第1rIl(D)に示すように、反応性イオンエ
ッチ(RIE)を用いて、開口部24直下の第3の酸化
膜28および第2の窒化膜27を選択的に除去する。
Next, as shown in 1rIl(D), the third oxide film 28 and the second nitride film 27 directly under the opening 24 are selectively removed using reactive ion etching (RIE).

その後、第2のパッド酸化膜26に沿って形成される側
壁のバーズビーク29の伸びが素子領域ib!tM起 
禽Rり  n  −n  #k  +L  −a−x 
  し エ  fp  At  //ド 鴫    峻
 1  ↓暢  L 瞥−第2の窒化膜23.27をマ
スクとしてシリコン基体21を約1.6−選択酸化する
ことにより、第1図(E)に示すように溝部に分離酸化
膜31を形成する。この時、第2の窒化膜27.第3の
酸化膜28および第1の窒化膜23の一部は、分離酸化
膜31上に押し上げられた状態となる。
Thereafter, the extension of the bird's beak 29 on the sidewall formed along the second pad oxide film 26 extends to the device region ib! tM start
BirdRri n -n #k +L -a-x
By selectively oxidizing the silicon substrate 21 by approximately 1.6 mm using the second nitride film 23 and 27 as a mask, as shown in FIG. 1(E), An isolation oxide film 31 is then formed in the trench. At this time, the second nitride film 27. Parts of the third oxide film 28 and the first nitride film 23 are pushed up onto the isolation oxide film 31.

続いて、第1図(F)に示すように、第3の酸化膜28
をマスクとして第1の窒化膜23および第2の窒化膜2
7の一部を選択的に除去し、素子領域周辺部の分離酸化
膜31上にのみ、換言すれば分離酸化膜31の周辺部上
のみに第2の窒化膜27を残す。
Subsequently, as shown in FIG. 1(F), a third oxide film 28 is formed.
The first nitride film 23 and the second nitride film 2 are
7 is selectively removed, and the second nitride film 27 is left only on the isolation oxide film 31 at the periphery of the element region, in other words, only on the periphery of the isolation oxide film 31.

次に、第3の酸化膜28を除去した後、自己整合プロセ
スを行なうために、第1図(G)に示すように、素子領
域上に拡散マスクとなるべき酸化膜32を2000〜4
000人厚程度形成し、さらに拡散層を形成すべき素子
領域上に開口部33を持つレジストパターン34を形成
する。ここで、レジストパターン34の縁35は、第2
の窒化膜27の領域上になるように形成する。すなわち
、レジストパターン34の形成時、第2の窒化膜27の
領域が自己整合プロセスのマスク合わせ余裕として与え
られることになる。
Next, after removing the third oxide film 28, in order to perform a self-alignment process, as shown in FIG.
A resist pattern 34 having an opening 33 is formed on the element region where the diffusion layer is to be formed. Here, the edge 35 of the resist pattern 34 is
The nitride film 27 is formed over the region of the nitride film 27. That is, when forming the resist pattern 34, the region of the second nitride film 27 is provided as a mask alignment margin for the self-alignment process.

続いて、第1図()T)に示すように、レジストパター
ン34および第2の窒化膜27をマスクとして酸化膜3
2のエツチングを行ない、拡散層を形成すべき素子領域
36を露出させる。その後、レジストパターン34を除
去し、素子領域36に拡散層37を形成する。
Subsequently, as shown in FIG. 1()T), the oxide film 3 is formed using the resist pattern 34 and the second nitride film 27 as a mask.
Etching step 2 is performed to expose the element region 36 where the diffusion layer is to be formed. Thereafter, the resist pattern 34 is removed and a diffusion layer 37 is formed in the element region 36.

そして、この素子領域上の酸化・エツチング・拡散工程
、すなわち自己整合プロセスを必要回数くり返し、さら
に、第1図(I)に示すように素子領域上に酸化膜38
が形成されている段階で、必要に応じて第2の窒化膜2
7を除去すれば、素子形成後の最終分離形状においても
平坦性の良い表面を得ることができる。
Then, the oxidation/etching/diffusion process on the element region, that is, the self-alignment process, is repeated as many times as necessary, and then an oxide film 38 is formed on the element region as shown in FIG. 1(I).
is formed, the second nitride film 2 is formed as necessary.
By removing 7, a surface with good flatness can be obtained even in the final separated shape after element formation.

なお、以上の一実施例において、第1図(C)の第3の
酸化膜28は多結晶シリコン膜で代用することもできる
。すなわち、多結゛晶シリコンは分離酸化膜形成工程で
酸化され、酸化膜に変換されろため、一実施例で示した
第3の酸化膜28と同等の効果を持つことになる。
In the above embodiment, the third oxide film 28 in FIG. 1(C) may be replaced with a polycrystalline silicon film. That is, since polycrystalline silicon is oxidized and converted into an oxide film in the isolation oxide film forming process, it has the same effect as the third oxide film 28 shown in one embodiment.

(発明の効果) 以上、詳細に説明したように、この発明によれば、改良
型選択酸化分離法において、分離工程終了後も素子領域
周囲の分離酸化膜上に限り、換言すれば分離酸化膜の周
辺部上にのみ窒化膜が形成されているため、後の自己整
合プロセスにおいてこの窒化膜が酸化膜のエツチングマ
スクとして働き、素子領域周囲の分離酸化膜に深い窪み
が発生するのを防止し、平坦な表面が得られるようにな
る。したがって、拡散層においても平坦な接合面が得ら
れ、安定した素子特性が得られるようになる。
(Effects of the Invention) As described in detail above, according to the present invention, in the improved selective oxidation separation method, even after the separation process is completed, the isolation oxide film remains only on the isolation oxide film around the element region. Since the nitride film is formed only on the periphery of the device, this nitride film acts as an etching mask for the oxide film in the later self-alignment process, preventing deep depressions from forming in the isolation oxide film around the device area. , a flat surface is obtained. Therefore, a flat bonding surface can be obtained also in the diffusion layer, and stable device characteristics can be obtained.

さらに、この発明によれば、溝側壁の第2の窒化膜上に
第3の膜が形成されることになるので、選択酸化工程で
の第2の窒化膜の酸化速度が低下し、耐酸化マスクとし
て必要な窒化膜厚を薄くできる。窒化膜厚を薄くするこ
とは、選択酸化工程上大きな効果が期待できる。
Furthermore, according to the present invention, since the third film is formed on the second nitride film on the trench sidewall, the oxidation rate of the second nitride film in the selective oxidation step is reduced, and the oxidation resistance is reduced. The thickness of the nitride film required as a mask can be reduced. Reducing the thickness of the nitride film can be expected to have a great effect on the selective oxidation process.

以上のように、この発明は、微細化・平坦化に優れた改
良型選択酸化分離法と、酸化膜分離法の利点である自己
整合技術とを、両者の長所を失うことなく結合させる技
術であり、従来の欠点であった窪みや欠陥の発生も防止
され、微細でかつ平坦な表面を持つ素子分離領域と素子
領域を同時に形成することが可能となる。
As described above, this invention is a technology that combines the improved selective oxidation separation method, which is excellent in miniaturization and planarization, and the self-alignment technology, which is an advantage of the oxide film separation method, without losing the advantages of both. This prevents the occurrence of depressions and defects, which are drawbacks of the conventional method, and makes it possible to simultaneously form an element isolation region and an element region having fine and flat surfaces.

したがって、バイポーラ型、MOS型を問わず、高集積
かつ高性能な半導体集積回路装置の製造に広く供するこ
とができる。
Therefore, the present invention can be widely used in manufacturing highly integrated and high-performance semiconductor integrated circuit devices, regardless of bipolar type or MOS type.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の半導体集積回路装置の製造方法の一
実施例を示す工程断面図、第2図は従来の改良型選択酸
化分離法による分離酸化膜領域の形成方法を工程順に示
す断面図、第3図は従来のLOCO5法により形成され
た分離酸化膜領域に自己整合技術を適用した場合の工程
断面図、第4図は従来の改良型選択酸化分離法により形
成された工程断面図であろ− 2】・−シリコン基体、22・・第1のパッド酸化膜、
23 ・第1の窒化膜、24・・開口部、25・・・溝
、26・・・第2のパッド酸化膜、27・・第2の窒化
膜、28・・・第3の酸化膜、31・・分離酸化膜。 第1図 第3図 第4図
FIG. 1 is a process cross-sectional view showing an embodiment of the method for manufacturing a semiconductor integrated circuit device of the present invention, and FIG. 2 is a cross-sectional view showing, in order of process, a method for forming an isolation oxide film region by a conventional improved selective oxidation separation method. , Figure 3 is a cross-sectional view of the process when self-alignment technology is applied to the isolation oxide film region formed by the conventional LOCO5 method, and Figure 4 is a cross-sectional view of the process formed by the conventional improved selective oxidation separation method. Aro-2]・-Silicon base, 22・・First pad oxide film,
23 - First nitride film, 24... Opening, 25... Groove, 26... Second pad oxide film, 27... Second nitride film, 28... Third oxide film, 31... Isolation oxide film. Figure 1 Figure 3 Figure 4

Claims (3)

【特許請求の範囲】[Claims] (1)シリコン基体上に第1のパッド酸化膜および第1
の窒化膜を順次形成し、該窒化膜および酸化膜に開口部
を形成する工程と、その開口部に対応する部分のシリコ
ン基体に、前記第1の窒化膜および第1のパッド酸化膜
の下にアンダーカットを有して溝を形成する工程と、そ
の溝の内面に第2のパッド酸化膜を形成し、さらに全表
面に第2の窒化膜および第3の膜を順次形成する工程と
、その後、前記開口部直下の第3の膜および第2の窒化
膜を選択的に除去する工程と、その後、第1の窒化膜お
よび第2の窒化膜をマスクとしてシリコン基体を酸化す
ることにより、溝部に分離酸化膜を形成し、その上に第
2の窒化膜、第3の膜ならびに第1の窒化膜の一部を押
し上げた状態とする工程と、続いて、第3の膜をマスク
として第1の窒化膜および第2の窒化膜の一部を除去す
ることにより、前記分離酸化膜の周辺部上にのみ第2の
窒化膜を残す工程とを具備してなる半導体集積回路装置
の製造方法。
(1) A first pad oxide film and a first pad oxide film on a silicon substrate.
nitride films are sequentially formed, openings are formed in the nitride films and oxide films, and a portion of the silicon substrate corresponding to the openings is formed under the first nitride film and the first pad oxide film. forming a groove with an undercut, forming a second pad oxide film on the inner surface of the groove, and sequentially forming a second nitride film and a third film on the entire surface; After that, a step of selectively removing the third film and the second nitride film directly under the opening, and then oxidizing the silicon substrate using the first nitride film and the second nitride film as a mask, A step of forming an isolation oxide film in the groove portion and pushing up a second nitride film, a third film, and a part of the first nitride film thereon, and then using the third film as a mask. manufacturing a semiconductor integrated circuit device comprising the step of: removing a portion of the first nitride film and the second nitride film to leave the second nitride film only on the peripheral portion of the isolation oxide film; Method.
(2)第3の膜は酸化膜であることを特徴とする特許請
求の範囲第1項記載の半導体集積回路装置の製造方法。
(2) The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the third film is an oxide film.
(3)第3の膜は多結晶シリコン膜であり、この多結晶
シリコン膜は、分離酸化膜形成時の酸化工程により酸化
膜となることを特徴とする特許請求の範囲第1項記載の
半導体集積回路装置の製造方法。
(3) The semiconductor according to claim 1, wherein the third film is a polycrystalline silicon film, and the polycrystalline silicon film becomes an oxide film through an oxidation process during formation of the isolation oxide film. A method of manufacturing an integrated circuit device.
JP60035290A 1985-02-26 1985-02-26 Method for manufacturing semiconductor integrated circuit device Expired - Lifetime JPH0715937B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60035290A JPH0715937B2 (en) 1985-02-26 1985-02-26 Method for manufacturing semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60035290A JPH0715937B2 (en) 1985-02-26 1985-02-26 Method for manufacturing semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS61196549A true JPS61196549A (en) 1986-08-30
JPH0715937B2 JPH0715937B2 (en) 1995-02-22

Family

ID=12437639

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60035290A Expired - Lifetime JPH0715937B2 (en) 1985-02-26 1985-02-26 Method for manufacturing semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0715937B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4863562A (en) * 1988-02-11 1989-09-05 Sgs-Thomson Microelectronics, Inc. Method for forming a non-planar structure on the surface of a semiconductor substrate

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56140646A (en) * 1980-03-10 1981-11-04 Western Electric Co Method of manufacturing semiconductor circuit on semiconductor silicon substrate

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56140646A (en) * 1980-03-10 1981-11-04 Western Electric Co Method of manufacturing semiconductor circuit on semiconductor silicon substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4863562A (en) * 1988-02-11 1989-09-05 Sgs-Thomson Microelectronics, Inc. Method for forming a non-planar structure on the surface of a semiconductor substrate

Also Published As

Publication number Publication date
JPH0715937B2 (en) 1995-02-22

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