JPS61151516A - Substrate for mis type active matrix display device - Google Patents
Substrate for mis type active matrix display deviceInfo
- Publication number
- JPS61151516A JPS61151516A JP59279311A JP27931184A JPS61151516A JP S61151516 A JPS61151516 A JP S61151516A JP 59279311 A JP59279311 A JP 59279311A JP 27931184 A JP27931184 A JP 27931184A JP S61151516 A JPS61151516 A JP S61151516A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- electrode
- substrate
- charge holding
- image
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Liquid Crystal (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、アクティブマトリクス液晶表示装置における
薄膜トランジスタ基板に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor substrate in an active matrix liquid crystal display device.
従来のアクティブマトリクス液晶表示装置の単位画素の
例を第2図(菊、 (6) 、 (13”)に示す。第
2図に)は、単位画素構造例の平面図を示し、第2図(
6)。An example of a unit pixel of a conventional active matrix liquid crystal display device is shown in FIG. (
6).
(c)は、そnぞn第2図に)のD−DI線とに−El
線に沿つ几断面図である。ガラス等の透明絶縁基板1上
には、Of、Ag10f、MQ 、AI等の遮光膜を兼
ねたゲート電極2が設けらn1行電極として延在してい
る。前段のゲート電極2′も図示さnている。ゲート電
極2上には、二酸化シリコン、チツ化シリコン等のゲー
ト絶a膜a、アモルファスシリコン等の半導体M5が2
000A〜5000ム位の膜厚で設けらn1半導体膜5
上には列電極としてのドレイン電極6、ソース電極7が
配さn、ソース電極7と画素電極4が接続さnている。(c) is connected to the D-DI line (see Figure 2) and -El
It is a sectional view of the box along the line. On a transparent insulating substrate 1 made of glass or the like, gate electrodes 2 which also serve as light shielding films such as Of, Ag10f, MQ2, AI, etc. are provided and extend as n1 row electrodes. The preceding gate electrode 2' is also shown. On the gate electrode 2, there is a gate insulating film a made of silicon dioxide, silicon oxide, etc., and a semiconductor M5 made of amorphous silicon, etc.
N1 semiconductor film 5 provided with a film thickness of about 000A to 5000μ
A drain electrode 6 and a source electrode 7 as column electrodes are arranged on the top, and the source electrode 7 and the pixel electrode 4 are connected.
画像信号等管保持するための電荷保持用容量は、前段の
ゲート電極21と絶縁膜8と画素電極4とで構成さnて
いる。さらに上部からの光を連間するために遮光膜やパ
ッシベーション膜等が形成さnるが、本発明に直接関係
ないので省略する。このように、光を連間する他行のゲ
ート電極配線21と画素電極4で電荷保持用容量を形成
する几め、表示として有効な画素面積即ち開孔率が減少
してしまう欠点を有する。また開孔率を大きくする几め
に、電荷保持用容量を形成しない方法も考えらnるが、
液晶の容量が電圧依存性金持っているのと、寄生容量等
のために画像信号等の九めに画像信号等が歪み、画像劣
化の原因となっているため、良好な画像を得るためには
、電荷保持用容量が必要で、かつ大きい方が良い。A charge holding capacitor for holding image signals, etc. is composed of the gate electrode 21 at the previous stage, the insulating film 8, and the pixel electrode 4. Furthermore, a light shielding film, a passivation film, etc. are formed to pass light from above, but these are omitted as they are not directly related to the present invention. As described above, the method of forming a charge holding capacitor between the gate electrode wiring 21 of the other row and the pixel electrode 4 that connects light has the disadvantage that the effective pixel area for display, that is, the aperture ratio is reduced. In addition, in order to increase the porosity, a method that does not form a charge retention capacitor may be considered, but
In order to obtain a good image, the capacitance of the liquid crystal is voltage-dependent, and the image signal is distorted due to parasitic capacitance, etc., causing image deterioration. requires a charge retention capacitor, and the larger the capacitor, the better.
第2図b> 、 G[+)及び(C)の例から分るよう
に、従来は、開孔率が小さくなり、かつ電荷保持容量を
大きくとnず良好な画質が得られなかったが、本発明は
、工数を特に増加しないで、開孔率が大きくかつ電荷保
持容量も大きく良好な画像表示を持つアクティブマトリ
クス液晶表示装置用基板を提供することを目的とする。As can be seen from the examples in Fig. 2b>, G[+), and (C), in the past, good image quality could not be obtained unless the aperture ratio was small and the charge retention capacity was large. SUMMARY OF THE INVENTION An object of the present invention is to provide a substrate for an active matrix liquid crystal display device that has a large porosity, a large charge holding capacity, and a good image display without particularly increasing the number of man-hours.
上記問題点を解決するtめに本発明は、ゲート電極を透
明導電膜で形成し、ゲート電極と画素電極とで構成され
る電荷保持用容量部が光を透過する構造にする。なお、
半導体膜は、光の影響を受けにくい膜厚(例えば100
0A以下〕に形成する。In order to solve the above-mentioned problems, the present invention forms the gate electrode with a transparent conductive film, and has a structure in which the charge holding capacitor section composed of the gate electrode and the pixel electrode transmits light. In addition,
The semiconductor film has a thickness that is not easily affected by light (for example, 100
0A or less].
上記のように構成すると、ゲート電極と画素電極で形成
さnる電荷保持用容量部が、光を透過するので開孔率が
大きくなり、かつゲート電極を大きくして電荷保持用容
量を大きく出来て、工数を増加することなく良好な画質
を得ることが出来る〔実施例〕
以下に本発明の実施例を図面に基づいて説明する。第1
図6)、の)及び(G)は、本発明の単位画素の構造例
を示す。第1図の)、ω)は、そn−’Pn第1第1図
人−A1線とB−、Bl線に沿った断面図である。ガラ
ス等の透明絶縁基板1上には、工To等の透明導電膜で
形成さnるゲート電極2が設けらn1行電極として延在
している。前段のゲート電極2′も図示している。ゲー
ト電極上2には、二酸化シリコン、チツ化シリコン等の
ゲート絶縁膜8、アモルファスシリコン等の半導体膜5
が形成さnている。なおアモルファスシリコンの膜厚ハ
、光の影響を受けにくい膜厚(例えば100OA以下〕
に形成さnている。前段のゲート電極2I上には、前記
ゲート絶縁膜8と同時に形成さrL九絶Hk膜8が形成
さ3% 工To等の透明導電膜である画素電極4の一部
とくよって電荷保持用容量が構成さnている。半導体膜
5上には、列電極としてのドレイン電極6、ソース電極
7が配さn1ソース電極7と画素電極4が接続さnてい
る。さらくバツシベーショ/膜等も形成さnる場合もあ
る単位画素をこのような構造にすると、前段のゲート電
極21と画素電極4で構成さnる電荷保持用容量部が光
を透過するので開孔率が大きく々る。また第1図6)に
示すように、ゲート電極巾を大きくして画素電極4との
オーバーラツプを大きくして電荷保持用容量も大きく形
成することが出来る。tx第8図ら)は、ゲート電極配
線部9を幅広くして、ゲートライン断線を起きに<<シ
た本発明の他の平面構造例を示す。第8図の)は1電荷
保持用容量部のゲートライン2′のライン端部と画素電
極4との交差を出来るだけ少なくして、耐圧不良の発生
を起きに〈<シた本発明の他の平面構造例を示す。なお
、第8図(d 、 (6)では、半導体膜、ソース、ド
レイン電極等は、図示してない。With the above configuration, the charge retention capacitor portion formed by the gate electrode and the pixel electrode transmits light, so the aperture ratio increases, and the gate electrode can be enlarged to increase the charge retention capacitance. [Embodiment] An embodiment of the present invention will be described below based on the drawings. 1st
FIGS. 6), 6) and 6(G) show examples of the structure of the unit pixel of the present invention. ) and ω) in FIG. 1 are cross-sectional views taken along lines A1 and B- and Bl in FIG. On a transparent insulating substrate 1 made of glass or the like, gate electrodes 2 made of a transparent conductive film such as Toxic oxide are provided and extend as n1 row electrodes. The preceding gate electrode 2' is also shown. On the gate electrode 2, there is a gate insulating film 8 made of silicon dioxide, silicon nitride, etc., and a semiconductor film 5 made of amorphous silicon etc.
is formed. Note that the film thickness of amorphous silicon is a film thickness that is not easily affected by light (for example, 100 OA or less).
It is formed in n. On the gate electrode 2I in the previous stage, a rL9Hk film 8 is formed simultaneously with the gate insulating film 8, and is combined with a part of the pixel electrode 4, which is a transparent conductive film such as 3% toner, to form a charge retention capacitor. is composed of n. A drain electrode 6 and a source electrode 7 as column electrodes are arranged on the semiconductor film 5, and the source electrode 7 and the pixel electrode 4 are connected. If a unit pixel has such a structure, in which a buffer/film etc. may also be formed, the charge holding capacitor formed by the gate electrode 21 and the pixel electrode 4 in the previous stage will transmit light, so it will not open. The porosity is large. Furthermore, as shown in FIG. 1 (6), the width of the gate electrode is increased to increase the overlap with the pixel electrode 4, thereby making it possible to form a large charge holding capacitor. tx FIG. 8 et al.) show another planar structure example of the present invention in which the gate electrode wiring portion 9 is widened to prevent gate line disconnection. ) in FIG. 8 is to reduce the intersection of the line end of the gate line 2' of the charge holding capacitor section and the pixel electrode 4 as much as possible to prevent breakdown voltage failure. An example of the planar structure is shown below. Note that in FIG. 8(d), (6), the semiconductor film, source, drain electrodes, etc. are not shown.
本発明は、以上説明し九ように、電荷保持容量が十分大
きくとn、かつ開孔率の大きい単位画素を得ることがで
き、明るく、コント乏ストの良い良好な画質を持り九低
コストのMIS城アクティブマトリクス表示装置用の薄
膜トランジスタ基板を提供できる。As explained above, the present invention makes it possible to obtain a unit pixel with a sufficiently large charge holding capacity and a large aperture ratio, and has a bright, good image quality with good contrast, and is low cost. The present invention can provide a thin film transistor substrate for an MIS active matrix display device.
第1図@は一本発明による単位画素構造例を示す平面図
であり、第1図(6) 、 (c)はそnぞn第1図(
ロ)A−AI線とB−Bl線に沿った断面図である。第
2図@は、従来の単位画素構造例の平面図でめり、第2
図の)、C)はそn、(′n第2図(m+7)D−が線
とm−z線に沿った断面図である。第8図(2)。
の)は本発明による他の実施例の平面図を示す。
10.基板、2.2’、、ゲート電極、8゜。
絶縁膜、411画素電極、59.半導体膜、6゜、ドレ
イン電極、71.ソース電極、80.絶縁膜、90.配
線部
以上
出願人 セイコー電子工業株式会社
代理人 弁理士 最 上 務
第1図Cb)
第1回(C)
第2図(b)
第2図(C)
41i誤a、S
第3図(b)Figure 1 @ is a plan view showing an example of a unit pixel structure according to the present invention, and Figure 1 (6) and (c) are the same as Figure 1 (
B) It is a sectional view taken along the A-AI line and the B-Bl line. Figure 2 @ is a plan view of an example of a conventional unit pixel structure.
), C) are cross-sectional views taken along the lines (m+7) and m-z in FIG. 2 (m+7) and m-z. FIG. 3 shows a plan view of an embodiment of the invention. 10. Substrate, 2.2', Gate electrode, 8°. Insulating film, 411 pixel electrode, 59. Semiconductor film, 6°, drain electrode, 71. source electrode, 80. Insulating film, 90. Wiring Department and above Applicant Seiko Electronic Industries Co., Ltd. Agent Patent Attorney Mogami Affairs Figure 1 Cb) 1st (C) Figure 2 (b) Figure 2 (C) 41i erroneous a, S Figure 3 (b) )
Claims (1)
縁膜と透明導電膜からなる画素電極の一部とによつて構
成されたMIS型アクティブマトリクス表示装置用基板
において、前記ゲート電極が透明導電膜で形成されたこ
とを特徴とするMIS型アクティブマトリクス表示装置
用基板。In a substrate for an MIS type active matrix display device, in which at least a charge retention capacitor section is constituted by a preceding gate electrode, an insulating film, and a part of a pixel electrode made of a transparent conductive film, the gate electrode is formed of a transparent conductive film. A substrate for an MIS type active matrix display device, characterized in that it is formed of.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59279311A JPS61151516A (en) | 1984-12-25 | 1984-12-25 | Substrate for mis type active matrix display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59279311A JPS61151516A (en) | 1984-12-25 | 1984-12-25 | Substrate for mis type active matrix display device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61151516A true JPS61151516A (en) | 1986-07-10 |
Family
ID=17609393
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59279311A Pending JPS61151516A (en) | 1984-12-25 | 1984-12-25 | Substrate for mis type active matrix display device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61151516A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02234124A (en) * | 1989-03-08 | 1990-09-17 | Hitachi Ltd | liquid crystal display device |
JPH02250038A (en) * | 1989-03-23 | 1990-10-05 | Seiko Instr Inc | Thin film transistor array |
US5162901A (en) * | 1989-05-26 | 1992-11-10 | Sharp Kabushiki Kaisha | Active-matrix display device with added capacitance electrode wire and secondary wire connected thereto |
US5231039A (en) * | 1988-02-25 | 1993-07-27 | Sharp Kabushiki Kaisha | Method of fabricating a liquid crystal display device |
US5447261A (en) * | 1992-02-12 | 1995-09-05 | Nifco Inc. | Carrier bag |
US5463230A (en) * | 1989-08-11 | 1995-10-31 | Sharp Kabushiki Kaisha | Active matrix board |
US6235546B1 (en) * | 1989-12-22 | 2001-05-22 | North American Philips Corporation | Method of forming an active matrix electro-optic display device with storage capacitors |
-
1984
- 1984-12-25 JP JP59279311A patent/JPS61151516A/en active Pending
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5231039A (en) * | 1988-02-25 | 1993-07-27 | Sharp Kabushiki Kaisha | Method of fabricating a liquid crystal display device |
JPH02234124A (en) * | 1989-03-08 | 1990-09-17 | Hitachi Ltd | liquid crystal display device |
JPH02250038A (en) * | 1989-03-23 | 1990-10-05 | Seiko Instr Inc | Thin film transistor array |
US5162901A (en) * | 1989-05-26 | 1992-11-10 | Sharp Kabushiki Kaisha | Active-matrix display device with added capacitance electrode wire and secondary wire connected thereto |
US5463230A (en) * | 1989-08-11 | 1995-10-31 | Sharp Kabushiki Kaisha | Active matrix board |
US6235546B1 (en) * | 1989-12-22 | 2001-05-22 | North American Philips Corporation | Method of forming an active matrix electro-optic display device with storage capacitors |
US5447261A (en) * | 1992-02-12 | 1995-09-05 | Nifco Inc. | Carrier bag |
US5588569A (en) * | 1992-02-12 | 1996-12-31 | Nifco, Inc. | Carrier bag |
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