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JPH04358127A - Thin film transistor type liquid crystal display device - Google Patents

Thin film transistor type liquid crystal display device

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Publication number
JPH04358127A
JPH04358127A JP3116423A JP11642391A JPH04358127A JP H04358127 A JPH04358127 A JP H04358127A JP 3116423 A JP3116423 A JP 3116423A JP 11642391 A JP11642391 A JP 11642391A JP H04358127 A JPH04358127 A JP H04358127A
Authority
JP
Japan
Prior art keywords
electrode
insulating film
thin film
film transistor
liquid crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3116423A
Other languages
Japanese (ja)
Inventor
Shigeki Ogura
小椋 茂樹
Tamahiko Nishiki
玲彦 西木
▲よし▼澤 佳代
Yoshiyo Yoshizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP3116423A priority Critical patent/JPH04358127A/en
Publication of JPH04358127A publication Critical patent/JPH04358127A/en
Withdrawn legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To prevent the electrostatic breakdown of a gate insulating film and a light leak near a drain electrode by providing a shield electrode among the drain electrode, the channel part of a TFT, and liquid crystal and applying nearly the same potential with a counter electrode. CONSTITUTION:A thin film transistor(TFT) substrate has a 1st insulating film 12, formed on a gate electrode 1, a 2nd insulating film 13 which is formed over the entire surface of the 1st insulating film except at the connection part between a source electrode 8 and a picture element electrode 4, and the shield electrode 11 which is formed over the entire surface of the 2nd insulating film except the connection part between the source electrode 8 and picture element electrode 4. Further, the substrate is equipped with a 3rd insulating film 14 which is formed over the entire surface of the shield electrode except at the connection part between the source electrode 8 and picture element electrode 4 and the picture element electrode 4 formed on the 3rd insulating film. In this case, a voltage inputted to the shield electrode 11 is nearly as high as a voltage inputted to the counter electrode of a counter electrode substrate. Then the shield electrode 11 and the electrode substrate which faces the TFT are electrically connected.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、薄膜トランジスタ型液
晶表示装置、特にその薄膜トランジスタ基板における電
極構造とパターンに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor type liquid crystal display device, and particularly to an electrode structure and pattern on a thin film transistor substrate thereof.

【0002】0002

【従来の技術】従来、この分野の技術としては例えば「
EID90−6,ED90−35,IE90−15,1
0.4型カラーTFT−LCDの開発」に記載されたも
のが知られている。図5は前記文献等に記載されている
薄膜トランジスタ(以下、「TFT」という)の構造を
示す一部断面図である。
[Prior Art] Conventionally, as a technology in this field, for example,
EID90-6, ED90-35, IE90-15, 1
The one described in ``Development of 0.4-inch color TFT-LCD'' is known. FIG. 5 is a partial cross-sectional view showing the structure of a thin film transistor (hereinafter referred to as "TFT") described in the above-mentioned literature.

【0003】従来、薄膜トランジスタ型液晶表示装置(
以下「TFT−LCD」という)におけるTFT構造は
、図5に示されるような逆スタガ型構造が主流であった
。すなわち、ゲート電極32は最も下に形成されており
、ゲート絶縁膜34、半導体層35、オーミック接合層
36と続いて形成された後、ドレイン−ソース電極37
,38が形成されるという構造である。また、画素電極
33は、この図のようにドレイン−ソース電極37,3
8より後に形成されるものと、先に形成されるものとが
あり、どちらかが採用されている。そして、最後にパッ
シベーション膜39が設けられている。
Conventionally, thin film transistor type liquid crystal display devices (
The mainstream TFT structure in TFT-LCDs (hereinafter referred to as "TFT-LCD") has been an inverted staggered structure as shown in FIG. That is, the gate electrode 32 is formed at the bottom, and after the gate insulating film 34, semiconductor layer 35, and ohmic contact layer 36 are formed successively, the drain-source electrode 37 is formed.
, 38 are formed. Further, the pixel electrode 33 has drain-source electrodes 37 and 3 as shown in this figure.
There are some that are formed after 8 and others that are formed before 8, and either one is adopted. Finally, a passivation film 39 is provided.

【0004】0004

【発明が解決しようとする課題】しかしながら、こうい
った従来の構造のTFT−LCDにはいくつかの問題点
がある。まず第1に、TFT−LCDを作成する上で、
配向膜をTFT基板に塗布し、ラビングする工程がある
が、その時に静電気が発生し易いため、ゲート絶縁膜の
静電破壊によるゲート−ドレイン電極間ショート、又は
、ゲート−ソース電極間ショートが起きてしまうという
問題点があった。
SUMMARY OF THE INVENTION However, these conventional TFT-LCD structures have several problems. First of all, in creating a TFT-LCD,
There is a process of applying an alignment film to the TFT substrate and rubbing it, but static electricity is likely to be generated during this process, resulting in shorting between the gate and drain electrodes or between the gate and source electrodes due to electrostatic breakdown of the gate insulating film. There was a problem with this.

【0005】第2に、ドレイン電極がその上にある液晶
層と容量結合しているため、ドレイン信号が液晶層に入
り込み、ドレイン電極脇の光漏れが生じるという点であ
る。本発明は、以上述べたラビングの時の絶縁膜破壊と
ドレイン電極脇の光漏れを解決して、表示品質の優れた
TFT−LCDを提供することを目的とする。
Second, since the drain electrode is capacitively coupled to the liquid crystal layer above it, the drain signal enters the liquid crystal layer, causing light leakage near the drain electrode. An object of the present invention is to provide a TFT-LCD with excellent display quality by solving the above-mentioned problems of insulating film breakdown during rubbing and light leakage near the drain electrode.

【0006】[0006]

【課題を解決するための手段】前記問題点を解決するた
めに、本発明は、複数のゲート電極と、ゲート電極と交
差する複数のドレイン電極と、その交差部に設けられた
TFTと、TFTのソース電極に接続された画素電極と
を有するTFT基板と、液晶を挟んでTFT基板と対向
する対向電極基板とを備えたTFT−LCDにおいて、
TFT基板は、ゲート電極の上に形成された第1絶縁膜
と、第1絶縁膜上で、かつ、ソース電極と画素電極との
接続部以外の全面に形成された第2絶縁膜と、第2絶縁
膜上で、かつ、ソース電極と画素電極との接続部以外の
全面に形成された遮蔽電極と、遮蔽電極上で、かつ、ソ
ース電極と画素電極との接続部以外の全面に形成された
第3絶縁膜と、第3絶縁膜上に形成された画素電極とを
備え、かつ、遮蔽電極に入力する電圧が対向電極基板の
対向電極に入力する電圧と同程度になるように構成した
Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a plurality of gate electrodes, a plurality of drain electrodes intersecting with the gate electrodes, a TFT provided at the intersection, and a TFT. In a TFT-LCD including a TFT substrate having a pixel electrode connected to a source electrode of the TFT substrate, and a counter electrode substrate facing the TFT substrate with a liquid crystal in between,
The TFT substrate includes a first insulating film formed on the gate electrode, a second insulating film formed on the first insulating film and on the entire surface other than the connecting portion between the source electrode and the pixel electrode, and 2. A shielding electrode formed on the insulating film and on the entire surface other than the connection portion between the source electrode and the pixel electrode; and and a pixel electrode formed on the third insulating film, and configured such that the voltage input to the shielding electrode is approximately the same as the voltage input to the counter electrode of the counter electrode substrate. .

【0007】[0007]

【作用】本発明によれば、以上のようにTFT−LCD
を構成したので、ドレイン電極上の電圧信号は遮蔽電極
により遮蔽され、液晶層に入らなくなる。また、遮蔽電
極と画素電極との間に形成される蓄積容量がゲート−ソ
ース電極間寄生容量に起因する画素電極電圧のシフトダ
ウンを軽減させる。さらに、TFTのチャネル部の上の
遮蔽電極がゲート絶縁膜の静電破壊を防止する。
[Operation] According to the present invention, as described above, the TFT-LCD
, the voltage signal on the drain electrode is shielded by the shielding electrode and does not enter the liquid crystal layer. Furthermore, the storage capacitor formed between the shield electrode and the pixel electrode reduces downshifting of the pixel electrode voltage caused by the parasitic capacitance between the gate and source electrodes. Furthermore, a shielding electrode above the channel portion of the TFT prevents electrostatic breakdown of the gate insulating film.

【0008】[0008]

【実施例】以下、本発明の実施例について図面を参照し
ながら詳細に説明する。図1は本発明の実施例における
TFT基板の電極パターンを示す平面図、図2は本発明
の実施例におけるTFT基板の一部(図1のA−A′)
断面図である。まず図1及び図2に示すように、本実施
例におけるTFT基板の電極パターンの基本構造は、ゲ
ート電極1とドレイン電極2が交差する場所において半
導体層3をチャネルとするトランジスタが形成され、ソ
ース電極8と画素電極4は第1スルーホール6により電
気的に接続されている。
Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a plan view showing the electrode pattern of a TFT substrate in an embodiment of the present invention, and FIG. 2 is a part of the TFT substrate in an embodiment of the present invention (A-A' in FIG. 1).
FIG. First, as shown in FIGS. 1 and 2, the basic structure of the electrode pattern of the TFT substrate in this example is that a transistor with the semiconductor layer 3 as a channel is formed at the intersection of the gate electrode 1 and the drain electrode 2, and the source The electrode 8 and the pixel electrode 4 are electrically connected through the first through hole 6.

【0009】そして、図2に示すように、最も下に形成
されているゲート電極1の上には、ゲート絶縁膜として
機能する第1絶縁膜12が全面に形成されている。なお
、本実施例ではゲート電極1の表面は陽極酸化され、ゲ
ート−ドレイン電極1,2間のショートを防ぐためのゲ
ート陽極酸化膜9が形成されている。この第1絶縁膜1
2の上には半導体層3が図1に示すパターンで形成され
ている。半導体層3は、トランジスタのチャネル部にの
みあればよいのであるが、このパターンとしたのはゲー
ト−ドレイン電極1,2間のショート低減等のためであ
る。
As shown in FIG. 2, a first insulating film 12 functioning as a gate insulating film is formed over the entire surface of the gate electrode 1 formed at the bottom. In this embodiment, the surface of the gate electrode 1 is anodized, and a gate anodic oxide film 9 is formed to prevent short circuit between the gate and drain electrodes 1 and 2. This first insulating film 1
A semiconductor layer 3 is formed on the semiconductor layer 2 in the pattern shown in FIG. The semiconductor layer 3 only needs to be provided in the channel portion of the transistor, but this pattern is used to reduce short circuits between the gate and drain electrodes 1 and 2.

【0010】この半導体層3の上にはオーミック接合層
10があるが、そのパターンはドレイン電極2とソース
電極8と半導体層3の重なる部分に形成されている。オ
ーミック接合層10もこのパターンである必要はなく、
上記と同じ理由でこのパターンとなっている。このオー
ミック接合層10の上に、ドレイン−ソース電極2,8
が図1に示すようなパターンで形成されている。このパ
ターンはごく一般的なものである。
[0010] There is an ohmic contact layer 10 on this semiconductor layer 3, and its pattern is formed in a portion where the drain electrode 2, the source electrode 8, and the semiconductor layer 3 overlap. The ohmic contact layer 10 also does not need to have this pattern,
This pattern is used for the same reason as above. On this ohmic contact layer 10, drain-source electrodes 2, 8
are formed in a pattern as shown in FIG. This pattern is quite common.

【0011】ドレイン−ソース電極2,8の上には第2
絶縁膜13が、図2に示すように、第1スルーホール6
を除いて全面に形成されている。この第2絶縁膜13は
、この後に形成される遮蔽電極11とドレイン−ソース
電極2,8を電気的に非接続にするために必要である。 この第2絶縁膜13の上には、ITO等の透明な物質か
らなる遮蔽電極11が、第1,第2スルーホール6,7
以外に形成されており、図1には遮蔽電極開口部5とし
て示される。このような構造にすることにより、ドレイ
ン電極2上の信号は遮蔽電極11によって遮蔽されるこ
とが分かる。また、トランジスタのチャネル部の上にも
遮蔽電極11があるので、トランジスタのチャネル部は
電気的に守られる。なお、トランジスタのチャネル部を
除くゲート電極1上に遮蔽電極11を形成するとゲート
−遮蔽電極1,11間に容量が生じ、ゲート電圧パルス
が歪むので、本実施例においてはそこには遮蔽電極11
を形成していない。
[0011] On the drain-source electrodes 2 and 8, a second
As shown in FIG.
It is formed on the entire surface except for. This second insulating film 13 is necessary to electrically disconnect the shielding electrode 11 and the drain-source electrodes 2 and 8, which will be formed later. On this second insulating film 13, a shielding electrode 11 made of a transparent material such as ITO is installed in the first and second through holes 6, 7.
1, and is shown as a shield electrode opening 5 in FIG. It can be seen that by adopting such a structure, the signal on the drain electrode 2 is shielded by the shielding electrode 11. Further, since the shield electrode 11 is also provided on the channel portion of the transistor, the channel portion of the transistor is electrically protected. Note that if the shield electrode 11 is formed on the gate electrode 1 except for the channel part of the transistor, a capacitance will be generated between the gate and the shield electrodes 1 and 11, and the gate voltage pulse will be distorted.
is not formed.

【0012】この遮蔽電極11の上には、第2スルーホ
ール7以外に形成される第3絶縁膜14があり、さらに
、第3絶縁膜14の上に画素電極4が形成されている。 また、画素電極4はソース電極8と第1,第2スルーホ
ール6,7によって電気的に接続されている。このよう
に遮蔽電極11を形成すると、画素電極4のパターンを
ドレイン電極2と重なるくらいに延在させることができ
る。また、画素電極4と遮蔽電極11の間には、画素−
遮蔽電極間容量を持たせることができる。
A third insulating film 14 is formed on the shielding electrode 11 except for the second through hole 7, and further, a pixel electrode 4 is formed on the third insulating film 14. Furthermore, the pixel electrode 4 is electrically connected to the source electrode 8 through first and second through holes 6 and 7. By forming the shield electrode 11 in this manner, the pattern of the pixel electrode 4 can be extended to the extent that it overlaps with the drain electrode 2. Furthermore, between the pixel electrode 4 and the shielding electrode 11, the pixel
Capacitance between shield electrodes can be provided.

【0013】図3は、本発明の実施例によるTFT−L
CDの1画素あたりの等価回路図である。この図に示す
通り、ゲート電極1とドレイン電極2の交差する場所に
トランジスタ15が配置されている。ここで、ソース電
極は画素電極4と第1,第2スルーホールによって電気
的に接続しているので、一括して画素電極4として示し
てある。この画素電極4と対向電極基板上の対向電極1
7の間に液晶層16がある。一方、遮蔽電極11は、画
素電極4との重なり部分において、第3絶縁膜からなる
画素−遮蔽電極間容量19を有することになり、かつ、
第2絶縁膜からなる遮蔽−ドレイン電極間容量20も有
することになる。
FIG. 3 shows a TFT-L according to an embodiment of the present invention.
It is an equivalent circuit diagram per pixel of CD. As shown in this figure, a transistor 15 is arranged at a location where gate electrode 1 and drain electrode 2 intersect. Here, since the source electrode is electrically connected to the pixel electrode 4 through the first and second through holes, they are collectively shown as the pixel electrode 4. This pixel electrode 4 and the counter electrode 1 on the counter electrode substrate
7, there is a liquid crystal layer 16 between them. On the other hand, the shield electrode 11 has a pixel-shield electrode capacitance 19 made of the third insulating film in the overlapped portion with the pixel electrode 4, and
It also has a shield-drain electrode capacitance 20 made of the second insulating film.

【0014】このようにして、ドレイン電極2と画素電
極4間の容量結合は遮蔽電極11により回避される。ま
た、ドレイン電極2上の信号が液晶層16に入り込むの
も防ぐことができる。しかしながら、本発明においても
、ゲート−ソース電極間容量18の存在によるゲート信
号の画素電極への影響、すなわち画素電極電圧のシフト
ダウンは残るが、画素電極4からみた容量としては、画
素−遮蔽電極間容量19があるので、前記文献の記載か
ら明らかなように、シフトダウンの程度は軽減される。
In this way, capacitive coupling between the drain electrode 2 and the pixel electrode 4 is avoided by the shield electrode 11. Further, it is also possible to prevent signals on the drain electrode 2 from entering the liquid crystal layer 16. However, even in the present invention, the influence of the gate signal on the pixel electrode due to the existence of the capacitance 18 between the gate and source electrodes, that is, the shift down of the pixel electrode voltage remains, but the capacitance seen from the pixel electrode 4 is Since there is an intermediate capacity 19, the degree of downshifting is reduced, as is clear from the description in the above-mentioned document.

【0015】ここで、遮蔽電極11と対向電極17との
間に液晶を駆動する閾値電位Vth以上の電位差を生じ
ないようにすることが必要である。本実施例においては
、遮蔽電極11と対向電極17を電気的に接続し、同一
の信号を入力した。この電気的接続をTFTアレイ外部
において行うことは、遮蔽電極11と対向電極17がど
ちらも一枚のベタ電極であるために容易である。なお、
遮蔽電極11と対向電極17に必ずしも同一の信号を入
れる必要はなく、要するに、対向電極17と遮蔽電極1
1の間では常に直流的にVth以下であればよい。
Here, it is necessary to prevent a potential difference greater than the threshold potential Vth for driving the liquid crystal from occurring between the shielding electrode 11 and the counter electrode 17. In this example, the shielding electrode 11 and the counter electrode 17 were electrically connected and the same signal was input. It is easy to make this electrical connection outside the TFT array because both the shielding electrode 11 and the counter electrode 17 are one solid electrode. In addition,
It is not necessary to input the same signal to the shielding electrode 11 and the counter electrode 17;
1, it is sufficient that the voltage is always below Vth in terms of direct current.

【0016】図4は、本発明の実施例によるTFT−L
CDの電気的ブロック図である。ゲートドライバ、ドレ
インドライバ及び対向電極信号入力は従来のTFT−L
CDにおいても設けられていたものであり、本実施例に
おいては、対向電極17及び遮蔽電極11を接続して入
力端子24から共通の信号を入れるのみでよいので、回
路としても全く複雑化することはない。
FIG. 4 shows a TFT-L according to an embodiment of the present invention.
FIG. 2 is an electrical block diagram of a CD. Gate driver, drain driver and counter electrode signal input are conventional TFT-L
This is also provided in the CD, and in this embodiment, it is only necessary to connect the counter electrode 17 and the shield electrode 11 and input a common signal from the input terminal 24, so the circuit is not complicated at all. There isn't.

【0017】なお、本発明は上記実施例に限定されるも
のではなく、本発明の趣旨に基づき種々の変形が可能で
あり、それらを本発明の範囲から排除するものではない
It should be noted that the present invention is not limited to the above-mentioned embodiments, and various modifications can be made based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

【0018】[0018]

【発明の効果】以上詳細に説明したように、本発明によ
れば、ドレイン電極及びTFTのチャネル部と液晶の間
に遮蔽電極を設け、それに対向電極と同程度の電位を与
えたので、ラビング時の絶縁膜の静電破壊を防ぐことが
でき、かつ、ドレイン電極脇の光漏れを防ぐことかでき
る。
As explained in detail above, according to the present invention, a shielding electrode is provided between the drain electrode, the channel portion of the TFT, and the liquid crystal, and a potential similar to that of the counter electrode is applied to the shielding electrode. It is possible to prevent electrostatic discharge damage to the insulating film at the time of use, and also to prevent light leakage near the drain electrode.

【0019】また、画素−遮蔽電極間に容量を設けたの
で、ゲート−ソース電極間寄生容量による画素電極電位
のシフトダウンが低減する。
Furthermore, since a capacitor is provided between the pixel and the shield electrode, downshifting of the pixel electrode potential due to parasitic capacitance between the gate and source electrodes is reduced.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の実施例におけるTFT基板の電極パタ
ーンを示す平面図である。
FIG. 1 is a plan view showing an electrode pattern of a TFT substrate in an example of the present invention.

【図2】本発明の実施例におけるTFT基板の一部(図
1のA−A′)断面図である。
FIG. 2 is a cross-sectional view (along line AA' in FIG. 1) of a portion of a TFT substrate in an embodiment of the present invention.

【図3】本発明の実施例によるTFT−LCDの1画素
あたりの等価回路図である。
FIG. 3 is an equivalent circuit diagram per pixel of a TFT-LCD according to an embodiment of the present invention.

【図4】本発明の実施例によるTFT−LCDの電気的
ブロック図である。
FIG. 4 is an electrical block diagram of a TFT-LCD according to an embodiment of the present invention.

【図5】従来のTFT基板の一部断面図である。FIG. 5 is a partial cross-sectional view of a conventional TFT substrate.

【符号の説明】[Explanation of symbols]

1      ゲート電極 2      ドレイン電極 3      半導体層 4      画素電極 5      遮蔽電極開口部 6      第1スルーホール 7      第2スルーホール 8      ソース電極 11    遮蔽電極 12    第1絶縁膜 13    第2絶縁膜 14    第3絶縁膜 1 Gate electrode 2 Drain electrode 3 Semiconductor layer 4 Pixel electrode 5 Shield electrode opening 6 1st through hole 7 2nd through hole 8 Source electrode 11 Shielding electrode 12 First insulation film 13 Second insulating film 14 Third insulating film

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】  複数のゲート電極と、該ゲート電極と
交差する複数のドレイン電極と、その交差部に設けられ
た薄膜トランジスタと、該薄膜トランジスタのソース電
極に接続された画素電極とを有する薄膜トランジスタ基
板と、液晶を挟んで該薄膜トランジスタ基板と対向する
対向電極基板とを備えた薄膜トランジスタ型液晶表示装
置において、前記薄膜トランジスタ基板は、(a)前記
ゲート電極の上に形成された第1絶縁膜と、(b)該第
1絶縁膜上で、かつ、前記ソース電極と前記画素電極と
の接続部以外の全面に形成された第2絶縁膜と、(c)
該第2絶縁膜上で、かつ、前記ソース電極と前記画素電
極との接続部以外の全面に形成された遮蔽電極と、(d
)該遮蔽電極上で、かつ、前記ソース電極と前記画素電
極との接続部以外の全面に形成された第3絶縁膜と、(
e)該第3絶縁膜上に形成された前記画素電極とを備え
、かつ、前記遮蔽電極に入力する電圧を前記対向電極基
板の対向電極に入力する電圧と同程度にすることを特徴
とする薄膜トランジスタ型液晶表示装置。
1. A thin film transistor substrate having a plurality of gate electrodes, a plurality of drain electrodes intersecting the gate electrodes, a thin film transistor provided at the intersection thereof, and a pixel electrode connected to the source electrode of the thin film transistor. , a thin film transistor type liquid crystal display device comprising a counter electrode substrate facing the thin film transistor substrate with a liquid crystal in between, the thin film transistor substrate comprising: (a) a first insulating film formed on the gate electrode; and (b) ) a second insulating film formed on the first insulating film and on the entire surface other than the connecting portion between the source electrode and the pixel electrode;
a shielding electrode formed on the second insulating film and on the entire surface other than the connecting portion between the source electrode and the pixel electrode;
) a third insulating film formed on the shielding electrode and on the entire surface other than the connecting portion between the source electrode and the pixel electrode;
e) the pixel electrode formed on the third insulating film, and the voltage input to the shielding electrode is made to be approximately the same as the voltage input to the counter electrode of the counter electrode substrate. Thin film transistor type liquid crystal display device.
【請求項2】  遮蔽電極と薄膜トランジスタと対向す
る電極基板の対向電極とを電気的に接続したことをする
ことを特徴とする請求項1記載の薄膜トランジスタ型液
晶表示装置。
2. The thin film transistor type liquid crystal display device according to claim 1, wherein the shield electrode and a counter electrode of an electrode substrate facing the thin film transistor are electrically connected.
JP3116423A 1991-05-22 1991-05-22 Thin film transistor type liquid crystal display device Withdrawn JPH04358127A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3116423A JPH04358127A (en) 1991-05-22 1991-05-22 Thin film transistor type liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3116423A JPH04358127A (en) 1991-05-22 1991-05-22 Thin film transistor type liquid crystal display device

Publications (1)

Publication Number Publication Date
JPH04358127A true JPH04358127A (en) 1992-12-11

Family

ID=14686723

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3116423A Withdrawn JPH04358127A (en) 1991-05-22 1991-05-22 Thin film transistor type liquid crystal display device

Country Status (1)

Country Link
JP (1) JPH04358127A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5426313A (en) * 1993-04-22 1995-06-20 Nec Corporation Thin film transistor array having optical shield layer
EP0682282A2 (en) * 1994-05-13 1995-11-15 THOMSON multimedia S.A. Liquid crystal display device with shielded pixel structure
JPH08338998A (en) * 1995-06-13 1996-12-24 Nec Corp Active matrix type liquid crystal display device and its production
EP0766120A2 (en) * 1995-09-27 1997-04-02 Sharp Kabushiki Kaisha Active matrix substrate and display device incorporating the same
US5786876A (en) * 1994-03-17 1998-07-28 Hitachi, Ltd. Active matrix type liquid crystal display system
US6982768B2 (en) 1996-02-20 2006-01-03 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5426313A (en) * 1993-04-22 1995-06-20 Nec Corporation Thin film transistor array having optical shield layer
US5786876A (en) * 1994-03-17 1998-07-28 Hitachi, Ltd. Active matrix type liquid crystal display system
EP0682282A2 (en) * 1994-05-13 1995-11-15 THOMSON multimedia S.A. Liquid crystal display device with shielded pixel structure
EP0682282A3 (en) * 1994-05-13 1996-01-10 Thomson Multimedia Sa Liquid crystal display device with shielded pixel structure.
US5654731A (en) * 1994-05-13 1997-08-05 Thomson Consumer Electronics, S.A. Shielded pixel structure for liquid crystal displays
CN1036618C (en) * 1994-05-13 1997-12-03 汤姆森消费电子(法国)有限公司 Liquid crystal display device with shielded pixel structure
JPH08338998A (en) * 1995-06-13 1996-12-24 Nec Corp Active matrix type liquid crystal display device and its production
EP0766120A2 (en) * 1995-09-27 1997-04-02 Sharp Kabushiki Kaisha Active matrix substrate and display device incorporating the same
EP0766120A3 (en) * 1995-09-27 1998-07-08 Sharp Kabushiki Kaisha Active matrix substrate and display device incorporating the same
US6982768B2 (en) 1996-02-20 2006-01-03 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device

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