JPS61140156A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS61140156A JPS61140156A JP59260770A JP26077084A JPS61140156A JP S61140156 A JPS61140156 A JP S61140156A JP 59260770 A JP59260770 A JP 59260770A JP 26077084 A JP26077084 A JP 26077084A JP S61140156 A JPS61140156 A JP S61140156A
- Authority
- JP
- Japan
- Prior art keywords
- gel
- resin
- lead frame
- dam
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 239000011347 resin Substances 0.000 claims description 28
- 229920005989 resin Polymers 0.000 claims description 28
- 238000007789 sealing Methods 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 239000003822 epoxy resin Substances 0.000 claims description 5
- 229920000647 polyepoxide Polymers 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 abstract description 13
- 238000000034 method Methods 0.000 abstract description 8
- 238000000465 moulding Methods 0.000 abstract description 3
- 239000000499 gel Substances 0.000 description 43
- 229920001296 polysiloxane Polymers 0.000 description 12
- 238000001723 curing Methods 0.000 description 7
- 239000003795 chemical substances by application Substances 0.000 description 4
- 238000004132 cross linking Methods 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 230000035515 penetration Effects 0.000 description 3
- 239000000725 suspension Substances 0.000 description 3
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229920002379 silicone rubber Polymers 0.000 description 2
- 239000004945 silicone rubber Substances 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- 241000282326 Felis catus Species 0.000 description 1
- 238000003848 UV Light-Curing Methods 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 125000000217 alkyl group Chemical group 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000002075 main ingredient Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000003921 oil Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 229920002545 silicone oil Polymers 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Dispersion Chemistry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は、半導体装置に関し、特に、各リード間に間隙
のあるリードフレームを使用するレジン封止型半導体装
置の封止技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and particularly to a sealing technique for a resin-sealed semiconductor device using a lead frame with gaps between each lead.
レジン封止型半導体パッケージにおいて使用されるリー
ドフレームの一般的な構造としては第４図に示すような
ものが周知である。As a general structure of a lead frame used in a resin-sealed semiconductor package, the one shown in FIG. 4 is well known.
すなわち、リードフレームは、一般に、第４図に示すよ
うに、その略中央に、半導体素子（チップ）を搭載（マ
ウント）するタブと称される部分１４と、そのタブ１４
から延在して、このタブ１４を支持しているタブ吊りリ
ードと称される部分１５と、タブ１４の周囲に、半導体
素子と、コネクタワイヤ（リード線）により、ワイヤボ
ンディングして、該素子内の内部配線を外部に取り出し
するり−ド１６と、これらリード１６を固定したり、ト
ランスファーモールドの際のレジンの流れを止めるタブ
バーと称される部分１７と、枠１８とから成っている。That is, as shown in FIG. 4, the lead frame generally has a portion 14 called a tab on which a semiconductor element (chip) is mounted, and the tab 14 approximately in the center thereof.
A part 15 called a tab suspension lead extending from the tab 14 and supporting the tab 14 is wire-bonded to the semiconductor element and a connector wire (lead wire) around the tab 14. It consists of a lead 16 for taking out internal wiring to the outside, a portion 17 called a tab bar for fixing these leads 16 and stopping the flow of resin during transfer molding, and a frame 18.
このリードフレームを使用するレジン封止型半導体パッ
ケージの一般的な製法例は次の通りである。A typical manufacturing method for a resin-sealed semiconductor package using this lead frame is as follows.
すなわち、上記リードフレームのタブに、周知の合金共
晶法などの技術により、チップを固着し、コネクタワイ
ヤにより、該チップの電極とリードの先端部とをワイヤ
ボンディング後、これをモールド金型に入れて、トラン
スファーモールドを行ない、タブバーの内側まで樹脂を
モールドする主要工程を経てレジン封止型半導体パッケ
ージを得る。That is, a chip is fixed to the tab of the lead frame using a well-known technique such as the alloy eutectic method, and after wire bonding the electrode of the chip and the tip of the lead using a connector wire, this is placed in a mold. A resin-sealed semiconductor package is obtained through the main process of transferring resin and molding the resin to the inside of the tab bar.
本発明者らは、このレジン封止型半導体装置において、
半導体素子のα線によるソフトエラーな防止するために
、該素子上にシリコン（Ｓｉ）ゲルを表面塗布すること
を考えた。ところが、前記のごと＜Ｓｉゲルを半導体素
子表面にのみ塗布した場合はレジンの硬化後の製品の信
頼性試験に於て耐温度サイクル性が低下し、コネクタワ
イヤーに破断を生じることがあった。このＳｉゲルをレ
ジンとコネクタワイヤとの間に介在させればかかるワイ
ヤの断線を生じないことに着目して、半導体素子のみな
らずコネクタワイヤ全体をもかかるＳｉゲルにより被覆
することを検討した。The present inventors have discovered that in this resin-sealed semiconductor device,
In order to prevent soft errors caused by alpha rays in semiconductor devices, we considered applying silicon (Si) gel to the surface of the devices. However, as described above, when the Si gel is applied only to the surface of the semiconductor element, the temperature cycle resistance of the product decreases in the reliability test after the resin is cured, and the connector wire may break. Noting that if this Si gel is interposed between the resin and the connector wire, the wire will not be disconnected, we have considered covering not only the semiconductor element but also the entire connector wire with this Si gel.
しかるに、このＳｉゲルは液状のもので、リードフレー
ムのタブにチップを搭載し、ワイヤボンディング後に、
コネクタワイヤをも含めて、このＳｉゲルをボッティン
グしようとしても、リードフレームの各リード間には間
隙があり、Ｓｉゲルがその隙間より下方向に流出してし
まうし、また、多めにＳｉゲルをポツティングして、チ
ップのみならず、コネクタワイヤ全体をも被覆しようと
してもチップやワイヤなどからＳｉゲルが流れ落ちてし
まうなどそれは不可能であることを知った。However, this Si gel is liquid, and when the chip is mounted on the tab of the lead frame and wire bonded,
Even if you try to bott this Si gel, including the connector wires, there are gaps between the leads of the lead frame, and the Si gel will flow downward through the gaps. I discovered that even if I tried to cover not only the chip but also the entire connector wire by potting it, the Si gel would run off from the chip and wire, making it impossible.
なお、リードフレームの構造やリードフレームを使用す
るレジン封止型半導体装置については、工業調査会１９
８０年１月１５日発行日本マイクロエレクトロニクス協
会編１’−ＩＣ化実装技術」Ｐ１３７〜１４０に詳述さ
れている。Regarding the structure of lead frames and resin-encapsulated semiconductor devices that use lead frames, please refer to the Industrial Research Council 19.
It is described in detail in "1'-IC Mounting Technology" edited by Japan Microelectronics Association, published January 15, 1980, pages 137-140.
本発明の目的は、各リード間に隙間を有するようなリー
ドフレームを使用して成るレジン、封止型半導体装置に
おいて該フレーム上に搭載したチップのみならず、コネ
クタワイヤやこれらのワイヤボンディング部などをＳｉ
ゲルにより被覆し、耐湿性の向上やワイヤの断線やα線
によるソフトエラーなどの生じない、高信頼性のレジン
封止型半導体装置を得ることにある。The object of the present invention is to provide a resin-sealed semiconductor device that uses a lead frame with gaps between each lead, in which not only chips mounted on the frame but also connector wires and wire bonding parts thereof, etc. Si
The object of the present invention is to obtain a highly reliable resin-sealed semiconductor device that is coated with gel and has improved moisture resistance and is free from wire breakage and soft errors caused by alpha rays.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりであ・る。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、例えば、チップ組み込み前のリードフレーム
を型に入れて、８ｉゲルにより被覆しようとする部分、
すなわち、少なくともチップとワイヤとワイヤボンディ
ング部を取り囲むようにして、エポキシ樹脂などのレジ
ンでＳｉゲル流れ止め用の適宜の高さのダムを構築し、
また、その際に、同時に、当該レジンにより、各リード
の隙間を埋めるようにする。これによって、リードフレ
ームを使用しても、Ｓｉゲルボッティングの際の流れが
当該ダムによりせき止められ、また、リードフレーム下
方への流れもせき止められ、チップやコネクタワイヤな
ど所望の部分をＳｉゲルにより被覆することができる。That is, for example, the part of the lead frame that is to be covered with 8i gel after the lead frame is placed in a mold before the chip is assembled;
That is, a dam of an appropriate height for preventing the flow of Si gel is constructed using resin such as epoxy resin to surround at least the chip, the wire, and the wire bonding part, and
Moreover, at the same time, the gaps between the respective leads are filled with the resin. As a result, even if a lead frame is used, the flow during Si gel botting is blocked by the dam, and the flow downward of the lead frame is also blocked, and desired parts such as chips and connector wires are covered with Si gel. Can be coated.
次に、本発明を、実施例を示ｊ図面により説明する。 Next, the present invention will be explained with reference to drawings showing examples.
第１図は９本発明の実施例を示す半導体装置の断面図で
、第１図にて、１は半導体素子、２はコネクタワイヤ（
リード線）、３はリードフレーム、４はこのリードフレ
ーム３のタブ、５はリード、６はシリコン系ゲル、７は
前記のゲルの流れ止め用のダム、８は当該ゲルの各リー
ド５隙間からの流出を防止する、すなわち、リード隙間
を埋めるレジンであり、このレジン８はダム７と同一素
材よす成り、また、９はモールドレジンにより形成され
た封止体を示す。FIG. 1 is a sectional view of a semiconductor device showing nine embodiments of the present invention. In FIG. 1, 1 is a semiconductor element, 2 is a connector wire (
3 is a lead frame, 4 is a tab of this lead frame 3, 5 is a lead, 6 is a silicone gel, 7 is a dam for stopping the flow of the gel, 8 is from each lead 5 gap of the gel The resin 8 is made of the same material as the dam 7, and 9 indicates a sealing body formed of molded resin.
ここに使用された半導体素子組み込み前のリードフレー
ムの要部平面図を第２図に示す。第２図に示すように、
このリードフレーム３には、半導体素子を搭載するタブ
４の外側であって、リード（インナーリード）５および
タブ吊りリード１０の先端部上に四角形状の適宜幅の、
ゲル流出止め用のダム７が載置（固着）されている。FIG. 2 shows a plan view of the main parts of the lead frame used here before the semiconductor element is assembled therein. As shown in Figure 2,
This lead frame 3 has a rectangular shape with an appropriate width on the outside of the tab 4 on which the semiconductor element is mounted and on the tips of the leads (inner leads) 5 and the tab suspension leads 10.
A dam 7 for preventing gel outflow is mounted (fixed).
かかるリードフレーム３は、例えば次のようにして作る
ことができる。Such a lead frame 3 can be made, for example, as follows.
すなわち、リードフレーム３を、第３図に示すような、
上盤１１と下型１２とからなる成形型に入れ、当該型の
ゲート（図示せず）より、ゲル流れ止め用のダム７を構
成する素材を、インジェクションすると、上型１１の溝
部１３に当該素材が流れ止み、上記成形型よりリードフ
レーム３を取り出しすると、第２図に示すような、適当
な高さ、幅を有するリング状のダム７が形成され、同時
に、上記インジェクションの際に、当該素材により各リ
ード５の隙間を埋めることができる。That is, the lead frame 3 is as shown in FIG.
When the material constituting the dam 7 for preventing gel flow is injected into a mold consisting of an upper mold 11 and a lower mold 12 through a gate (not shown) of the mold, the material forming the dam 7 for preventing gel flow is injected into the groove 13 of the upper mold 11. When the material stops flowing and the lead frame 3 is taken out from the mold, a ring-shaped dam 7 with appropriate height and width is formed as shown in FIG. The gap between each lead 5 can be filled with the material.
本発明のかかるリードフレームを使用して、第１図に示
すような半導体装置は、例えば次のようにして製造する
ことができる。Using the lead frame of the present invention, a semiconductor device as shown in FIG. 1 can be manufactured, for example, as follows.
第２図に示すようなリードフレーム３のタブ４上に、半
導体素子１を固着し、該素子１の電極とインナーリード
５の先端部とをコネクタワイヤ２により第１図に示すよ
うに、電気的物理的に接続し、ゲル流れ止め用のダム７
で囲まれたエリアに、シリコン系ゲル６形成材料をポツ
ティングし、少なくとも半導体素子１、コネクタワイヤ
２並びに、このワイヤ２と半導体素子１とのボンディン
グ部およびワイヤ２とインナ−リード５先端部とのボン
ディング部とを当該ゲル形成材料の硬化により形成され
たシリコン系ゲル６により被覆後、モールド金型に入れ
て、モールドレジンを周知のトランスファーモールド法
によりトランスファーモールドして、封止体９を形成後
、公知の所法に従い、ダムバーの切断、リードメッキな
どを行い半導体装置を得る。The semiconductor element 1 is fixed onto the tab 4 of the lead frame 3 as shown in FIG. Dam 7 for physically connecting and stopping gel flow
A silicon gel 6 forming material is potted in the area surrounded by at least the semiconductor element 1, the connector wire 2, the bonding portion between the wire 2 and the semiconductor element 1, and the bonding portion between the wire 2 and the tip of the inner lead 5. After covering the bonding portion with a silicone gel 6 formed by curing the gel-forming material, it is placed in a mold, and the mold resin is transfer-molded by a well-known transfer molding method to form a sealing body 9. Then, according to known methods, cutting of the dam bar, lead plating, etc. are performed to obtain a semiconductor device.
本発明半導体装置を構成する半導体素子（チップ）１は
、例えばシリコン単結晶基板から成り、周知の技術によ
って、このチップ内には多数の回路素子が形成され、１
つの回路機能が与えられている。回路素子の具体例は、
例えばＭＯＳ）ランジスタから成り、これらの回路素子
によって、例えばメモリや論理回路の回路機能が形成さ
れている。A semiconductor element (chip) 1 constituting the semiconductor device of the present invention is made of, for example, a silicon single crystal substrate, and a large number of circuit elements are formed within this chip by a well-known technique.
Two circuit functions are given. Specific examples of circuit elements are:
For example, it consists of transistors (MOS), and these circuit elements form circuit functions such as a memory or a logic circuit.
コネクタワイヤ２は、例えばｈｔ細線やＡｕ細線による
構成されている。The connector wire 2 is made of, for example, a thin HT wire or a thin Au wire.
リードフレーム３は、例えば４２アロイ （４２％Ｎｉ
５８％Ｆｅ）などにより構成される。The lead frame 3 is made of, for example, 42 alloy (42%Ni
58% Fe).
次に、本発明に使用されるシリコーン系ゲル６について
説明する。Next, the silicone gel 6 used in the present invention will be explained.
このゲル６には、前記のごとく、例えばＩＣ（集積回路
）メモリーのソフトエラ一対策用として用いられていた
ものを使用できる。As described above, the gel 6 may be one that has been used as a countermeasure against soft errors in IC (integrated circuit) memories, for example.
このゲルはリキッド状であり、１液タイプ、２液タイプ
があり、例えば主剤と硬化剤とから成る２液タイプの場
合、これらを混合し、反応硬化（架橋）させると、硬化
物を得る。This gel is in the form of a liquid and is available in one-part type and two-part type. For example, in the case of a two-part type consisting of a main ingredient and a hardening agent, a cured product is obtained by mixing these and performing reaction curing (crosslinking).
硬化システムとしては、次の反応式で示すように、縮台
型、付加型、紫外線硬化型がある。As shown in the following reaction formula, curing systems include a reduction type, an addition type, and an ultraviolet curing type.
縮合型 ｃａｔ：５ｎ−Ｉｉ系触媒 Ｒ：例えばアルキル基 （以下同じ） 付加型 紫外線硬化型 硬化物を得るに、加熱（ベーク）するとゴム化が進む。condensed type cat: 5n-Ii catalyst R: For example, an alkyl group (same as below) Additive type UV curing type To obtain a cured product, heating (baking) progresses the rubberization.
本発明に使用されるシリコーン系ゲル６はシリコーンゴ
ムと異なり架橋密度の低いものである。The silicone gel 6 used in the present invention has a low crosslinking density, unlike silicone rubber.
一般に、封止材料として使用されているクリコーン系樹
脂とも異なる。It is also different from the crecone resin that is generally used as a sealing material.
シリコーン系ゲルよりも架橋密度の低いものとしてシリ
コーン系オイルがある。Silicone oil has a lower crosslinking density than silicone gel.
架橋密度は一般に針入度計を用いて測定され、それに使
用される針についてはＡＳＴＭＤ１３２１に規格がある
。Crosslink density is generally measured using a penetrometer, and the needles used therefor are standardized in ASTM D1321.
針入度からみて、一般にゲルは４０〜２００ｍの範囲、
オイルは２００＋ｍｓ以上であり、ゲルの硬化反応の促
進によりゴム化が起こり、シリコーンゴムと称されてい
るものは一般に針入度４０瓢以下である。In terms of penetration, gels generally have a range of 40 to 200 m.
The oil is 200+ ms or more, and rubberization occurs by promoting the curing reaction of the gel, and what is called silicone rubber generally has a penetration rate of 40+ ms or less.
したがって、本発明に使用されるシリコーン系ゲルは柔
軟であり、シリコーン系ゲルの硬化によっても、ワイヤ
の破断などが起こらない。Therefore, the silicone gel used in the present invention is flexible, and even when the silicone gel is hardened, the wire does not break.
このシリコーン系ゲルの具体例としては、例えば信越化
学工業社製ＫＪＲ９０１０、Ｘ−３５−１００、東しシ
リコーン社製ＪＣＲ６１１０などがある。Specific examples of this silicone gel include KJR9010 and X-35-100 manufactured by Shin-Etsu Chemical Co., Ltd., and JCR6110 manufactured by Toshi Silicone Co., Ltd., for example.
↓記Ｘ−３５−１００ＣＡ （主剤）、Ｂ（硬化剤）２
液タイプ、針入度１００）の硬化反応機構は白金付加型
で、２液低温高温用ゲルで一７５〜２５０℃の温度範囲
で使用できる。↓X-35-100CA (base agent), B (curing agent) 2
The curing reaction mechanism of the liquid type (penetration 100) is a platinum addition type, and it is a two-part low-temperature/high-temperature gel that can be used in a temperature range of -75 to 250°C.
ダム７は封止体９を構成する封止レジンと同一素材より
成っていてもよいし、また、他のレジンを使用してもよ
い。The dam 7 may be made of the same material as the sealing resin constituting the sealing body 9, or another resin may be used.
封止レジン９に例えばエポキシ樹脂を使用するときには
、これと同一素材のエポキシ樹脂を使用してもよいし、
これ以外の例えばポリイミド系レジンを使用してもよい
。For example, when epoxy resin is used for the sealing resin 9, an epoxy resin made of the same material as this may be used,
Other resins, such as polyimide resins, may also be used.
リードフレーム３の各リード５間の隙間を埋めるレジン
８にはダム７と同一素材が使用される。The same material as the dam 7 is used for the resin 8 that fills the gaps between the leads 5 of the lead frame 3.
（１１Ｓｉゲル流れ止め用のダムを設け、かつ、リード
フレームの各リード間の隙間を埋めるようにしたので、
Ｓｉゲルをボッティングして、少なくとも、半導体素子
やコネクタワイヤや当該ワイヤボンディング部を被覆す
ることができ、このＳｉゲルは、湿分な水分子として透
過させるだけで、樹脂封止型半導体装置において問題と
なる水膜の形成を行わず、したがって耐湿性に富む。(Since we installed a dam to stop the flow of 11Si gel and filled the gaps between each lead of the lead frame,
Botting Si gel can cover at least semiconductor elements, connector wires, and wire bonding parts, and this Si gel can be used in resin-sealed semiconductor devices by simply permeating it as moisture molecules. It does not form a problematic water film and is therefore highly moisture resistant.
（２） このＳｉゲルは柔軟性に富むので、Ｓｉゲル
が加熱硬化しても、コネクタワイヤにひずみがかからず
、ワイヤの断線などを回避することができる。(2) Since this Si gel is highly flexible, even if the Si gel is heated and hardened, no strain is applied to the connector wire, and wire breakage can be avoided.
（３）耐湿性に富み、ワイヤの断線も生ぜず、しかもα
線によるソフトエラー効果も果たすことができるので、
信頼性の高いレジン封止型半導体装置が得られた。(3) Highly moisture resistant, does not cause wire breakage, and α
Since the soft error effect due to lines can also be achieved,
A highly reliable resin-sealed semiconductor device was obtained.
（４）Ｓｉゲル流れ止め用のダムや各リード間の隙間を
埋めるのに、レジンを使用するようにしたので、封止レ
ジンとの密着性などに問題なくレジン封止型半導体装置
を得ることができた。(4) Since resin is used to fill the dam for preventing the flow of Si gel and the gaps between each lead, it is possible to obtain a resin-sealed semiconductor device without problems with adhesion with the sealing resin. was completed.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.
例えば、前記実施例では、リードフレームのＳｉ系ゲル
流れ止め用のダム内のみレジンで隙間を埋める例を示し
たが、リードフレーム全域にわたり各リード間の隙間を
レジンで埋めてもよい。For example, in the embodiment described above, an example was shown in which the gap was filled with resin only in the dam for preventing the flow of Si-based gel in the lead frame, but the gap between each lead may be filled with resin over the entire area of the lead frame.
本発明はレジ／封止型半導体装置全般に適用でき、前記
実施例のデエアルインラインタイプのプラスチックパッ
ケージの他、例えばフラットパックタイプのプラスチッ
クパッケージなどにも適用できる。The present invention can be applied to all cash register/sealed type semiconductor devices, and can also be applied to, for example, flat pack type plastic packages in addition to the air in-line type plastic packages of the above embodiments.
また、各種電子部品のパッケージング技術にも適用でき
る。It can also be applied to packaging technology for various electronic components.
第１図は本発明の実施例を示す断面図、第２図は本発明
に使用されるリードフレームの平面図、
第３図は本発明に係るリードフレーム成形の一態様の説
明図、
第４図は従来例を示すリードフレームの平面図である。
１・・・半導体素子、２・・・コネクタワイヤ、３・・
・リ−１”７レーム、４・・・タブ、５・・・リード、
６・・・シリコーン系ゲル、７・・・シリコーン系ゲル
の流れ止め用ダム、８・・・シリコーン系ゲルの流れ止
め用レジン、９・・・レジン封止体、１０・・・タブ吊
りリード、１１・・・上型、１２・・・下型、１３・・
・溝部、１４・・・タブ、１５・・・タブ吊りリード、
１６・・・リード、１７・・・タブバー、１８・・・枠
。
ｌ〆′−＼
代理人 弁理士 高 橋 明 夫ｒ′。
第 １ 図FIG. 1 is a sectional view showing an embodiment of the present invention, FIG. 2 is a plan view of a lead frame used in the present invention, FIG. 3 is an explanatory diagram of one aspect of lead frame molding according to the present invention, and FIG. The figure is a plan view of a lead frame showing a conventional example. 1... Semiconductor element, 2... Connector wire, 3...
・Lee-1” 7 reams, 4...Tab, 5...Lead,
6...Silicone gel, 7...Dam for preventing the flow of silicone gel, 8...Resin for preventing the flow of silicone gel, 9...Resin sealing body, 10...Tab suspension lead , 11...upper mold, 12...lower mold, 13...
・Groove, 14...Tab, 15...Tab hanging lead,
16...Lead, 17...Tab bar, 18...Frame. l〆′−＼ Agent Patent Attorney Akio Takahashi r′. Figure 1
Claims (1)
前記リードフレームとをコネクタワイヤにより電気的物
理的に接続し、レジンで封止するタイプのレジン封止型
半導体装置において、前記リードフレーム上にシリコン
系ゲル流れ止め用のダムを前記レジンあるいは他のレジ
ンにより形成するとともに、当該レジンによりリードフ
レームの各リード間の隙間を埋め、少なくとも半導体素
子およびコネクタワイヤをシリコン系ゲルにより被覆し
、かつ、前記レジン封止を行って成ることを特徴とする
半導体装置。 ２、ダムが、エポキシ樹脂より形成され、レジン封止が
、該エポキシ樹脂より行われて成る、特許請求の範囲第
１項記載の装置。[Claims] 1. A resin-sealed semiconductor device in which a semiconductor element is mounted on a lead frame, the element and the lead frame are electrically and physically connected by a connector wire, and sealed with resin. In this step, a dam for preventing the flow of silicon-based gel is formed on the lead frame using the resin or another resin, and the gap between each lead of the lead frame is filled with the resin, and at least the semiconductor element and the connector wire are coated with silicon-based gel. A semiconductor device characterized by being coated with gel and sealed with the resin. 2. The device according to claim 1, wherein the dam is made of epoxy resin, and the resin sealing is made of the epoxy resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59260770A JPS61140156A (en) | 1984-12-12 | 1984-12-12 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59260770A JPS61140156A (en) | 1984-12-12 | 1984-12-12 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61140156A true JPS61140156A (en) | 1986-06-27 |
Family
ID=17352483
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59260770A Pending JPS61140156A (en) | 1984-12-12 | 1984-12-12 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61140156A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6049120A (en) * | 1997-01-14 | 2000-04-11 | Mitsubishi Denki Kabushiki Kaisha | Thermal-stress-resistant semiconductor sensor |
-
1984
- 1984-12-12 JP JP59260770A patent/JPS61140156A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6049120A (en) * | 1997-01-14 | 2000-04-11 | Mitsubishi Denki Kabushiki Kaisha | Thermal-stress-resistant semiconductor sensor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR0167297B1 (en) | L.O.C package and its manufacturing method | |
| US5733800A (en) | Underfill coating for LOC package | |
| US6885093B2 (en) | Stacked die semiconductor device | |
| US6383292B1 (en) | Semiconductor device encapsulators | |
| US4766095A (en) | Method of manufacturing eprom device | |
| KR20070015014A (en) | How to make a stacked die package | |
| US6236107B1 (en) | Encapsulate resin LOC package and method of fabrication | |
| US6297544B1 (en) | Semiconductor device and method for manufacturing the same | |
| JPH08264569A (en) | Method for manufacturing resin-sealed semiconductor device | |
| JPS61140156A (en) | semiconductor equipment | |
| US20070080435A1 (en) | Semiconductor packaging process and carrier for semiconductor package | |
| JPS61194747A (en) | Resin seal type semiconductor integrated circuit device | |
| US6384333B1 (en) | Underfill coating for LOC package | |
| JPS63107156A (en) | Resin-encapsulated semiconductor device | |
| JPS62210651A (en) | Resin-encapsulated semiconductor device | |
| JPS62249458A (en) | semiconductor equipment | |
| JP2001185567A (en) | Semiconductor device and method of manufacturing the same | |
| JPS63107050A (en) | Resin-encapsulated semiconductor device | |
| JPH0897334A (en) | Resin-sealed semiconductor device | |
| JPS63107151A (en) | Pin-grid-array plastic package | |
| KR0172020B1 (en) | Resin-sealed semiconductor device | |
| JP2543525B2 (en) | Resin-sealed semiconductor device | |
| JPS61101056A (en) | semiconductor equipment | |
| JPH02119147A (en) | Manufacturing method for resin-encapsulated semiconductor devices | |
| JPS61168943A (en) | Semiconductor device |