JPS62249458A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS62249458A JPS62249458A JP61092175A JP9217586A JPS62249458A JP S62249458 A JPS62249458 A JP S62249458A JP 61092175 A JP61092175 A JP 61092175A JP 9217586 A JP9217586 A JP 9217586A JP S62249458 A JPS62249458 A JP S62249458A
- Authority
- JP
- Japan
- Prior art keywords
- cap
- gel
- base
- silicone
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 35
- 125000006850 spacer group Chemical group 0.000 claims description 13
- 239000003566 sealing material Substances 0.000 claims description 4
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
- 239000000499 gel Substances 0.000 description 36
- 229920001296 polysiloxane Polymers 0.000 description 23
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 238000001723 curing Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 229920002379 silicone rubber Polymers 0.000 description 6
- 239000004945 silicone rubber Substances 0.000 description 6
- 238000004132 cross linking Methods 0.000 description 5
- 238000007789 sealing Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 239000003795 chemical substances by application Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229920001971 elastomer Polymers 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 230000035515 penetration Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 2
- 239000003921 oil Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000003848 UV Light-Curing Methods 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 125000000217 alkyl group Chemical group 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000013464 silicone adhesive Substances 0.000 description 1
- 239000004447 silicone coating Substances 0.000 description 1
- 229920002545 silicone oil Polymers 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Dispersion Chemistry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に、シリコーン系ゲルに
より半導体素子を封止して成る半導体装置のスペーサ一
部およびキャップ部の改良並びに耐湿性の向上技術に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices, and in particular to improvements in a spacer portion and a cap portion of a semiconductor device in which a semiconductor element is sealed with a silicone gel, and to improve moisture resistance. Regarding improvement technology.
本発明者等は、先に、半導体素子をシリコーン系ゲルに
より封止して成る半導体装置を提案した。The present inventors previously proposed a semiconductor device in which a semiconductor element is sealed with a silicone gel.
この装置の一例は、その裏面から外部接続ピンが垂直方
向に引出されたペース上に半導体素子を固着し、ワイヤ
ボンディング後、当該ベース上に投げられたダムにより
区画されたエリア内に、シリコーン系ゲル材をボッティ
ングし、ベークにして、当該ゲルを形成し、このゲル（
より半導体素子を封止して成る。In one example of this device, a semiconductor element is fixed on a paste with external connection pins pulled out vertically from the back side of the base, and after wire bonding, a silicone-based Botting the gel material and baking it to form the gel (
It is made by sealing a semiconductor element.
このゲルは湿分な水分子として透過するだけで、水膜を
形成しないので、耐湿性ある半導体装置となすことがで
きるが、柔軟であるため、半導体素子の機械的損傷をさ
ける等から、ダム上にキャップを取付けして成る。This gel only passes through as moisture molecules and does not form a water film, so it can be used as a moisture-resistant semiconductor device. It consists of a cap attached to the top.
一方、かかる従来のアキシャルピングリットアレイタイ
プの半導体装置では、実装時にプリント基板から浮かせ
て、洗浄（性）を良くするなどの目的から、その外部接
続ビンにスペーサーと称される例えばリング状の補助具
を取付けることが行われている。On the other hand, in such conventional axial pin grid array type semiconductor devices, for example, a ring-shaped support called a spacer is attached to the external connection bin for the purpose of lifting it off the printed circuit board during mounting and improving cleaning (ability). The equipment is being installed.
このように、従来例ではスペーサーの取付けなどの煩雑
な工程を要するなどの難点があった。なお、シリコーン
系ゲルにより半導体素子を封止する技術については、先
に本出願人より提出された％願昭５９−２２２１８７、
％願昭５９−１９９６１９などがある。As described above, the conventional example has drawbacks such as requiring complicated steps such as attaching a spacer. Regarding the technology of sealing semiconductor elements with silicone gel, see % Application No. 59-222187 previously submitted by the present applicant.
% Gansho 59-199619, etc.
本発明は半導体装置をプリント基板などの実装基板に実
装するときに、当該装置が当該基板から一定の高さを保
持できるスペーサーを殊更に取付ける必要がない技術を
提供することを目的とする。An object of the present invention is to provide a technique in which, when a semiconductor device is mounted on a mounting board such as a printed circuit board, there is no need to attach a spacer that allows the device to maintain a constant height from the board.
本発明は、また、シリコーン系ゲルで封止して成る半導
体装置において、従来の装置に比してより一層耐湿性を
向上し得る技術を提供することを目的とする。Another object of the present invention is to provide a technique that can further improve moisture resistance in a semiconductor device sealed with silicone gel compared to conventional devices.
本発明の前記ならびにそのほかの目的と新規な特徴は１
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention are as follows:
It will become clear from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、本発明では、前記のごとき半導体装置におけ
るキャップにおいて、従来のダムを一体化したキャップ
とするとともに、キャップ裏面に該キャップを支持する
２本の支持体を立設して該支持体によりペース上にキャ
ップを支持し、これら支持体間に封止材を充填し、さら
に、キャップの端部なペース下面より突出させた。これ
により、キャップ端部の突出によりスペーサー効果をも
たせることができまた、支持体間の封止材により、より
一層封止の信頼性を向上させることができ、さらに、当
該支持体によりダムとしての役割を果させることもでき
た。That is, in the present invention, in the cap for the semiconductor device as described above, the conventional dam is integrated into the cap, and two supports for supporting the cap are erected on the back surface of the cap, and the pace is increased by the supports. A cap was supported on top, a sealing material was filled between these supports, and the ends of the cap were made to protrude from the lower surface of the paste. As a result, the protrusion of the end of the cap can provide a spacer effect, and the sealing material between the supports can further improve sealing reliability.Furthermore, the support can be used as a dam. I was able to fulfill my role.
次に、本発明を、図面に示す実施例に基づき説明する。 Next, the present invention will be explained based on embodiments shown in the drawings.
第１図は本発明による半導体装置の実施例を示す要部断
面図、第２図は同全体断面図、第３図は当該装置の平面
図、第４図は同底面図である。FIG. 1 is a cross-sectional view of a main part of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of the entire semiconductor device, FIG. 3 is a plan view of the device, and FIG. 4 is a bottom view of the same.
これら図にて、１はペース、２は外部接続ビン、３は半
導体素子、４はコネクタワイヤ、５はキャップ、６はシ
リコーン系ゲルである。In these figures, 1 is a paste, 2 is an external connection bottle, 3 is a semiconductor element, 4 is a connector wire, 5 is a cap, and 6 is a silicone gel.
ペース１は、例えばガラスエポキシ基板に！り構成され
、該ペース１の裏面からは多数の外部接続ビン２が垂設
されている。ペースｌの表面からは、該接続ビンのヘッ
ド部７が突出している。ペース１には図示されていない
が、導体パターンを有する。For example, Pace 1 can be used on glass epoxy substrates! A large number of external connection bins 2 are vertically provided from the back surface of the pace 1. A head portion 7 of the connecting bottle protrudes from the surface of the paste l. Although not shown in the figure, the paste 1 has a conductor pattern.
ペース１上に半導体素子３をシリコーン系接着剤などに
より固着する。A semiconductor element 3 is fixed onto the paste 1 using a silicone adhesive or the like.
第１図における、半導体素子３は、例えばシリコン単結
晶基板から成り、周知の技術によって、この半導体素子
（チップ）内には多数の回路素子が形成され、１つの回
路機能を与えている。回路素子は、例えばＣＭＯ８から
成り、これらの回路素子によって１例えば論理回路およ
びメモリの回路機能が形成されている。The semiconductor element 3 in FIG. 1 is made of, for example, a silicon single crystal substrate, and a large number of circuit elements are formed within this semiconductor element (chip) by a well-known technique to provide one circuit function. The circuit elements include, for example, a CMO 8, and these circuit elements form circuit functions such as a logic circuit and a memory.
半導体素子３のボンディング電極（図示せず）と前記ペ
ース１表面の導体パターンを、例えばＡｕ線よりなるコ
ネクタワイヤ４により、周知の超音波ワイヤボンディン
グ法などによりワイヤボンディングする。The bonding electrode (not shown) of the semiconductor element 3 and the conductive pattern on the surface of the paste 1 are wire-bonded using a connector wire 4 made of, for example, an Au wire by a well-known ultrasonic wire bonding method or the like.
かかる結線により、当該素子３内の内部配線が外部に取
出され、電気的導通がとられる。かかるワイヤボンディ
ング後に、半導体素子３、コネクタワイヤ４、外部接続
ビン２のヘッド部７を被覆するように、シリコーン系ゲ
ル６を形成するゲル材をボッティングする。Through this connection, the internal wiring within the element 3 is taken out to the outside and electrical continuity is established. After such wire bonding, a gel material forming a silicone gel 6 is potted so as to cover the semiconductor element 3, the connector wire 4, and the head portion 7 of the external connection pin 2.
本発明に使用されるシリコーン系ゲル（ゲル材）６とし
ては、従来エレクトロニクスあるいはオプティカルファ
イバー用シリコーンコーディング剤として市販されてい
たものを使用でき、例えばシリコーンゲルはＩＣメモリ
ーのソフトエラ一対策用として用いられていた。本発明
はこれを封止材料として使用せんとするものである。As the silicone gel (gel material) 6 used in the present invention, those conventionally commercially available as silicone coating agents for electronics or optical fibers can be used. For example, silicone gel is used to prevent soft errors in IC memory. was. The present invention aims to use this as a sealing material.
ゲルは、その加熱硬化前はリキッド状態であり、１液タ
イプ、２液タイプがあり、例えば主剤と硬化剤とから２
液タイプのゲル材の場合、これらを混合すると反応硬化
（架橋反応）し、硬化物（ゲル）を得る。Gel is in a liquid state before it is heated and cured, and there are two types, one-part type and two-part type.
In the case of a liquid type gel material, when these are mixed, reaction and curing (crosslinking reaction) occur to obtain a cured product (gel).
硬化システムとしては次の反応式で示す様に、縮金型、
付加型、紫外勝硬化型がある。As shown in the following reaction formula, the curing system is a shrinking mold,
There are addition type and ultraviolet curing type.
縮合型 一８ｉ−＋ＲＯＨ Ｃａｔ：５ｎ−Ｔｉ系触媒 Ｒ：例えばアルキル基（以下同じ） 付加型 紫外線硬化型 硬化物を得るに、加熱（ベータ）するとゴム化が進む。condensed type 18i-+ROH Cat: 5n-Ti catalyst R: For example, an alkyl group (the same applies below) Additive type UV curing type To obtain a cured product, heating (beta) progresses the rubberization.
本発明に使用されるシリコーン系ゲル６はシリコーンゴ
ムやシリコーンオイルと異なり架橋密度の低いものであ
る。The silicone gel 6 used in the present invention has a low crosslinking density, unlike silicone rubber or silicone oil.
例えば架橋密度の大小からみるとゴムが架橋密度が一番
大で、その下がゲル、さらに、その下がオイルというこ
とになる。For example, looking at the crosslinking density, rubber has the highest crosslinking density, below that is gel, and below that is oil.
架橋密度は一般に針入度計を用いて測定され、針入度計
についてはＪ Ｉ ＳＫ２８０８に規定され、それに使
用される針についてはＡＳＴＭＤ１３２１に規格がある
。The crosslinking density is generally measured using a penetrometer, and the penetrometer is specified in J I SK2808, and the needle used therein is specified in ASTM D1321.
針入・度からみて、一般に、ゲルは４．０〜２０．０寵
の範囲、オイルは２０．０ｍ以上であり、ゲルの硬化反
応の促進によりゴム化が起こり、ゴムと称されているも
のは一般に針入度４．０ ｗｔ以下である。In terms of penetration and degree, gels are generally in the range of 4.0 to 20.0 meters, and oils are 20.0 meters or more, and rubberization occurs due to the acceleration of the curing reaction of gel, which is called rubber. generally has a penetration of 4.0 wt or less.
本発明に使用されるシリコーン系ゲル６には前記の如く
、市販のものが使用され、例えば信越化学工業社製ＫＪ
Ｒ９０１０、Ｘ−３５−１００東レシリコーン社製ＪＣ
Ｒ６１１Ｑなどが使用できる。As mentioned above, commercially available silicone gels are used as the silicone gel 6 used in the present invention, such as KJ manufactured by Shin-Etsu Chemical Co., Ltd.
R9010, X-35-100 JC manufactured by Toray Silicone Co., Ltd.
R611Q etc. can be used.
上記Ｘ−３５−１００［Ａ（主剤）、Ｂ（硬化剤）２液
タイプ、針入度１０ｕ＋］の硬化反応機構は白金付加型
で、２液低温高温用ゲルで一７５〜２５０Ｃの温度範囲
で使用できる。The curing reaction mechanism of the above X-35-100 [A (base ingredient), B (curing agent) 2-part type, penetration 10u+] is a platinum addition type, and it is a 2-part low-temperature high-temperature gel with a temperature range of -75 to 250C. Can be used in
ゲル材の流れ止めに、ベース１上に垂設した二つの支持
体８．９のうち半導体素子３に近い側の支持体８を使用
することができる。Of the two supports 8.9 vertically disposed on the base 1, the support 8 closer to the semiconductor element 3 can be used to prevent the gel material from flowing.
この支持体８の内側をシリコーン系グ／ｌ／６により封
止し、さらに、両支持体８．９の間にシリコーン系ゲル
６を充填すると、封止性が向上する。If the inside of this support 8 is sealed with silicone gel/l/6 and the silicone gel 6 is further filled between both supports 8 and 9, the sealing performance will be improved.
外側の支持体９の外側ベース１上にシリコーンゴム接着
剤１０を塗布しておく。A silicone rubber adhesive 10 is applied on the outer base 1 of the outer support 9.
両支持体８，９間のシリコーン系ゲル６に代えてシリコ
ーンゴム接着剤を充填してもよく、内側の支持体８内部
にシリコーン系ゲル６が塗布され、さらに、このように
、シリコーンゴム接着剤が充填（塗布）されていること
により、耐湿性を向上させることができる。A silicone rubber adhesive may be filled instead of the silicone gel 6 between the supports 8 and 9, and the silicone gel 6 is applied inside the inner support 8, and the silicone rubber adhesive is applied in this way. By filling (coating) with the agent, moisture resistance can be improved.
キャップ５を支持体８．９上に載置する。Place the cap 5 on the support 8.9.
キャップ５は天井部１１から直角方向に延在部１２を有
し、さらに、該延在部１２から延在したスペーサ一部１
３を有する。The cap 5 has an extending portion 12 extending perpendicularly from the ceiling portion 11, and further includes a spacer portion 1 extending from the extending portion 12.
It has 3.
キャップ５は、外側の支持体９の外側ベース上に塗布さ
れたシリコーンゴム接着剤１０により、ベース１に取付
けすることができる。The cap 5 can be attached to the base 1 by means of a silicone rubber adhesive 10 applied onto the outer base of the outer support 9.
スペーサ一部１３は、ベース１の裏面から適宜長さで突
出している。スペーサ一部１３は例えば第３図、第４図
のキャップのコーナ部のみに設けられてもよい。キャッ
プ５や支持体８．９は、例えば合成樹脂により構成され
る。The spacer portion 13 protrudes from the back surface of the base 1 by an appropriate length. The spacer portion 13 may be provided, for example, only at the corner portion of the cap shown in FIGS. 3 and 4. The cap 5 and the support body 8.9 are made of, for example, synthetic resin.
このように、キャップ５自体にスペーサ一部１３を設け
ることにより、殊更にスペーサーを外部接続ピン２に取
付ける工程を省略できる。By providing the spacer portion 13 on the cap 5 itself in this manner, the step of attaching the spacer to the external connection pin 2 can be omitted.
また、半導体素子３’！’コネクタワイヤ４はシリコー
ン系ゲル６により被覆され、このゲＡ／６は耐湿性に富
むので、耐湿性に富んだ半導体装置が得られるが、さら
に、支持体８と支持体９の間にシリコーン系ゲル６を入
れると、キャップ５とベース１間から、水分などの、半
導体素子３に害を与える、有害物質が侵入してきてもこ
の両支持体８゜９間のシリコーン系ゲルの存在６により
、耐湿性が確保され、かかる二重シールにより、耐湿性
を従来に比してより一層向上させることができる。Also, semiconductor element 3'! 'The connector wire 4 is covered with silicone gel 6, and this gel A/6 has high moisture resistance, so a semiconductor device with high moisture resistance can be obtained. When the silicone gel 6 is inserted, even if harmful substances such as moisture that harm the semiconductor element 3 enter from between the cap 5 and the base 1, the presence of the silicone gel 6 between the two supports 8 and 9 prevents harmful substances from entering. , moisture resistance is ensured, and such double sealing makes it possible to further improve moisture resistance compared to the conventional method.
その際、シリコーン系ゲル６により、半導体素子３のみ
ならず、コネクタワイヤ４や外部接続ピン２のヘッド部
７にも当該シリコーン系ゲル６を被覆しているので、よ
り一層耐湿性を向上させることができろ。At this time, not only the semiconductor element 3 but also the connector wire 4 and the head portion 7 of the external connection pin 2 are coated with the silicone gel 6, so that moisture resistance can be further improved. Be able to do it.
シリコーンゴム接着剤１０により、支持体８゜９をベー
ス１上に立設しておくことにより、当該支持体８，９を
シリコーン系ゲル６の液状ゲル材の流れ止め（ダム）に
も使用できる。By erecting the supports 8° 9 on the base 1 using the silicone rubber adhesive 10, the supports 8 and 9 can also be used as a dam for the liquid gel material of the silicone gel 6. .
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で梅々変史可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained based on the examples above, the present invention is not limited to the above examples, and may be modified without departing from the gist of the invention. Needless to say.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野であるピングリッドアレイ
タイプの半導体パッケージに適用した場合について説明
したが、７リコーンゲルを使用する他のタイプの半導体
パッケージにも適用できる。The above explanation has mainly been about the application of the invention made by the present inventor to a pin grid array type semiconductor package, which is the field of application in which the invention was made. can also be applied.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとおりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
すなわち、本発明によれば、スペーサーを殊更に取付け
る必要がなく、また、耐湿性を向上させることができた
。That is, according to the present invention, there is no need to particularly attach a spacer, and moisture resistance can be improved.
第１図は本発明による半導体装置の実施例を示す要部拡
大断面図、
第２図は同全体断１１￥ｉ因、
第３図は本発明による半導体装置の実施例を示す平面図
、
第４図は同底面図である。
１・・・ベース、２・・・外部接続ピン、３・・・半導
体素子、４・・・コネクタワイヤ、５・・・キャップ、
６・・・シリコーン系ゲル、７・・・外部接続ピンのヘ
ッド部、８・・・支持体、９・・・支持体、１ｏ・パシ
リコーンゴム接着剤、１１・・・キャップ天井部、１２
・・・キャップ延在部、１３・・・スペーサ一部。
第 １ 図
第 ２ 図FIG. 1 is an enlarged sectional view of essential parts showing an embodiment of a semiconductor device according to the present invention, FIG. 2 is a cross-sectional view of the same, and FIG. 3 is a plan view showing an embodiment of a semiconductor device according to the present invention. Figure 4 is a bottom view of the same. DESCRIPTION OF SYMBOLS 1... Base, 2... External connection pin, 3... Semiconductor element, 4... Connector wire, 5... Cap,
6... Silicone gel, 7... Head portion of external connection pin, 8... Support body, 9... Support body, 1o. Pasilicone rubber adhesive, 11... Cap ceiling part, 12
... Cap extension, 13... Part of spacer. Figure 1 Figure 2
Claims (1)
ベース上に固着された半導体素子と、該素子を覆うゲル
剤と、上記ベースの側面に係合する端部と上記ベースの
表面に対する高さを規定する技持部とを持ちシール材に
より上記ベースに接着されてなるキャップとを備えた半
導体装置。 ２、上記キャップは、更に、上記ベースの裏面から突出
するスペーサ部を持っていることを特徴とする特許請求
の範囲第１項記載の半導体装置。 ３、キャップが樹脂製である特許請求の範囲第１項又は
第２項記載の半導体装置。[Claims] 1. A base with external connection terminals provided on the back surface, a semiconductor element fixed on the base, a gel covering the element, and an end portion that engages with the side surface of the base. A semiconductor device comprising: a cap that is bonded to the base using a sealing material; and a cap that defines a height relative to the surface of the base. 2. The semiconductor device according to claim 1, wherein the cap further has a spacer portion protruding from the back surface of the base. 3. The semiconductor device according to claim 1 or 2, wherein the cap is made of resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61092175A JPS62249458A (en) | 1986-04-23 | 1986-04-23 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61092175A JPS62249458A (en) | 1986-04-23 | 1986-04-23 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62249458A true JPS62249458A (en) | 1987-10-30 |
Family
ID=14047096
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61092175A Pending JPS62249458A (en) | 1986-04-23 | 1986-04-23 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62249458A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62177041U (en) * | 1987-03-25 | 1987-11-10 | ||
| US6140698A (en) * | 1998-12-21 | 2000-10-31 | Nortel Networks Corporation | Package for microwave and mm-wave integrated circuits |
| US7235873B2 (en) * | 2001-08-01 | 2007-06-26 | Infineon Technologies Ag | Protective device for subassemblies and method for producing a protective device |
| WO2012064708A1 (en) * | 2010-11-12 | 2012-05-18 | Apple Inc. | Unitary housing for electronic device |
-
1986
- 1986-04-23 JP JP61092175A patent/JPS62249458A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62177041U (en) * | 1987-03-25 | 1987-11-10 | ||
| JPH0346503Y2 (en) * | 1987-03-25 | 1991-10-01 | ||
| US6140698A (en) * | 1998-12-21 | 2000-10-31 | Nortel Networks Corporation | Package for microwave and mm-wave integrated circuits |
| US7235873B2 (en) * | 2001-08-01 | 2007-06-26 | Infineon Technologies Ag | Protective device for subassemblies and method for producing a protective device |
| WO2012064708A1 (en) * | 2010-11-12 | 2012-05-18 | Apple Inc. | Unitary housing for electronic device |
| JP2013542620A (en) * | 2010-11-12 | 2013-11-21 | アップル インコーポレイテッド | Unitary housing for electronic devices |
| US8730656B2 (en) | 2010-11-12 | 2014-05-20 | Apple Inc. | Unitary housing for electronic device |
| AU2011326123B2 (en) * | 2010-11-12 | 2015-04-23 | Apple Inc. | Unitary housing for electronic device |
| TWI555453B (en) * | 2010-11-12 | 2016-10-21 | 蘋果公司 | Single housing for electronic devices |
| US10118560B2 (en) | 2010-11-12 | 2018-11-06 | Apple Inc. | Unitary housing for electronic device |
| EP3648154A1 (en) * | 2010-11-12 | 2020-05-06 | Apple Inc. | Unitary housing for electronic device |
| US10696235B2 (en) | 2010-11-12 | 2020-06-30 | Apple Inc. | Unitary housing for electronic device |
| US11505131B2 (en) | 2010-11-12 | 2022-11-22 | Apple Inc. | Unitary housing for electronic device |
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