JPS61131679U

JPS61131679U -

Info

Publication number: JPS61131679U
Application number: JP1476785U
Authority: JP
Priority date: 1985-02-05
Filing date: 1985-02-05
Publication date: 1986-08-16

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例を示すブロツク図
、第２図は従来のレーダ装置を示すブロツク図、
第３図は送信パルスと送信開始時に距離Ｒにある
目標からの受信信号の１例を示す図である。図において、１はアンテナ、２は送受切換器、
３は送信器、４は受信器、５はＡ／Ｄコンバータ
、６はメモリ、７はアドレスカウンタ、８は周波
数分析器、９は表示器、１０はレーダタイミング
発生器、１１ａは送信パルス、１１ｂは送信パル
ス、１１ｃは送信パルス、１１ｄは送信パルス、
１２ａは受信信号、１２ｂは受信信号、１２ｃは
受信信号、１２ｄは受信信号、１３はレジスタ、
１４はカウンタ、１５はカウンタ、１６はカウン
タ、１７はカウンタである。なお、各図中同一符
号は同一または相当部分を示す。 Fig. 1 is a block diagram showing an embodiment of this invention, Fig. 2 is a block diagram showing a conventional radar device,
FIG. 3 is a diagram showing an example of a transmitted pulse and a received signal from a target located at a distance R at the time of starting transmission. In the figure, 1 is an antenna, 2 is a transmitter/receiver switch,
3 is a transmitter, 4 is a receiver, 5 is an A/D converter, 6 is a memory, 7 is an address counter, 8 is a frequency analyzer, 9 is a display, 10 is a radar timing generator, 11a is a transmission pulse, 11b is a transmission pulse, 11c is a transmission pulse, 11d is a transmission pulse,
12a is a received signal, 12b is a received signal, 12c is a received signal, 12d is a received signal, 13 is a register,
14 is a counter, 15 is a counter, 16 is a counter, and 17 is a counter. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims

[Scope of utility model registration request]

an antenna, a transmitter/receiver switch that switches input/output of the antenna, a transmitter that supplies a transmission signal to the transmitter/receiver switch, a receiver that receives the output of the transmitter/receiver, and receives the output of the receiver as an input. an A/D converter for converting into a digital signal;
A memory that stores the output of the D converter, a frequency analyzer that performs frequency analysis using the data stored in the memory, a display that displays the output of the frequency analyzer, and a radar timing generator that generates radar timing. a register that holds an initial value; a first counter that counts at a timing generated by the radar timing generator using the value held in the register as an initial value; and a carry output generated by the first counter. a second counter that counts according to the timing generated by the radar timing generator with the count value of the second counter as an initial value; and a third counter that counts using the carry output of the third counter. The present invention is characterized by comprising a fourth counter that starts counting, and an address counter that starts counting at the carry output of the third counter, stops counting at the carry output of the fourth counter, and generates the address of the memory. radar equipment.