JPS61131123A - Floating point arithmetic unit - Google Patents

Abstract

PURPOSE:To simplify the unit and to attain high speed processing by expanding processing data length for a rounding adder/subtractor and applying in advance arithmetic operation including digits expanded by a carry so as to eliminate the need for various circuits. CONSTITUTION:The processing data length of the rounding adder/subtractor 31 is expanded toward the lower-order by 2 digits so as to add the most significant bit of a preceding digit to the corresponding digit to any of the least significant bits in three digits of the low-order in response to the state of a mantissa part adding/subtracting adder/subtractor 18. Thus, the rounded data is outputted from the least significant bit, then neither a shifter nor an exponent switch selector is required. Further, the processing data length of an adder/ subtractor 31 is expanded by 1 bit toward the high-order and the arithmetic operation is executed in advance including digits expanded by the carry. Thus, generation of carry at rounding is prevented, the right shift function of a mantissa normalizing shifter is not required and a control circuit controlling the said shifter is not required.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a normalized 2
The present invention relates to a floating point arithmetic device that performs addition and subtraction between two floating point data and outputs normalized floating point data.

[Technical Background of the Invention] Floating point data applied in this type of floating point arithmetic unit is generally e formatted as shown in the format of FIG.
Bit exponent E, 0 digit (1 digit consists of m bits)
dn-1) and a 1-bit sign part S indicating the sign of the mantissa part M and the sign of the mantissa part M. FIG. 5 shows the configuration of a conventional floating point arithmetic unit. In Figure 5,
Floating point data OP1 to be subjected to floating point operations.
OP2 (with the exception of the sign part S) is latched into register 11.12.

Floating point data OP1. OP2 is normalized.

Normalized means that the most significant digit dO of the mantissa part M is not 0. Floating point data OP1. latched in registers 11.12. Each exponent part E of OP2 is supplied to a subtracter 13. This allows floating point data OP
1. Subtraction is performed between the exponent parts E of OP2, and the difference between the exponents is determined. The sign of this difference, that is, which exponent is larger, OPl or OF2, is determined by the carry (pollow) of the subtractor 13.
Shown in the output.

Floating point data O latched in registers 11.12
P1. Each exponent part E of OP2 is also supplied to the selector 14. The selector 14 selects the larger exponent part E of the exponent parts E of OPl and OF2 according to the carry output from the subtracter 13. On the other hand, each mantissa part M of the floating point data OP1°OF2 latched in registers 11 and 12 is
The signal is supplied to selector 15 and selector 16, respectively. The selector 15 selects the larger mantissa part M of the mantissa parts M of OPl and OF2 according to the carry output from the subtracter 13.

On the other hand, the selector 16 selects the smaller mantissa part M of the mantissa parts M of OPl and OF2. Selector 16
The selection data is supplied to the right shifter 11.

The right shifter 17 transfers the selected data of the selector 1B to the subtracter 1.
It is shifted to the right by the number of digits indicated by the subtraction result of 3 (ie, the difference between the exponents of OPl and OF2) to align the digits with the mantissa part M having the larger exponent. The input to the right shifter 17 is 0 digits, the output is n+2 digits, and the number of digits is expanded in the lower direction of the input. In the floating point arithmetic unit shown in FIG. 5, the accuracy of calculations is increased by including up to two digits shifted out to the right in subsequent calculations. This extra digit to be calculated is called a guard digit, and the accuracy of the calculation varies depending on the number of digits. Here, a case where the guard digit is two digits will be explained.

The selection data of the selector 15 is supplied to six inputs of the n+2-digit adder/subtractor 18, and the output data of the right shifter 17 is also supplied to the B input. Therefore, the adder/subtractor 18 adds or subtracts the scaled mantissa part M from the outside.
Operation mode signal ADDI (ADD
(addition with I-1, subtraction with ADDI-0). The calculation result of the adder/subtractor 18 is as shown in FIG.
Cases 1 and 2 are classified for addition and cases 3 to 6 for subtraction.

Note that case 5 in which do and di of the calculation results of the adder/subtractor 18 are both O can occur when the difference in the exponent parts is O or 1. Case 6 in which the calculation result of the adder/subtractor 18 is negative
can occur when the difference in exponent parts is O.

The calculation result of the adder/subtractor 18 (do, dl, dn-1
, ao.

gl (n+2 digits) is supplied to the pre-shift shifter 19 for normalization with a fixed value 1 (1 bit) added to the upper part of the result of the operation. The input of shifter 19 is 1 bit (1 digit') + (n+2) digits, and the output is 0 digit +
1 pit, and the 0 digits + 1 bit of the output corresponds to the 0 digits + 1 bit from the higher order of the input. The shifter 19 has three types of operation functions: left 1-digit shift, through (no shift), and right 1-digit shift. The control circuit 20 controls the carry output (CO) of the adder/subtractor 18 and the most significant digit dO of the calculation result of the adder/subtractor 18. That is, shift ¥19- is the right 1 if a carry occurs (Co-1) from the adder/subtracter 18 when the adder/subtracter 18 is performing an addition operation.
Set to digit shift mode. Further, the shifter 19 is set to through mode if there is no carry when the adder/subtracter 18 is performing an addition operation, or if the result is positive (dO≠0 at Co-1) when the adder/subtractor 18 is performing an addition operation. , if there is no carry during an addition operation, or if the result is positive and dO-0 during a subtraction operation, the shifter 19 is set to the left one digit shift mode. If the result is negative (CO-0), the through mode is set.

The upper 0 digits of the output of shifter 19 (0 digit + 1 pit) are 0
Addition and subtraction of digits! It is supplied to 8 inputs of s21. Adder/subtractor 2
Fixed to A input of 1! IO is provided. Adder/subtractor 21
is used as an adder for rounding when the operation result of the adder/subtractor 18 is positive, and as a subtracter for converting from negative to positive (subtracting the operation result of shifter 19 from O) when it is negative. . The operation mode of the adder/subtractor 21 is specified by the control circuit 20. That is, the adder/subtractor 21 is set to the addition mode when the adder/subtractor 18 is in an addition operation or in a subtraction operation and the result is positive (C0-1).

Further, the adder/subtractor 21 is set to the subtraction mode when the adder/subtractor 18 is in a subtraction operation and the result is negative (Co-0) (7>).

Rounding is performed by supplying the least significant bit of the output of shifter 19 to the carry input (CI) of adder/subtractor 21 in addition mode. On the other hand, adder/subtractor 18
The conversion of the calculation result from negative to positive is performed by supplying 1 to the input voltage (CI) of the adder/subtractor 21 in the subtraction mode. The carry data to the adder/subtractor 21 is supplied from a selector 22 that selects the least significant bit of the output of the shifter 19 or a fixed value. The selection operation of the selector 22 is controlled by the control circuit 20 described above. Therefore, when the adder/subtractor 18 is in an addition operation or in a subtraction operation and the result is positive (CO=
In the case of 1), the least significant bit of the output of the shifter 19 is selected for rounding, and when the adder/subtracter 18 is performing a subtraction operation and the result is negative (Go-0), 7 is selected.

From the above, in cases 1 to 6 in FIG. 6, the upper 0 digits of the output of the shifter 19, that is, the contents of the eight inputs of the adder/subtractor 21 are as shown by the underlines. As is clear from the figure, in cases other than case 1, the upper 0 digit of the output of the shifter 19,
That is, the contents of the 8 inputs of the adder/subtractor 21 are 1. Addition and subtraction a18
The carry output (Co) of is not included. Moreover, in case 1, it is Co-1. Therefore, in FIG. 5, a fixed value 1 is supplied to the top of the shifter 19 instead of CO.

In addition, in cases 1 to 6 in FIG.
The data (bit) position to be carried by 1 is as shown by the symbol.

Now, when a shift operation is performed by the shifter 19, it is necessary to correct the index accordingly. Therefore, the floating point arithmetic unit shown in FIG. 5 is provided with a selector 23 for selecting one of +1, o, or -1, and an adder 24. The selector 23 is controlled by instructions to the shifter 19 from the htm circuit 20 described above. Thus, the selector 23 selects +1 when the shifter 19 is in the right one-digit shift mode, -1 when it is in the left one-digit shift mode, and selects O when it is in the through mode. The selection data of the selector 23 is supplied to the adder 24 and added to the index selected by the selector 14. As a result, index correction for the shift operation of the shifter 19 is performed.

The calculation result (0 digit) of the adder/subtractor 21 is supplied to a leading zero digit detector (hereinafter referred to as LZD detector) 25, which detects the number 1 of the leading zero digit. Further, the calculation result (0 digit) of the adder/subtractor 21 is supplied to the shifter 26 with a fixed value 1 (1 pit) added to the upper part of the calculation result. The shifter 26 is the adder/subtractor 21
Rounding (addition) is performed at , resulting in a carry (
CO2-1), the calculation result of the adder/subtractor 21 is shifted one digit to the right. In this case, the most significant digit of the output data of the shifter 26 is 1. On the other hand, in cases other than the above, the shifter 26 performs a left shift by one digit of the leading zero digit detected by the LZD detector 25. As a result, floating point data OP1. The normalized mantissa part M of the floating point operation result of OP2 is obtained. The operation of the chic 26 is based on the operation mode signal ADD2 which specifies the operation mode of the adder/subtractor 21, the key IJ- output (C
O2) LZD detector 25f7) Controlled by the control circuit 27 according to the result of detecting the number of digits. ``The control circuit 27 also controls the adder/subtractor 28 that calculates the exponent part E of the floating point operation result. The adder/subtracter 28 adds 1 to the addition result of the adder 24 when the shifter 26 performs a one-digit shift to the right. On the other hand, when the shifter 26 performs a left shift, the adder/subtractor 28 subtracts the number of digits of the shift from the addition result of the adder 24.

The control contents of the control circuit 20 for the shifter 19, the adder/subtracter 21, the selector 22, and the selector 23 described above are as follows:
Carry output (Co) of unit 18 and adder/subtractor 18
Table 1 shows the correspondence with the most significant digit dO of the calculation result.

Further, the control circuit 2 for the shifter 26 and the adder/subtractor 28
The control contents of 7 are shown in Table 2 in correspondence with the operation mode (addition/subtraction) of the adder/subtractor 21 and the carry output (CO2) of the adder/subtractor 18.

31111 Table 2 [Problem 1 of Background Art] In the conventional floating point arithmetic device described above, floating point data OP1. Although floating point operations in OP2 are performed correctly, there are various problems described below. Ta.

■ Adder/subtractor 21 for rounding (and conversion from negative to positive)
A shifter 19 is required between the adder/subtractor 18 for mantissa operation and the adder/subtractor 21 in order to supply rounding bits to the carry input.

(2) Since the shifter 19 is used, a selector 23 and an adder 24 are required to correct the exponent by the number of digits shifted by the shifter 19.

(2) Since a carry may occur as a result of rounding (addition for rounding) in the adder/subtractor 21, the shifter 26 for normalizing the mantissa needs not only a left shift function but also a right shift function.

(2) For the same reason as (2) above, the adder/subtractor 28, which has not only a subtraction function but also an addition function, is required as a means for determining the exponent part of the floating-point operation result.

(2) For the same reason as (2) above, a control circuit 27 is required to control the left/right shift of the shifter 26 and the addition/subtraction of the adder/subtractor 28.

[Purpose of the Invention] This invention was made in view of the above circumstances, and its purpose is to eliminate the need for carrying manpower to the adder for rounding (and conversion from negative to positive), and to eliminate the need for the same number of rounds due to rounding. It is an object of the present invention to provide a floating point arithmetic device which can eliminate the occurrence of carries from adders and subtracters, thereby simplifying the circuit configuration.

[Summary of the Invention] According to the present invention, normalized first and second A floating point arithmetic unit is provided that performs addition or subtraction between floating point data and outputs normalized third floating point data. This floating point arithmetic device includes first and second subtracters, selection means, digit alignment means, and n+g digits (Ω is the number of guard digits used to improve the precision of calculation).
, a second adder/subtractor for n+g+1 digits, a leading zero digit detector, a left shifter, and an adder.

In the above floating point arithmetic device, the first subtractor includes a first
and calculates the exponent difference between the exponent parts of the second floating point data. The selection means selects an exponent part of the floating point data having a larger exponent out of the first or second floating point data according to the subtraction result of the first subtracter. Further, the digit alignment means shifts the mantissa part of the floating point data having the smaller exponent to the right by the difference between the exponents of the first and second floating point data in accordance with the subtraction result of the first subtracter. This performs digit alignment of the mantissa parts of the first and second floating point data.The first adder/subtractor adds or Subtraction is performed in response to a first calculation mode signal.

The operation result (n+g digits) of the first adder/subtractor is supplied to one input of the second adder/subtractor, which converts the operation result to a positive value when it is negative, and rounds it when it is not negative. The other input of the second adder/subtractor is supplied with each bit of the 1st digit to the n+g-4th digit, the n+g digit, and the n+a-3rd digit to the n+a-th digit.
- Correction data in which the upper three bits of each digit are O is supplied. The second adder/subtractor performs addition or subtraction between the data supplied to both of these inputs according to the second operation mode signal. The contents of the least significant bit and the 0th digit (most significant digit) of the n+g-3rd digit to n+g-1st digit of the correction data and the second operation mode signal are as follows: It is determined by the control circuit according to the carry output of , all the most significant bits of the operation result of the first adder/subtractor, the most significant bit of each of the lower 1+Q digits, and the first operation mode signal.

The leading zero digit detector detects the number of leading zero digits of the operation result of the second adder. The left shifter shifts the operation result of the 2'2 adder/subtractor to the left by the number of leading zero digits detected by the leading zero detector. As a result, the normalized mantissa part of the floating point operation results of the first and second floating point data, ie, the mantissa part of the third floating point data, is obtained.

On the other hand, the exponent part of the third floating point data is obtained by adding 1 by an adder to the exponent of the exponent part selected by the selection means, and from the +1 result, the leading zero digit detected by the leading zero detector. It can be found by subtracting the number of digits.

[Embodiment of the Invention] An embodiment of the invention will be described below with reference to FIGS. 1 to 3. Note that the same parts as in FIG. 5 are given the same reference numerals and detailed explanations are omitted. In the floating point arithmetic unit shown in FIG. 1, numeral 31 is a 1-bit+(n+2) digit adder/subtracter for rounding the operation result of the adder/subtractor 18 or converting from negative to positive; The handling data length is expanded by 1 bit + 2 digits compared to . The expanded two digits match the guard digits of the adder/subtractor 18 for mantissa calculation. Lower n+2 of 8 inputs of adder/subtractor 31
The digits contain the output data of the adder/subtractor 18 (digits dO, dl,...
・N+2 digit calculation result consisting of dn-1, gO, gl)
is supplied, and its upper (most significant bit) is fixed 1i!
0 is supplied. On the other hand, the six inputs of the adder/subtractor 31 are supplied with correction data necessary for the above-mentioned rounding or conversion from negative to positive.

As shown in FIG. 2, the data length of the above correction data is bit C (MSB) and digits do, dl, -dn-1,
gO, ol (LSD) 1 bit + (n+2)
It is a digit. dO-dn-3 and gl of the above correction data
all bits of each digit, and the upper mm-1 of each digit of dn-2, dn-1, and go (represents the number of bits constituting one digit)
All bits are 0. Further, the most significant bit C of the correction data is la+. In addition, the correction data dn-
2, dn-1, the least significant bit of each digit of go (dn-IL
SB, dn-2LSB, QOLSB) is In-2
゜1n-1,1CI. These II, 1n-
Each bit data of 2, 1n-1, and Ia is sent to the control circuit 32.
Supplied from.

The control circuit 32 receives an arithmetic mode signal ADD1 . Adder/subtractor 18
The carry output (Co) of
An operation mode signal that specifies the operation mode of the adder/subtractor 31 according to the most significant bit of 1 digit dn-IM S B, the most significant bit of 00 digit aOM S B, and the most significant bit of 91 digit g1 M S B ADD3 and the above [,
It has the necessary circuit configuration for outputting In-2, In-1, and Ig (17). FIG. 3 shows the configuration of the control circuit 32, in which the OR gate 41 receives the arithmetic mode signal A.
DDI and carry output from adder/subtracter 18 (Co
) is supplied. The output signal of the OR gate 41 is supplied to the M input of the adder/subtractor 31 as an operation mode signal ADD3. The above calculation mode signal ADDI and the adder/subtractor 18
The carry output 1 (CO) from the Exclusive NOR gate (hereinafter referred to as “EXNOR”) 42
Also supplied. The output signal of the EXN OR 42 is supplied as the bit data to the six inputs (the most significant bit C) of the adder/subtractor 31. In addition, the above ADDI and C
O is the most significant digit of (In-1) in the output data of the adder/subtractor 18, dn-1M S B, and the AND gate 4.
3. The output signal of the AND gate 43 is the six inputs of the adder/subtractor 31 (
dn-2 least significant bit (dn-2LSB) of the dn-2 digit. Also, do in the output data of the adder/subtractor 18
All bits (m bits) of the digit are provided to a NOR gate 44 . The output signal from the NOR gate 44 is E
Along with the output signal from OR42, the NOR gate 4
5. The output signal from the NOR gate 45 is the most significant bit aO of the gO digit in the output data of the adder/subtractor 18.
It is supplied to the AND gate 46 together with MSB. The output signal of the AND gate 46 is the bit data (n-
It is supplied as 1 to the A input of the adder/subtractor 31 (dn-1 digit least significant bit dn-ILSB). Further, the output signal from the NOR gate 44 is also supplied to the inverter 47.

The output signal of the inverter 41 is supplied to the NOR gate 48 along with the output signal la+ from the EXNOR 42. The output signal from the NOR gate 48 is sent to the adder/subtracter 1
The most significant bit of g1 digit in the output data of 8 g1M S
It is supplied to the AND gate 49 together with B. The output signal of the AND gate 49 is the A input of the adder/subtractor 31 (the least significant bit gOLSB of the gO digit) as the bit data Ig.
supplied to

Referring again to FIG. 1, 1 bit of adder/subtractor 31 + (
The n±2) digit output data is connected to each input of an LZD detector (leading zero digit detector) 33 that detects the number of leading zero digits of the output data, and a left shifter 34. The input of the left shifter 34 is n+3 digits, and the output is 0 digit, and the 0 digit of the output corresponds to the upper 0 digit position of the input. The left shifter 34 shifts the output data of the adder/subtractor 31 to the left by the number of leading zero digits detected by the LZD detector 33, and outputs a normalized mantissa part.

At this time, the most significant bit 1 of the output data of the adder/subtractor 31 is treated as one digit. On the other hand, selector 14
The selection data (exponent part E) is supplied to six inputs of the adder 35. A fixed value of 1 is supplied to 8 inputs of the adder 35. The output data of the adder 35 is supplied to six inputs of a subtracter 36 for outputting the exponent part of the floating point arithmetic result. The detection result of the LzD detector 33 (ie, the number of leading zero digits of the output data of the adder/subtractor 31) is supplied to eight inputs of the subtracter 36.

Note that the circuit for detecting overflow, underflow, and zero in the result of the operation of the adder/subtractor 18, the circuit for generating the sign of the result of the floating-point operation, and the like are not directly related to the present invention, and therefore their description will be omitted.

However, zero detection is performed by the LZD detector 33. If the LZD detector 33 detects that the mantissa part is zero, the exponent part of the floating-point operation result is forcibly set to zero. This circuit is omitted because it is not directly related to this invention.

Now, in the floating point arithmetic unit shown in FIG.
．． It is latched to 12. Each exponent part E of the floating point data OP1°OF2 latched in the registers 11 and 12 is supplied to the subtracter 13. This allows floating point data O
P1. Subtraction is performed for the exponent part 1 of OP2, and the difference between the exponents is determined.

The carry (borrow) output of the subtractor 13 indicates whether the difference is positive or negative, that is, which exponent is larger, OPI or OF2. Floating point data OP1. latched in register 1.12. Each mantissa part M of OP2 is supplied to the selector 15 and the selector 16, respectively. The selector 15 is
According to the carry output from the subtracter 13, OPl, OF2
The larger mantissa part M is selected from among the mantissa parts M of . On the other hand, the selector 16 selects the smaller mantissa part M of the mantissa parts M of OPl and OF2. The selection data of the selector 16 is supplied to the right shifter 17. The right shifter 11 converts the selection data of the selector 16 into the subtraction result of the subtracter 13 (
That is, the number of digits indicated by the difference between the exponents OPl and OF2 is also shifted to the right to align the digits with the mantissa part M having the larger exponent. The mantissa digit alignment process described above is the first stage (referred to as equalization) of floating point arithmetic.

The selection data of the selector 15 is supplied to six inputs of an (n+2) digit adder/subtractor 18. The output data of the right shifter 11 is supplied to eight inputs of the adder/subtractor 18 . The adder/subtractor 18 is
Addition or subtraction of the scaled mantissa part M is performed according to the operation mode signal ADDI. The above mantissa addition and subtraction is the second stage of floating point operations.

Next, rounding/inversion (conversion from negative to positive), which is the third stage of floating point arithmetic, will be explained.

All bits of 60 digits that are part of the n+2 digit output data (mantissa addition/subtraction result) of the adder/subtractor 18, the most significant bit of dn-1 digit dn-IM S B, the most significant bit of gO digit aOM S B , and the most significant bit gI of the 01 digit
MSB is output from the control circuit 3 along with the arithmetic mode signal ADD1 and the carry output (Co) of the adder/subtractor 18.
2. According to these input data, the control circuit 32 generates part of the correction data for rounding or conversion from negative to positive (i.e., bit data Is, In-2°1n-1,
1(] ) and an arithmetic mode signal ADD3 specifying the arithmetic mode of the adder/subtracter 31.

The bit data ll1l output from the control circuit N32 is
It is supplied to the most significant bit C of the six inputs of the adder/subtractor 31.

Similarly, bit data In-2, In-1, [ is addition/subtraction 1
1ii131 A input's dn-2, dn-1, gO digit's least significant bit dn-2LSB, dn-ILS
B, supplied to OOLSB. In addition, all bits of dO to dn-3 digits and 01 digit of the six inputs of the adder/subtractor 31, and the upper m71 of dn-2, dn-1, and gO digits
A fixed value of 0 is supplied to the pit.

On the other hand, the lower n+2 digits of the 8 inputs of the adder/subtractor 31 are supplied with the output data of the n+2 digits of the adder/subtractor 18, and the fixed value 0 is supplied to the most significant bit of the 8 inputs.

Furthermore, an arithmetic mode signal ADD3 outputted from the control circuit 32 is supplied to the M input of the adder/subtractor 31.

The adder/subtractor 31 performs addition or subtraction between A and 8 manual inputs according to the calculation mode signal ADD3.

As is clear from the third factor, the calculation mode signal ADD3 is determined by the calculation mode signal ADD1 and the carry output (CO) from the adder/subtractor 18. Specifically, the calculation mode signal ADD3 becomes O only when ADDi =Co -0, that is, only when the calculation (subtraction) result of the adder/subtractor 18 is negative. This causes the adder/subtractor 31 to perform subtraction (
(conversion from negative to positive) is indicated. On the other hand, adder/subtractor 18
If the operation result is not negative, ADD3 becomes 1,
Addition (rounding) is instructed to the adder/subtractor 31.

Bit data la+ is an operation mode signal!, similar to operation mode signal ADD3. It is determined by ADD1 and the carry output (Go) from adder/subtractor 18. Specifically, ■- is 1 in the case of ADDl-Co, and O in other cases. This indicates that when addition is performed in the adder/subtractor 18, the carry from the adder/subtractor 18 is given to the most significant bit of the six inputs of the adder/subtractor 31. Also,
When subtraction is performed in the adder/subtracter 18, the carry level inverted data from the adder/subtracter 18 is given to the most significant bit of the six inputs of the adder/subtracter 31. Note that in the case of subtraction, the result is positive if a carry occurs, and the result is negative if there is no carry, which is different from the carry in the case of addition. As is clear, la+ is 1 only in case 1 and case 6 among the six cases shown in FIG.

As shown in FIG. 3, the bit data I n-2 includes the operation mode signal ADD1, the carry output (Go) from the adder/subtractor 18, and the output data dn-1 of the adder/subtractor 18.
The most significant bit of the digit is determined by dn-IMSB. Specifically, I n-2 matches dn-IM S 8 when ADDi −Co =1, and becomes O otherwise. That is, case 1 of the six cases shown in Figure 6
In this case, dn-1M SB is used as In-1.

As shown in FIG. 3, the total data in-1 includes the operation mode signal ADD1, the carry output (Co) from the adder/subtractor 18, and the output data d of the adder/subtractor 18.

All bits of the digit and 90 of the output data of the adder/subtractor 18
Determined by the most significant bit of the digit gOM_SB.

j1 Overall, 4trn-1 is ADD1≠Co (addition is performed in the adder/subtractor 18 and no carry occurs, or subtraction is performed in the adder/subtractor 18 and a carry occurs) and
If one dO≠O, it matches Ω0M5B, and in other cases it becomes O. That is, among the six cases shown in FIG. 6, gOM S B is used as l n-1 only in case 2.3.

Similar to ln-1, the bit data Ia is generated by the operation mode signal ADD1 and the carry output (G
o) All 60-digit bits of the output data of the adder/subtractor 18,
and the output of the adder/subtractor 18 to the most significant bit gOMSB of the 90 digits of data. Specifically, I(
7 is glM when ADD1≠Go (addition is performed in the adder/subtractor 18 and no carry occurs, or subtraction is performed in the adder/subtractor 18 and a carry occurs) and dO−0.
Matches SB, otherwise O. That is, among the six cases shown in FIG. 6, aIM SB is used as Ia only in cases 4 and 5.

The control contents of the control circuit 32 for the adder/subtractor 31 described above are made in correspondence with the operation mode (addition/subtraction) of the adder/subtractor 18, the carry output (CO) of the adder/subtractor 18, and the 60 digits of the output data of the adder/subtractor 18. It is shown in Table 3.

Table 3*: r rreIevent en: [n -2, In -L e in each item of 1G
n means dn-1MS8゜aOMsB, glM
Indicates that it is sB.

In the adder/subtractor 31, addition (rounding) or subtraction (conversion from negative to positive) between the A and B input contents is performed as follows by the control operation of the control circuit 32 shown in Table 3.

(1) When addition is performed in the adder/subtractor 18 and a carry occurs (corresponds to case 1 in FIG. 6) In this case, of the correction data supplied to the six inputs of the adder/subtractor 31, the most significant bit C is 1, and the least significant bit of dn-2 digits dn-
The 2LSB matches the most significant bit dn-IMSB of the dn-1 digit of the output data of the adder/subtractor 18, and the other bits are fixedly set to 0. The adder/subtractor 31 adds the six-input data (correction data) to the B input data, that is, the n+2 digit output data of the adder/subtractor 51g, with O (1 pit) added to the upper part. The most significant bit C of the 8 inputs is O, so no carry occurs from the adder/subtractor 31, and since the most significant bit C of the 6 inputs is 1, the most significant bit C of the output data of the adder/subtractor 31 becomes 1. This 1 correctly reflects the occurrence of a carry in the addition operation of the adder/subtractor 18.

Furthermore, since the most significant bit dn-IM S B of the dn-1 digit of the output data of the adder/subtractor 18 is used as the least significant bit dn-2L3B of the dn-2 digit of the A manual data, the output data of the adder/subtractor 18 dn-2 digit least significant bit, next dn-1 digit most significant bit dn-1M S
B is added and rounding is performed. This operation is performed in case 1 of the sixth factor, at the bit position (d
This is equivalent to the case where the data of the n-1 digit (most significant bit) is rounded by the selector 22 and the adder/subtracter 21 as a carry.

(a) When addition is performed in the adder/subtractor 18 and no carry occurs (corresponding to case 2 in Figure 6), in this case,
Among the correction data supplied to the six inputs of the adder/subtractor 31,
The least significant bit of dn-1 digit dn-1 and SB are adder/subtractor 1
The most significant 1 bit aO of the 00 digit of the output data of 8
Matches M S 8, and otherwise is fixedly set to 0. The adder/subtractor 31 adds the six input data (correction data) and the B input data, that is, the n+2 digit output data of the adder/subtractor 18 with O (1 pit) added to the upper part. The most significant bits C of are both O, so no carry occurs from the adder/subtractor 31. Also, the most significant bit gOM8B of the 00 digit of the output data of the adder/subtractor 18 is the dn-1 digit of the 6-input data. Since it is used as the least significant bit dn-ILSB of the adder/subtractor 18, the most significant bit of the next 00 digit is added to the least significant bit of the dn-1 digit of the output data of the adder/subtractor 18, and rounding is performed. This operation is equivalent to the case where the data at the bit position indicated by the symbol M (the most significant bit of the 00 digit) is rounded as a carry of the adder/subtractor 21 through the selector 22 in case 2 of FIG. be.

(3) When subtraction is performed in the adder/subtractor 18 and the content of the 60 digits of the result is not 0 and a carry occurs (the result is positive) (corresponding to case 3 in FIG. 6), in this case, the adder/subtractor 31 Of the correction data supplied to the six inputs of dn-1
The least significant bit dn-ILSB of the digit matches the most significant bit aOM S B of the 00 digit of the output data of the adder/subtractor 18, and the other bits are fixed to O. The adder/subtractor 31 adds the 6-input data (correction data) and the 8-input data, that is, the n+2-digit output data of the adder/subtractor 18 with O (1 pit) added to the upper part. The most significant bit C of the 8 inputs A and 8 is O, so no carry is generated from the adder/subtractor 31. Also, the most significant bit of the 00 digit of the output data of the adder/subtractor 18 (IOM S B is the least significant bit of the dn-1 digit of the six-input data, dn-I L
Since it is used as S B, the most significant bit of the next 00 digit QQM 8 B is added to the least significant bit of the dn-1 digit of the output data of the adder/subtractor 18, and rounding is performed.

This operation is shown by the symbol M in case 3 of diagram M6.
This is equivalent to the case where the data at the bit position (most significant bit of +110 digits) is manually rounded as a carry of the adder/subtractor 21 via the selector 22.

(4) When subtraction is performed in the adder/subtractor 18 and the content of the 60th digit of the result is 0 and a carry occurs (the result is positive) (corresponding to case 4.5 in Figure 6), in this case, the addition/subtraction Of the correction data supplied to the six inputs of the device 31, 0
The least significant bit of the 0th digit (IOLsB matches the most significant bit of the g1th digit (IIMSB) of the output data of the adder/subtractor 18,
Otherwise, it is fixed to O. The adder/subtractor 31 inputs A input data (correction data) and B human data, that is, the adder/subtractor 1.
The output data of n+2 digits of 8 is added with data in which O (1 bit) is added to the upper part. The most significant hit C of the 8 inputs A and 8 is 0, so no carry is generated from the adder/subtractor 31. Also, the most significant bit of the 91st digit of the output data of the adder/subtractor 18! IIM S B is A
The 90 least significant bits of the input data are used as gOLSB, so the 90 least significant bits of the output data of the adder/subtractor 18 are the most significant bits of the next 91 digits! IIIMs
B is added and rounding is performed. This operation, in cases 4 and 5 in FIG.
This is equivalent to the case where rounding is performed manually using the carry of the adder/subtractor 21 with 9 reasons. In addition, when subtraction is performed in the adder/subtractor 18, the resulting do and the contents of the 61st digit are O, and no carry occurs (corresponding to case 5 of the 6th factor)
is floating point data OP1. The difference in the exponent part of OP2 is 0
or 1, and in this case, the first digit of Ω is always 0. Therefore, as mentioned above, the most significant bit g of the 91st digit
Rounding with IMSB does not cause recirculation problems.

(5) When subtraction is performed in the adder/subtractor 18 and no carry occurs (the result is negative) (corresponds to case 6 in FIG. 6) In this case, the correction data supplied to the six inputs of the adder/subtractor 31 Among them, the most significant bit C is set to 1, and the other bits are fixedly set to O. The adder/subtractor 31 converts the A input data (correction data) into B input data, that is, n+2 of the adder/subtractor 18.
Subtract data with 0 (1 bit) added to the upper part of the digit output data. The subtraction result of the adder/subtractor 31 is 109·t: 7. Since the most significant bit C of the 6 inputs is 1.8 and the most significant bit of the input is O. : AA, +) (7)
l Q (7)°"21"015 Therefore, the negative output data of the adder/subtractor 18 is converted into positive data.

The above is the third stage of floating-point operations, rounding/inversion (
(conversion from negative to positive).

Finally, normalization, which is the fourth stage of floating point arithmetic, will be explained.

The 1-bit+(n+2) digit positive output data of the adder/subtractor 31 is supplied to the LZD detector 33 and left shifter 34. The LZD detector 33 detects the number of leading zero digits of the output data of the adder/subtractor 31.

At this time, the LZD detector 33 treats the most significant bit of the output data of the adder/subtractor 31 as the most significant digit. That is, the LZD detector 33 operates as a counter for the number of leading zero digits of n+3 digit data. The left shifter 34 shifts the output data of the adder/subtractor 31 to the left by the number of leading zero digits detected by the LZ[ ) detector 33, and outputs the upper zero digit. The 0-digit output data from this left shifter 34 is floating point data OP1. The normalized mantissa part of the floating point operation result of OP2 is shown.

Now, when a left shift is performed by the left shifter 34, the value of the exponent part E selected by the selector 14 is subtracted by the number of left shift digits of the left shifter 34, and the exponent part correction accompanying the mantissa part normalization is performed. There is a need. However, with this alone,
Since the value would be one digit less than the correct exponent, 1 is added in advance to the value of the exponent part E selected by the selector 14.

This is due to the following reasons. That is, in this example, the number of leading zero digits detected by the LZD detector 33 includes one digit (one bit) extended to the most significant part of the mantissa. Therefore, even if the number of digits in the mantissa is 18.31
This is because the number of leading zero digits is counted as 1 even if it does not change before and after the operation. In other words, in this example, the number of leading zero digits is counted as one more digit. The exponent part correction for the extended digits is performed by the adder 35. That is, adder 35
adds a fixed value 1 to the value of the exponent part E selected by the selector 14 (the larger exponent part E of the exponent parts E of the floating point data OP1 and OP2). The subtracter 36 subtracts the number of leading zero digits detected by the LZD detector 33 from the output data of the adder 35 (that is, the exponent part corrected by +1). The output data of the subtracter 36 indicates the exponent part E of the floating point operation result of the floating point data OP1°○P2.

Therefore, if the adder/subtracter 18 performs addition and a carry occurs, or if the most significant bit of the output data is set to 1 due to rounding in the adder/subtracter 31, LZ
The number of leading zero digits detected by the D detector 33 is O, and the +1 correction result by the adder 35 directly becomes the exponent part E of the floating point arithmetic result.

As described above, according to this embodiment, ■ the processing data length of the adder/subtractor 31 for rounding or conversion from negative to positive is extended from the conventional 0 digits to the lower digits (1 bit in the upper part); , the MSB of one lower digit of the five digits can be added to any of the lower three LSB digits depending on the state of the adder/subtractor 18 for mantissa addition/subtraction (that is, depending on each case in FIG. 6). Therefore, there is no need for a shifter (shifter 19 in FIG. 5) for outputting rounding data from the least significant bit.

(2) Since this type of shifter is not required, a selector for switching index correction data (selector 23 in FIG. 5) is not required.

■ The processing data length of the adder/subtractor 31 for rounding or conversion from negative to positive has been changed from the conventional 0 digit to 1 bit in the upper part (2 bit in the lower part).
Since the calculation is performed in advance including the digits to be extended by carry, the occurrence of carries during rounding can be prevented.

■ Due to the above (■), it is no longer necessary to provide the shifter for mantissa normalization with a right shift function.

(2) According to the above (2), a subtracter (subtractor 36) may be used instead of an adder/subtractor (adder/subtractor 28 in FIG. 5) for exponent calculation.

(2) The above (2) eliminates the need for a circuit such as the control circuit 27 that detects the occurrence of a carry from the rounding adder/subtractor 21 and controls the shifter 26 and the adder/subtractor 28, as shown in FIG. 1. Furthermore,
In the above embodiment, the processing data length of the adder/subtractor 31 was explained as being 1 bit + (n+2) times, but
It may be a digit. In this case, it is sufficient to supply the dot data 1m to the least significant bit position of the most significant digit of the adder/subtractor, and supply the fixed value O to the remaining upper bit positions.

Further, in the embodiment described above, the case where the guard digit is two digits has been described, but the invention is not limited to this.

If the guard digit is 9 digits, the processing data length of the adder/subtracter for rounding or conversion from negative to positive should be 1 bit (digit) + (n+Q) digits, and the left shifter for mantissa normalization should be The input may be n+g+1 digits.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to eliminate the need for rounding (and carry to the adder/subtractor for negative to positive conversion), and it is possible to eliminate the need for carry from the adder/subtractor due to rounding. This eliminates the need for shifters and various other circuits that were conventionally provided between the adder/subtractor for adding and subtracting the mantissa and the adder/subtractor for rounding (and converting from negative to positive). This allows the circuit configuration to be simplified.

Moreover, since there is no delay in processing caused by these circuits (particularly shifters), processing speed can be increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a floating point arithmetic unit according to an embodiment of the present invention, and FIG. 2 is an adder/subtractor 31 shown in FIG.
Figure 3 shows the structure of the correction data supplied to the
Figure 4 is a diagram showing the format of floating point data, - Figure 5 is a block diagram of a conventional floating point arithmetic unit, and Figure 6 is a block diagram of a conventional floating point arithmetic unit. FIG. 3 is a diagram showing classification of calculation results of an adder/subtractor. 13, 36...subtractor, 14-16...selector,
17... Right shifter, 18.31... Adder/subtractor, 32
... Control circuit, 33... Leading zero digit detector (LZD detector), 34... Left shifter, 35... Adder. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 6 Arrow: irreleVant

Claims (2)

[Claims] (1) Addition or subtraction between normalized first and second floating point data consisting of an e-bit exponent part, an n-digit mantissa part with one digit of m bits, and a sign part indicating the sign of the same mantissa part A floating point arithmetic unit that performs normalized third floating point data and outputs normalized third floating point data, a first subtracter that calculates an exponent difference between exponent parts of the first and second floating point data; a selection means for selecting the exponent part of the floating point data having a larger exponent according to the subtraction result of the first subtracter; digit alignment means for aligning the digits of the mantissa parts of the first and second floating point data by shifting the first and second floating point data to the right by the difference in exponents; and a first adder/subtractor of n+g digits (g is the number of digits of the guard digit) that performs addition or subtraction between the mantissa parts of the second floating point data according to the first operation mode signal; A second adder/subtractor of n+g+1 digits converts the result of the same operation into a positive value when the result is negative, and rounds the result of the same operation when the result is not negative, and the result of the operation of the first adder/subtractor is transferred to one input and the second adder/subtractor. 1st digit to n+g-4
digit, all bits of the n+g digit, and correction data in which the upper m-1 bits of each of the n+g-3 digit to n+g-1 digit are 0 are used as the other input, and addition or subtraction between each input data is performed as the second input. a second adder/subtractor that performs operations according to the operation mode signal; a carry output from the most significant digit of the first adder/subtractor; all bits of the most significant digit of the operation result of the first adder/subtractor; and the lower 1
According to the most significant bit of each +g digit and the first calculation mode signal, the least significant bit and the 0th digit (
a control circuit that determines the contents of the most significant digit) and the second operation mode signal; a leading zero digit detector that detects the number of leading zero digits of the operation result of the second adder/subtractor; The operation result of the second adder/subtractor is shifted to the left by the number of leading zero digits detected by the detector and the mantissa part of the third floating point data is output.The input is n+g+1 digits and the output is n digits to the left. a shifter; an adder that adds 1 to the exponent of the exponent part selected by the selection means; and subtracts the number of leading zero digits detected by the leading zero detector from the addition result of the adder;
and a second subtracter that outputs the exponent part of the third floating point data. (2) The calculation result of the first adder/subtractor is supplied to the lower digit of one input of the second adder/subtractor, and 0 is supplied to the higher digit. floating point arithmetic unit.