JPH05167456A - Arithmetic operation circuit - Google Patents

Abstract

PURPOSE:To obtain a required arithmetic operation accuracy with small scale hardware configuration by providing a specific rounding circuit to implement rounding processing of symmetry in sign. CONSTITUTION:A rounding circuit 11 rounding data in N-bits of 2's complement form into data in (N-L) bits is provided with an N-bit adder (adder means) 12 and a data selector (output means) 13 which outputs L-bits bit pattern data (100...0) when a sign bit in the N-bit data indicates positive or 0 (0 or over) and outputs bit pattern data of L bits (011...1) when the sign bit indicates a negative data. In this case, N, L are both natural numbers and the relation of N>L is set. Then data in L bits (any bit pattern data) from the data selector 13 are adds 0s in (N-L) bits to a high-order at the adder 12 and the result is added to the N-bit data and rounded.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating point processor satisfying the IEEE format, an arithmetic circuit used for image data compression in a digital signal processing circuit, and more particularly, a floating point rounding process of 2's complement format, The present invention relates to an arithmetic circuit which handles data in a two's complement format suitable for normalization, multiplication or addition / subtraction.

[0002]

2. Description of the Related Art Conventionally, as an arithmetic circuit of this type, there is, for example, one disclosed in JP-A-1-227770. FIG. 7 shows the configuration thereof. The orthogonal transform arithmetic circuit 1 and the rounding ROM 2 are used as an orthogonal transformer 3, and the input N ₁ bit data is converted to N ₂ bit data by the orthogonal transform arithmetic circuit 1. After that, the N ₂ bit data is rounded by the ROM 2 to be rounded to (N ₂ −L) bits having a smaller number of bits than this.
In the rounding process, positive and negative symmetric rounding is performed so that the rounding is symmetrical with respect to 0.

There is also a floating point (IEEE format) normalization circuit as disclosed in Japanese Patent Laid-Open No. 3-117918. "Normalization" means to eliminate consecutive high-order invalid bits of the mantissa by a bit shift operation,
At the same time, the number of shifted bits is subtracted from the exponent part, and the significant bit in the mantissa part is moved to the higher order to prevent a precision loss during calculation. FIG. 8 shows the configuration, in which the mantissa part and the exponent part are input, the number of consecutive high-order invalid bits in the mantissa part is counted by the priority encoder 4, and the barrel shifter 5 is counted by the counted number of bits. Shifts the mantissa part to the upper direction (shift left). At the same time, the subtractor 6 subtracts the number of bits counted from the exponent.

With such a configuration, the significant bit of the mantissa part is moved to the higher order to prevent the digit loss during multiplication and addition / subtraction. At this time, if the mantissa part is shifted by the number of invalid bits, the subtraction result of the exponent part may cause underflow. In order to prevent this, a comparison function is added to the priority encoder 4 that counts the number of invalid bits in the mantissa, the number of invalid bits in the mantissa is compared with the number of bits in the exponent, and the smaller value is output. The barrel shifter 5 performs bit shift and the subtractor 6 performs subtraction.

Further, regarding floating-point multiplication and addition / subtraction processing, there is one shown in a user's manual "TMS320C30" (second generation digital signal processor) of Texas Instruments Japan, Inc. First, FIG. 9 shows a floating point multiplication process.
In the figure, a (man) indicates a mantissa part and a (exp) indicates an exponent part. First, in step (1), a 24-bit mantissa part is multiplied to obtain a 50-bit result c (man). Then, in step (2), the exponent part is added to obtain c (exp). A special case check is performed on the results of these multiplications and additions. As this check, first, in step (3), it is checked whether c (man) is zero in the extended precision format, and if it is zero, c (exp) is changed to − in step (7).
It is set to 128 and is expressed as zero. If it is not zero, normalization by shift processing is performed in steps (4) and (5). That is, when it is necessary to shift right by 1 bit, c (man) is shifted right by 1 bit in step (8), and 1 is added to c (exp). Also, if it is necessary to shift right by 2 bits, in step (9) c (man)
Is shifted right by 2 bits, and 2 is added to c (exp). If the result is already normalized, step
There is no shift as shown in (6).

Then, in step (10), c (man) is set to the extended precision floating point format by deleting the extra bits. Furthermore, in steps (11) to (18), c (e
Check for the special case of xp). In this check, when c (exp) overflows in the positive direction as in step (11), set c (exp) to the maximum positive number in the extended precision format and overflow in the negative direction. , C (exp) is set to the smallest negative number in extended precision format. On the other hand, if c (exp) underflows as shown in step (12), c (exp) is set to zero as shown in step (15). That is, c (man) =
0 and c (exp) =-128.

Next, FIG. 10 shows a flow chart of floating point addition processing. Here, signed data is assumed, and the case of floating-point subtraction is also applicable. First, in step (1), x (exp) is set to the larger one of the two exponents a (exp) and b (exp). here,
For simplicity of explanation, it is assumed that a (exp) ≦ b (exp). Then, in step (2), the difference is set by subtraction processing between these exponents. In step (3),
Regarding the two mantissas a (man) and b (man), the exponent is smaller, that is, a (man) is shifted rightward by d bits to align the mantissas. After the mantissas are aligned, addition processing is performed on the mantissas as shown in step (4).

Based on this addition result, steps (5)-
In (7), a special case of c (man) is tested. There are three in this test. First, in step (5) c (man)
Is zero, and in step (8), c (exp) is set to the minimum negative number, and is represented as zero. On the other hand, if c (man) has overflowed, c (man) is set to 1 in step (9).
Shift right by bits and add 1 to c (exp). In step (10) the result is normalized. Then step (11)
In (12), the special case of c (exp) is tested. If c (exp) causes a positive overflow, set c (exp) to the maximum positive number in the extended precision format, otherwise, set c (exp) to the extended precision. Set to the smallest negative value in the format.

[0009]

However, first, in the case of the rounding circuit disclosed in Japanese Patent Laid-Open No. 2-227770, the ROM 2 is rounded in order to perform positive and negative symmetric rounding so that the rounding is symmetrical with respect to 0. I am using it, and the hardware scale becomes large.

In the floating point normalization circuit disclosed in Japanese Patent Laid-Open No. 3-117918, underflow of the exponent part is prevented even though the underflow of the exponent part is prevented in the bit shift processing of the mantissa part. No mention is made of what happens when it occurs. Therefore, for example, when the exponent part underflows as a result of multiplication or addition / subtraction, even if the normalization circuit of the publication is used, the underflow is output as it is, causing a problem in calculation accuracy.

Further, in the case of the floating point multiplication process shown in FIG. 9, it is premised that the two input floating point data are normalized, so that the multiplication result is normalized to "0". Normalization can be performed by shifting "1" and "2" bits, but if an unnormalized numerical value is input, the multiplication result cannot be properly normalized. In addition, since the multiplication result is set to "0" only due to the occurrence of underflow in the exponent part, the calculation accuracy decreases.

In the case of the floating point addition process shown in FIG. 10, two input exponent parts are compared, the difference between them is calculated, and the exponent parts are small so that both exponent parts have the same value. The mantissa corresponding to one of them is bit-shifted in the lower direction. At this time, lower bits exceeding a predetermined number of bits are truncated, and then the mantissa is added. Since the extra low-order bits that have been shifted are truncated when aligning, the calculation error increases.

[0013]

According to a first aspect of the present invention, L bits (however, L is required) corresponding to a sign bit of N-bit (where N is a natural number) binary data of 2's complement format.
Is a natural number set to the relationship of L <N) of "100 ...
Output means for switching and outputting bit pattern data of "0" and "011 ... 1", and L-bit bit pattern data output from this output means is added to the lower L bits of the N-bit binary data. A rounding circuit including an adding means is provided to convert the input N-bit binary data into (N
-L) The data is rounded.

According to the second aspect of the present invention, the input of the M-bit mantissa part and the J-bit exponent part (where M and J are natural numbers) is set to K bits (where K is K <J). Minimum value Emin that can be represented by the exponent part of the generated natural number)
First subtracting means for subtracting from the J-bit exponent part,
Counting means for counting the number of bits until the first appearance of a bit different from the sign bit as viewed from the upper side of the input mantissa is compared with the output of the first subtracting means and the output of this counting means. The comparison output means for outputting the smaller one, the first shift means for shifting the input data of the mantissa part in the upper direction by the number of bits of the output value of the comparison output means, and the output value of the first subtraction means Means for converting a negative one of the above into a positive value, second shift means for shifting the input mantissa data in the lower direction by the number of bits of the output value of the converting means, and the input J bit Second subtraction means for subtracting the output value of the comparison output means from the exponent part of, and the output value of the first shift means and the second subtraction means when the output of the first subtraction means is 0 or more. Outputs the output value and is negative Sometimes, a two's complement type floating point normalization circuit comprising a switching means for outputting the output value of the second shift means and the minimum value Emin is provided, and an M-bit mantissa part and a J-bit exponent part are inputted. The M-bit mantissa part and the K-bit exponent part are output.

According to the third aspect of the present invention, L bits (where L is L <N are satisfied according to the sign bit of binary data of N bits (where N is a natural number) of 2's complement format. Set natural numbers) "100 ... 0" and "011
The output means for switching and outputting the bit pattern data of "1" and the first adding means for adding the lower L bits of the N-bit binary data with the L-bit bit pattern data output from the output means. A rounding circuit for rounding the binary data of the N-bit mantissa part that has been input to (NL) bits, a detecting means for detecting the presence or absence of a carry in the first adding means, and a carry case. Second addition means for adding "1" to the exponent part, shift means for shifting the output of the first addition means by 1 bit in the lower direction when a carry is present, and shift for this shift means when a carry is present. A 2's complement floating-point rounding circuit is provided, which includes a switching means for outputting the result and outputting the addition result of the first adding means when there is no carry.

According to the invention of claim 4, claim 2 or 3
The arithmetic circuit described above is provided with a multiplication means for calculating the product of two mantissa parts and an addition means for calculating the sum of two exponent parts, thereby forming a two's complement floating-point multiplication circuit.

Further, in the invention according to claim 5, the subtracting means for calculating the difference between the two input exponent parts and the larger one of the two exponent parts depending on the sign bit of the subtracted difference output. An exponent output switching means for outputting an exponent part, an absolute value calculating means for calculating an absolute value of the difference output, and any one of the two input mantissa parts of the data is output as a bit of an output value from the absolute value calculating means. A shift means for shifting in the lower direction by a few minutes, and L bits (however, L) depending on the sign bit of the binary data of 2's complement format (where N is a natural number) output from this shift means.
Is a natural number set to the relationship of L <N) of "100 ...
Output means for switching and outputting bit pattern data of "0" and "011 ... 1" and addition for adding the L bit bit pattern data output from the output means to the lower L bits of the N bit binary data. A rounding circuit for rounding the input N-bit binary data into (NL) -bit data, and an addition / subtraction unit for performing addition / subtraction between the output of the rounding circuit and the input two mantissa data. Is provided to provide a two's complement floating-point adder / subtractor circuit.

[0018]

According to the first aspect of the present invention, since the positive and negative symmetric rounding processing is performed by the predetermined two kinds of bit pattern data output means and addition means, a small-scale hardware configuration is used to eliminate the rounding deviation. It will be small, and the required calculation accuracy will be obtained.

Further, according to the second aspect of the present invention, in the floating point normalization processing, when the underflow is determined, not only the exponent part but also the remaining number of significant bits in the mantissa part are taken into consideration. Therefore, the underflow process is not unnecessarily performed, and the calculation accuracy can be improved.

According to the third aspect of the invention, since the rounding process of the mantissa part of the floating point data is performed in positive and negative symmetry using the rounding circuit according to the first aspect of the invention,
The calculation accuracy is improved.

Further, according to the invention described in claim 4, the normalization process according to the invention according to claim 2 and the rounding process of the mantissa part of the floating point multiplication result can be prevented as positively or negatively as possible. Since the floating-point rounding processing according to the third aspect of the present invention, which is performed symmetrically, is used, the calculation precision is high, and since such a normalization circuit is incorporated, it is possible to input an unnormalized input. Also can correctly normalize the multiplication result.

According to the fifth aspect of the invention, in the floating point addition / subtraction process, after the bit shift process of the mantissa part when aligning the exponent parts, the lower extra bits exceeding the predetermined number of bits are processed. Since the rounding circuit according to the first aspect of the present invention performs the positive / negative symmetrical rounding process, the calculation error is reduced and the calculation accuracy is improved.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the invention described in claim 1 will be described with reference to FIG. The present embodiment relates to a rounding circuit 11 that rounds N-bit data in 2's complement format into (NL) -bit data, and includes an N-bit adder (adding means) 12 and N-bit data. If the sign bit of is positive or 0 (0 or more), L-bit "100 ... 0" bit pattern data is output, and if the sign bit is negative, L-bit "011 ... 1" bit pattern data is output. And a data selector (output means) 13 for outputting data. Here, N and L are both natural numbers, and N> L is set. The L-bit data (any bit pattern data) output from the data selector 13 is added to the N-bit data by adding (N−L) -bit 0 to the higher order in the adder 12 and rounded. Be done.

In such a configuration, for example, N =
Taking L = 3 and rounding 6-bit data consisting of 3 bits after the decimal point into an integer, the rounding circuit 11 of the present embodiment can obtain rounding results as shown in Table 1. Becomes

[0025]

[Table 1]

As can be seen from this table, according to this embodiment, the bit pattern data of "100" is added to the lower L bits (= 3 bits) to be rounded when it is positive or 0, and when it is negative. By adding the bit pattern data "011" and truncating the data, the rounding process is realized with positive and negative symmetry centered on "0". As a result,
Rounding deviation at the final stage in signal processing becomes small,
The calculation accuracy is improved. Since the ROM is not required for such rounding processing, the circuit scale can be small.

Next, a second embodiment of the invention according to claim 1 will be described with reference to FIG. The same parts as those shown in the above-mentioned embodiment are designated by the same reference numerals. In the present embodiment, only "100 ... 0" is prepared as the L-bit bit pattern data, and "100 ... 0" or "011" depending on the sign bit in the N-bit data.
The gate circuit 14 includes L exclusive OR gates as an output means for generating and outputting bit pattern data "1".
In place of the data selector 13.

With the configuration of this embodiment, rounding processing similar to that of the above embodiment is performed. The L-bit bit pattern data to be prepared may be "011 ... 1" and the sign bit side may be inverted.

Next, an embodiment of the invention described in claim 2 will be described with reference to FIG. In this embodiment, a two's complement floating-point normalization circuit 15 which inputs an M-bit mantissa part and a J-bit exponent part for normalization and outputs an M-bit mantissa part and a K-bit exponent part 15 It is about. Here, M, L, and K are all natural numbers, and K <J is set.

First, a subtractor (first subtraction means) 16 for calculating the difference between the input J-bit exponent part and the minimum value Emin of the exponent part that can be expressed by a predetermined number of bits is provided. Further, a priority encoder (counting means) 17 is provided which counts and outputs the number of bits until a bit different from the sign bit is first found when viewed from the upper side of the mantissa part of the input M bits. The subtractor 16 and the priority encoder 17 are connected to a comparator 18 for comparing the outputs of the both, and the smaller one of the outputs of the subtractor 16 and the priority encoder 17 is selected according to the output of the comparator 18. A selector 19 for switching is provided. These comparators 18
The comparison output unit 20 is configured by the selector 19 and the selector 19. Further, there is provided a barrel shifter (first shift means) 21 for shifting the input mantissa data in the upper direction by the number of bits of the output value of the selector 19. Further, a subtractor (second subtraction means) 22 for subtracting the output value of the selector 19 from the input J-bit exponent part 22.
Is provided.

On the other hand, when the output value output from the subtractor 16 via the selector 19 is negative, there is provided a code conversion circuit (converting means) 23 for converting this into a positive value. A barrel shifter connected to the code conversion circuit 23 and shifting the input mantissa data in the lower direction by the number of bits of the output value of the code conversion circuit 23 (second
Shift means) 24 is provided. Further, the output value of the priority encoder 17 and the code conversion circuit 23
An underflow detection circuit 25 for detecting whether or not an underflow has occurred is provided by using the output value of and as a input.

Further, the outputs of the barrel shifters 24 and 21, the minimum value Emin, and the output of the subtractor 22 are selectively input to an overflow / underflow processing circuit 27 via a switching circuit (switching means) 26. The output of the underflow detection circuit 25 is directly input to the overflow / underflow processing circuit 27. Here, the changeover circuit 26 includes two changeover switches SW ₁ and SW ₂ provided for two systems, and when the sign bit is positive or 0 and 0 or more, the 0 terminal side is selected and the sign bit is negative. In the case of, the one terminal side is set to be selected. The 0 terminal side of the changeover switch SW ₁ is connected to the barrel shifter 21 side, and the 1 terminal side is connected to the barrel shifter 24 side. The 0 terminal side of the changeover switch SW ₂ is connected to the subtractor 22 side, and the 1 terminal side is connected to the minimum value Emin. Therefore, the subtractor 16
When the sign bit is 0 or more, the output value of the barrel shifter 21 and the output value of the subtractor 22 are output, and when the sign bit is negative, the output value of the barrel shifter 24 and the minimum value Emin are output.

The overflow / underflow processing circuit 27 sets and outputs predetermined data in the exponent part and the mantissa part when the exponent part exceeds the maximum value that can be expressed by a predetermined number of bits. On the other hand, when the underflow is detected by the underflow detection circuit 25, 0
Is set in the exponent part and the mantissa part and output.

The normalizing circuit 15 receives the M-bit mantissa part and the J-bit exponent part for normalization, and outputs the M-bit mantissa part and the K-bit (K <J) exponent part. This is suitable for normalizing multiplication and division results.

First, the priority encoder 1 determines the number of consecutive consecutive invalid bits of the input M-bit mantissa part.
Count at 7. That is, if the mantissa is positive, the number of consecutive bits of 0 until the first 1 appears from the upper part below the decimal point is counted, and if the mantissa is negative, 0 first appears. The number of consecutive 1 bits up to is counted.
At the same time, the subtracter 16 subtracts the minimum value Emin that can be represented by a predetermined number of bits K from the input J-bit exponent. As a result, the maximum shift amount when shifting the mantissa part for normalization is obtained. That is, if the mantissa part is bit-shifted beyond this value, an underflow will occur when the shift bit number is subtracted by the exponent part, and a valid value will be replaced with 0 unnecessarily, and the calculation accuracy will be reduced. This is to avoid this because it will deteriorate.

Next, the subtractor 16 is operated by the comparator 18.
Is compared with the output value of the priority encoder 17, and the selector 19 selects the smaller value.
To control. Then, the mantissa part is bit-shifted in the upper direction by the barrel shifter 21 by the number of bits of the output value of the selector 19. Further, the subtractor 22 subtracts the shifted number of bits from the exponent part.

In the present embodiment, as described above, the input bit number J is the output bit number K in the exponent part.
Therefore, the output of the subtracter 16 = sign bit may be negative. In such a case, conventionally, underflow was processed and 0 was output, but the normalization circuit 15 of the present embodiment performs the following processing to prevent occurrence of underflow as much as possible. The calculation accuracy is improved.

First, when the output of the subtractor 16 becomes negative, the sign conversion circuit 23 converts the value into a positive value and the barrel shifter 24 converts the value into a positive value. Bit shift to. As a result, the lower significant bits of the mantissa are lost to some extent by the bit shift in the lower direction, but unless all bits are lost,
Underflow does not occur. That is, assuming that the output value of the priority encoder 17 is x and the output value of the sign conversion circuit 23 is y, of the M bits below the decimal point of the mantissa part (the sign bit is omitted here for simplification of description), The lower significant bits are (Mx) bits. Therefore, in the case of (Mx)> y, an effective bit remains in the mantissa part, and therefore underflow does not occur. At this time,
The exponent part is output as the minimum value Emin. Also, (M-
When x) ≦ y, all effective bits in the mantissa part disappear, resulting in underflow. (M-x)> y above
The underflow detection circuit 25 determines whether or not (M−x) ≦ y.

When the output of the subtracter 16 is positive or zero, the output value of the barrel shifter 21 as the mantissa part and the output value of the subtracter 22 as the exponent part overflow or underflow by the switches SW ₁ and SW _2. Processing circuit 27
When the output of the subtractor 16 is negative, the output value of the barrel shifter 24 is output as the mantissa and the minimum value Emin is output as the exponent. Thereafter, the overflow / underflow processing circuit 27 outputs a positive maximum value or a negative minimum value in the case of overflow, and 0 in the case of underflow as the mantissa part and the exponent part.

An embodiment of the invention described in claim 3 will be described with reference to FIG. This embodiment relates to a floating point rounding circuit 31 of 2's complement format, and uses the rounding circuit 11 according to the above-mentioned invention for rounding the mantissa part with N-bit data. In addition, a circuit for processing the exponent part is added to the processing of the rounding circuit 11. First, an overflow detector (detection means) 32 for detecting the presence or absence of a carry in the adder (first addition means) 12 in the rounding circuit 11 is provided. Further, an adder (second adding means) 33 is provided for adding "1" to the exponent when the overflow detector 32 detects the presence of a carry in response to the input of the exponent. Further, there is provided a 1-bit shifter (shift means) 34 for shifting the output of the rounding circuit 11 (output of the adder 12) by 1 bit in the lower direction when such a carry is detected. This 1-bit shifter 34
There is provided a switch (switching means) SW _{3 in} which the 1-terminal side is connected to the output side of and the 0-terminal side is connected to the output side of the rounding circuit 11 without passing through the 1-bit shifter 34. This switch SW ₃ is switched according to the output of the overflow detector 32. When the overflow occurs, the 1 terminal side is selected, and when there is no overflow, it is 0.
The terminal side is set to be selected.

Therefore, as a result of the rounding processing of the mantissa part by the rounding circuit 11, when the overflow detector 32 detects that an overflow has occurred in the mantissa part, the adder 33 adds 1 to the input exponent part and outputs it. At the same time, the 1-bit shifter 34 outputs the mantissa data shifted by 1 bit in the lower direction. If there is no overflow, as described above, the output of the adder 12 of the rounding circuit 11 is directly output as the mantissa data.

As described above, according to this embodiment,
As a specific application of the rounding circuit 11 according to the described invention,
Floating point rounding can be performed with positive and negative symmetry,
The calculation accuracy is improved.

Further, an embodiment of the invention described in claim 4 will be described with reference to FIG. The present embodiment relates to a two's complement floating-point multiplication circuit 35, and specifically, FIG.
A multiplier (multiplication means) 36 for calculating the product of two mantissa parts 1 and 2 as the mantissa part input of the normalization circuit 15 as shown in FIG.
And an adder (adding means) 37 for calculating the sum of two exponents 1 and 2 as an exponent input, and a switching circuit 26 and an overflow / underflow processing circuit 27.
A floating point rounding circuit 31 as shown in FIG. 4 is provided between them.

In such a configuration, two floating point data (mantissa part 1 + exponent part 1, mantissa part 2 + exponent part 2)
Is input, the product of the mantissas is calculated by the multiplier 36,
At the same time, the sum of the exponents is calculated by the adder 37. After that, as described with reference to FIG. 3, the floating point normalization is performed by the normalization circuit 15, but finally, the overflow / underflow processing circuit 27 processes and outputs the data of the mantissa part 3 and the exponent part 3. Before that, rounding processing by the floating point rounding circuit 31 described in FIG. 4 is performed.

As a result, the floating-point multiplication result is normalized so that underflow is prevented as much as possible, and the mantissa part is rounded in positive and negative symmetry, resulting in high calculation accuracy. Further, according to the present embodiment, the multiplication circuit 35
Since the normalization circuit 15 is built in, the multiplication result can be correctly normalized even for an unnormalized input value.

Next, an embodiment of the invention described in claim 5 will be described with reference to FIG. The present embodiment relates to a two's complement floating point adder / subtractor circuit 38. First, a subtracter (subtracting means) 39 for calculating the difference between the input two exponent parts 1 and 2 is provided, and the two exponent parts 1 and 2 are provided according to the sign bit of the difference output subtracted by the subtractor 39. Two
A selector (exponential output switching means) 40 that outputs the larger exponent part 1 or 2 is provided. Also,
An absolute value calculator (absolute value calculating means) 41 for calculating the absolute value of the difference output from the subtractor 39 is provided, and the mantissa data input by the number of bits of the absolute value output of the absolute value calculator 41. Is provided with a barrel shifter (shift means) 42 for shifting in the lower direction. Here, only one of the two mantissa parts 1 and 2 is input to the barrel shifter 42 by the switch SW ₄ .

A rounding circuit 11 according to the present invention is provided on the output side of the barrel shifter 42, and is configured to round the output of the barrel shifter 42 to a predetermined number of bits smaller than that. ing. Also,
Such a mantissa processing system is provided with a switch SW ₅ for switching and outputting between the output from the rounding circuit 11 and the data that is input and does not pass through the rounding circuit 11 and is the mantissa 1 or 2. An adder / subtractor (adder / subtractor) 43 for performing addition and subtraction of is provided. Here, the switches SW ₄ and SW ₅ are configured such that the exponent part 1 <the exponent part 2
When the output of 9 is negative, it is switched to the 1 terminal side, and when the output of the subtractor 39 is positive or 0 by the exponent part 1 ≧ exponent part 2, it is switched to the 0 terminal side.

In such a configuration, two floating point data (mantissa part 1 + exponent part 1, mantissa part 2 + exponent part 2)
In order to calculate the sum or difference of, it is necessary to align the exponent parts 1 and 2 and then add and subtract the mantissa parts 1 and 2. Therefore, the difference between the exponents 1 and 2 is calculated by the subtractor 39, and the larger exponent 1 or 2 is output by the selector 40 according to the sign bit of the result. At the same time, the absolute value of the output of the subtractor 39 is calculated by the absolute value calculator 41 and output to the barrel shifter 42, and the mantissa part corresponding to the smaller exponent part is bit-shifted. After that, the rounding circuit 11 performs a rounding process of positive and negative symmetry on the lower-order extra bits exceeding the predetermined number of bits. In this way, align the exponents 1 and 2,
After rounding the mantissa part 1 or 2, the adder / subtractor 43 performs addition and subtraction of the two mantissa part data. After this, normalization processing may be performed to obtain an adder / subtractor output.

[0049]

According to the first aspect of the present invention, L <L depending on the sign bit of N-bit binary data in the 2's complement format.
L bits “100 ... 0” and “011 ...
Rounding including output means for switching and outputting bit pattern data of "1" and addition means for adding the L-bit bit pattern data output from the output means to the lower L bits of the N-bit binary data. With a circuit
Since the positive and negative symmetric rounding processing is performed, it is possible to reduce the rounding deviation with a small-scale hardware configuration, and thus it is possible to obtain the necessary calculation accuracy.

According to the second aspect of the present invention, K <for input of the M-bit mantissa part and the J-bit exponent part.
The minimum value Emi that can be represented by the K-bit exponent of the relationship J
first subtracting means for subtracting n from the J-bit exponent part, counting means for counting the number of bits until the first appearance of a bit different from the sign bit as seen from the upper side of the input mantissa part, The comparison output means for comparing the output of the first subtraction means and the output of the counting means and outputting the smaller one, and the input data of the mantissa part in the upper direction by the number of bits of the output value of the comparison output means. First shifting means for shifting, converting means for converting a negative value in the output value of the first subtracting means into a positive value, and input mantissa data by the number of bits of the output value of the converting means. When the output of the first subtracting means is 0 or more, the second shifting means for shifting only in the lower direction, the second subtracting means for subtracting the output value of the comparing and outputting means from the input J-bit exponent part are 0 or more. Sometimes the first shift hand 2 and the output value of the second subtraction means, and a switching means for outputting the output value of the second shift means and the minimum value Emin when the output value of the second subtraction means is negative. Is provided
Since the M-bit mantissa part and the J-bit exponent part are input and the M-bit mantissa part and the K-bit exponent part are output, when the underflow is determined in the floating point normalization process, Not only the exponent part but also the remaining number of significant bits in the mantissa part are taken into consideration, and the underflow process is not unnecessarily performed, and the calculation accuracy can be improved.

According to the third aspect of the invention, the rounding circuit according to the first aspect of the invention, the detecting means for detecting the presence / absence of a carry in the first adding means in the rounding circuit, and the carry presence When it is, the second which adds "1" to the exponent part
An adder, a shifter for shifting the output of the first adder by one bit in the lower direction when a carry is present, and a shift result of the shifter when a carry is present, and the shift result when the carry is not present. A 2's complement floating-point rounding circuit comprising switching means for outputting the addition result of the 1-adding means is provided, and rounding processing of the mantissa part of the floating-point data is performed by using the rounding circuit according to the present invention. Since the operations are performed symmetrically, the calculation accuracy can be improved.

According to the invention described in claim 4, in the arithmetic circuit according to claim 2 or 3, multiplication means for calculating a product of two mantissa parts and addition means for calculating a sum of two exponent parts. 3. The normalization process according to the present invention and the rounding process of the mantissa part are made positive and negative in order to prevent the occurrence of underflow in the floating-point multiplication result as much as possible. Since the floating-point rounding process according to the third aspect of the present invention, which is performed symmetrically, is used, the calculation precision can be made high, and such a normalization circuit is built in the multiplication circuit. For,
The multiplication result can be correctly normalized even for an unnormalized input.

Further, in the invention of claim 5, the subtracting means for calculating the difference between the two input exponents and the larger one of the two exponents depending on the sign bit of the subtracted difference output. An exponent output switching means for outputting an exponent part, an absolute value calculating means for calculating an absolute value of the difference output, and any one of the two input mantissa parts of the data is output as a bit of an output value from the absolute value calculating means. A shift means for shifting the lower direction by a few minutes, a rounding circuit according to the present invention, and an adder / subtractor means for adding / subtracting the output of the rounding circuit and the inputted two mantissa data are provided.
2. A floating-point addition / subtraction circuit of 2's complement format, wherein in the floating-point addition / subtraction process, after the bit shift process of the mantissa part when aligning the exponent parts, the lower extra bits exceeding the predetermined number of bits are set. Since the rounding circuit according to the invention performs positive and negative symmetric rounding processing, the calculation error can be reduced and the calculation accuracy can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the invention according to claim 1.

FIG. 2 is a block diagram showing a second embodiment of the invention according to claim 1;

FIG. 3 is a block diagram showing an embodiment of the invention described in claim 2.

FIG. 4 is a block diagram showing an embodiment of the invention according to claim 3;

FIG. 5 is a block diagram showing an embodiment of the invention described in claim 4.

FIG. 6 is a block diagram showing an embodiment of the invention described in claim 5;

FIG. 7 is a block diagram showing a conventional rounding circuit.

FIG. 8 is a block diagram showing a conventional floating point normalization device.

FIG. 9 is a flowchart showing a conventional floating point multiplication process.

FIG. 10 is a flowchart showing conventional floating point addition processing.

[Explanation of symbols]

 11 Rounding Circuit 12 Addition Means 13 and 14 Output Means 15 Floating Point Normalization Circuit 16 First Subtracting Means 17 Counting Means 20 Comparison Output Means 21 First Shift Means 22 Second Subtracting Means 24 Second Shift Means 26 Switching Means 31 Floating Point Rounding circuit 32 Detection means 33 Second addition means 34 Shift means 35 Floating point multiplication circuit 36 Multiplication means 37 Addition means 38 Floating point addition circuit 39 Subtraction means 40 Exponential output switching means 41 Absolute value calculation means 42 Shift means 43 Addition / subtraction means

Claims (5)

[Claims] 1. An L-bit (where L is a natural number set in a relationship of L <N) "100" according to a sign bit of N-bit (where N is a natural number) binary data in a two's complement format. Output means for switching and outputting bit pattern data of "0" and "011 ... 1", and L-bit bit pattern data output from this output means is added to the lower L bits of the N-bit binary data. And a rounding circuit including an adding means for rounding the input N-bit binary data to (NL) -bit data. 2. An exponent of K bits (where K is a natural number set in a relation of K <J) with respect to an input of an M-bit mantissa part and a J-bit exponent part (where M and J are natural numbers). A first subtraction means for subtracting the minimum value Emin that can be expressed by the part from the J-bit exponent part, and the number of bits until the first appearance of a bit different from the sign bit as seen from the upper side of the input mantissa part. Counting means for counting, comparison output means for comparing the output of the first subtraction means with the output of the counting means and outputting the smaller one, and input mantissa data of the output value of the comparison output means. First shift means for shifting in the upper direction by the number of bits, and converting means for converting a negative one of the output values of the first subtracting means into a positive value,
Second shift means for shifting the input mantissa data in the lower direction by the number of bits of the output value of the converting means, and subtracting the output value of the comparison output means from the input J-bit exponent portion. When the outputs of the second subtraction means and the first subtraction means are 0 or more, the output value of the first shift means and the output value of the second subtraction means are output, and when the outputs are negative, the output of the second shift means is output. Output value and the minimum value Emi
A floating-point normalization circuit of 2's complement format including switching means for outputting n is provided, and an M-bit mantissa part and a J-bit exponent part are input and an M-bit mantissa part and a K-bit exponent part are output. An arithmetic circuit characterized in that 3. An L-bit (where L is a natural number set in a relation of L <N) "100" according to a sign bit of N-bit (where N is a natural number) binary data in a two's complement format. Output means for switching and outputting bit pattern data of "0" and "011 ... 1" and L output from this output means for lower L bits of the N-bit binary data.
A rounding circuit for rounding the inputted binary data of the N-bit mantissa into (NL) -bit data, and a carry in the first adding means. Detecting means for detecting the presence / absence of the presence of a carry;
An adder, a shifter for shifting the output of the first adder by one bit in the lower direction when a carry is present, and a shift result of the shifter when a carry is present, and the shift result when the carry is not present. An arithmetic circuit characterized in that a floating-point rounding circuit of 2's complement format comprising switching means for outputting the addition result of the 1-adding means is provided. 4. A multiplication means for calculating a product of two mantissa parts and an addition means for calculating a sum of two exponent parts are provided,
The arithmetic circuit according to claim 2 or 3, wherein the arithmetic circuit is a two's complement floating point multiplication circuit. 5. A subtracting means for calculating a difference between two input exponents, and an exponential output switching for outputting a larger exponent of the two exponents according to a sign bit of the subtracted difference output. Means, an absolute value calculating means for calculating the absolute value of the difference output, and data of any of the two input mantissas, which are shifted in the lower direction by the number of bits of the output value from the absolute value calculating means. L according to the shift means and the sign bit of N-bit (where N is a natural number) binary data of 2's complement format output from the shift means.
Output means for switching and outputting bit pattern data of "100 ... 0" and "011 ... 1" of bits (where L is a natural number set to satisfy the relation of L <N) and the lower order of the N-bit binary data. The N-bit binary data which is input is composed of an addition means for adding the L-bit bit pattern data output from the output means to the L-bit (N-
A rounding circuit for rounding L) -bit data and addition / subtraction means for performing addition / subtraction of the output of the rounding circuit and the input two mantissa data are provided to form a two's complement floating-point addition / subtraction circuit. Characteristic arithmetic circuit.