JPH07121353A - Floating point adder / subtractor - Google Patents

Abstract

(57) [Summary] [Objective] An object of the present invention is to provide a floating-point number or subtraction device that executes addition and subtraction of floating-point numbers at high speed with a circuit configuration of a smaller scale. [Structure] A floating point adder / subtractor is mainly composed of a mantissa adder 11
It is composed of a 2's and 1's complementer 114 and a mantissa incrementer 117. Note that rounding and absolute value conversion of the mantissa part in floating point addition / subtraction occur exclusively in the following two cases. For true addition or true subtraction where the exponent difference is non-zero,
Mantissa adder 112 performs mantissa addition / subtraction and then mantissa incrementer 117 rounds exactly. In the case of true subtraction where the exponent difference is 0, the mantissa adder 112 calculates the mantissa difference, and when the mantissa difference is negative, the 2's complement unit configured by combining the 1's complementer 114 and the mantissa incrementer 117. To obtain the absolute value of the mantissa. [Effect] Since only one mantissa adder is required, the circuit scale is significantly reduced as compared with the conventional one.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating point addition / subtraction apparatus for calculating the sum or difference of floating point numbers in an information processing apparatus.

[0002]

2. Description of the Related Art In recent years, high-speed floating point arithmetic is required in many information processing fields such as digital signal processing and numerical calculation. Since the floating-point addition / subtraction has a larger processing amount than the integer addition / subtraction, the speedup of the floating-point addition / subtraction causes a large increase in the area and the number of elements. In a microprocessor incorporating the latest floating point arithmetic unit, one clock execution of floating point addition / subtraction is realized by adopting a pipeline processing technique.

Conventional floating point addition / subtraction devices are disclosed in, for example, Japanese Patent Laid-Open Nos. 1-302425 and 2-289006 (US Pat.
311296). Regarding floating point arithmetic, for example, ANSI / IEEE Std 754-1985 (The Institute of E
electrical and Electronics Engineers, Inc: "IEEE Stan
dard for Binary Floating-Point Arithmetic ", 1985,
Hereinafter, description will be made according to the IEEE754 standard), but this does not mean that the present invention depends on a specific standard or specification. Also, if the floating point number is a denormalized number or a special number, or if a floating point exception such as a high-order overflow occurs during addition or subtraction, an operation different from the following explanation will be caused, but it is out of the essence of the present invention. Therefore, it omits about such a special situation. In the detailed description, for example, only the situation in which addition / subtraction of normalized numbers is performed with rounding without overflow and a normalized number or the sum or difference of 0 is obtained will be described. Further, since the rounding algorithm is not an essential part of the present invention, only the most complex and frequently used nearest rounding (RN mode) among the four rounding modes defined in the IEEE754 standard will be described here. It is clear that the other three rounding schemes can be easily implemented by analogy with this description. Speaking of rounding below, it refers to the most recent rounding (RN mode rounding).

The following symbols are defined in the following description. The two floating point numbers to be added and subtracted are A and B, and the addition and subtraction result is R
It is represented by. The sign bit of the operand (augend or minuend) A is represented by s _A , the exponent part is represented by e _A , and the mantissa part is represented by m _A. Similarly, the sign bit, exponent part, and mantissa part of the operation number (addend or subtraction) B are respectively s _B , e _B , and m _B , and the sign bit, exponent part, and mantissa part of the sum or difference R are respectively s _R , Expressed as e _R and m _R. An overline for logical variables means logical negation. The symbol '*'
Don't care, that is, it is a logic that can be either 0 or 1. The symbols X, x, y, z, w, etc. are logical variables that represent either logical values 0 or 1.

The least significant bit within the range of mantissa precision (the number of significant digits) of the floating point number to be added and subtracted is a symbol
A bit that is one digit lower than the bit L is represented by a symbol G, a bit that is one digit less than the bit G is represented by a symbol R, and a logical sum of all bits of the mantissa that are lower than the bit R, that is, a sticky bit Is represented by the symbol S. The ones integer bit in the mantissa is the most significant bit of the mantissa
Bits that are one digit lower than the bit M are represented by the symbol U, and bits that are one digit higher than the bit M are represented by the symbol V. The relationship between specific bit positions for normalized numbers and the names assigned to them is shown in FIG. Here, the mantissa precision (the number of significant digits) is represented by n. According to the IEEE754 standard, M in the normalized number
Bits are hidden in the representation, but this is not the case in the internal representation in the floating-point adder / subtractor. The function max represents the larger number of its arguments.

The following terms will be defined in the following detailed description. A floating point number is composed of a sign, an exponent part, and a mantissa part. The term mantissa refers to the entire mantissa, including its hidden most significant bits. As shown in (Table 1), the terms of true addition and true subtraction are defined by the relationship between the codes s _A and s _B and the combination of addition and subtraction. Generally, the processing procedure of the floating-point adder / subtractor can be roughly divided into the case of true addition and the case of true subtraction.
In the case of true subtraction, addition and subtraction are performed respectively. Overflow of mantissa is defined as the sum of mantissas being 2 or more.
Digit cancellation is defined as the absolute value of the difference of the mantissa is less than 1. Shift means a logical shift with zero extension.
MSB and LSB mean the most significant bit and the least significant bit, respectively. For digit alignment, shift the mantissa part of the floating-point number with the smaller exponent to the right by the number of bits in the exponent difference, and digit loss is when the MSB of the mantissa is 0. Normalization is when digit loss occurs. This refers to the operation of left-shifting the mantissa until the MSB of the mantissa becomes 1, and subtracting the shifted number of bits from the exponent value.

[0007]

[Table 1]

A conventional floating point addition / subtraction device will be described below with reference to the drawings. (First Conventional Example) FIG. 3 is a block diagram of a floating point addition / subtraction device according to the first conventional example. In the figure, 301
Is a code generator, which generates a code of a true operation result from the code of two floating point numbers, the type of operation, the magnitude relationship of two exponents, and the magnitude relationship of two mantissas. An exponent subtractor 302 compares the magnitudes of two exponents and obtains an exponent difference. A first exponent selector 303 selects the larger of the two exponents. A right shift encoder 304 obtains the absolute value of the exponent difference and calculates the right shift amount in the pre-computation normalization. A mantissa comparator 305 determines the magnitude relationship between two mantissas. A first small mantissa selector 306 selects the mantissa part of the smaller floating-point number. A nibble level S-bit generator 307 calculates S bits in nibble units. Reference numerals 308, 309, and 310 denote an index difference 1 scanner, an index difference 0 scanner, and an index difference −1 scanner, which detect that the index difference is 1, 0, −1, respectively. Reference numeral 311 is an exponent difference selector for selecting whether the exponent difference is 1, 0, -1, or other. An exponential corrector 312 reduces the post-computation normalized bit number predicted in advance from the larger exponent. A left shift encoder 313 calculates the right shift amount in the pre-computation normalization by obtaining the absolute value of the index difference. Reference numerals 314 and 315 denote mantissa left and right shifters, which shift the mantissa left or right for digit alignment of both mantissas m _A and m _B or normalization before operation. A large mantissa selector 316 selects the mantissa part of the larger floating point number. 31
A second small mantissa selector 7 selects the mantissa part of the smaller floating point number. An S-bit generator 318 generates S-bits at the time of digit alignment. A rounding logic 319 corrects the least significant 1 bit of the provisionally rounded addition / subtraction result to realize accurate rounding. Reference numeral 320 denotes an exponent decrementer, which subtracts 1 from the exponent predicted value for post-computation normalization. Reference numeral 321 denotes an exponent incrementer, which adds 1 to the exponent predicted value for post-operation normalization. A second exponent selector 322 corrects the discrepancy of ± 1 in the exponent value prediction related to the post-computation normalization. 32
Reference numeral 3324 denotes a mantissa adder / subtractor which substantially adds and subtracts the mantissa part and rounds it. An addition / subtraction result selector 325 selects one of the two addition / subtraction results to which a rounding 1 is added to the correct bit position.

The operation of the first conventional floating-point addition / subtraction device configured as described above will be described. In this conventional example, floating-point numbers are added and subtracted by three-stage pipeline processing. This conventional example receives a floating point number A represented by an input (s _A , e _A , m _A ) and a floating point number _B represented by an input (s _B , e _B , m _B ), and adds or After the subtraction is performed, the sum (A + B) or difference (A−B) of the results represented by the outputs (s _R , e _R , m _R ) is output. A and B are normalized numbers, and 1 of the hidden MSBs of m _A and m _B has been added in advance.
The outline of the three-stage pipeline processing will be described below. <1st stage> ・ Compare the magnitude of A and B by the exponent part.

If the exponent difference is 0, the mantissa part is used to compare the magnitudes of A and B. • Predict the number of bits with precision loss when the exponent difference is 1, 0, −1 and true subtraction.・ Determine the sign of the result based on the sign of the two floating point numbers, the magnitude relationship, and the type of operation. <2nd stage> ・ Based on the precision cancellation, the mantissa is normalized or aligned before calculation.

When the index difference is 1, 0, −1 and true subtraction, the index value is adjusted based on the precision loss prediction. <Third stage> -Substantially add and subtract mantissa and round. -Corrects only one bit and then normalizes it to correct the exponent and mantissa.

In the case where the floating point numbers A and B are added and subtracted according to this conventional example, the specific operation will be briefly described below.
Occurrence of overflow of the mantissa can be determined by setting the V bit of the sum calculated by the first mantissa adder / subtractor 323 to 1. Prediction of the number of precision loss bits in the left shift encoder 313 causes a prediction error of 1 bit at the maximum. Therefore, when the prediction fails, the addition / subtraction result selector 325 and the exponent adjusters 320 to 322
1-bit correction of the exponent part and the mantissa part is carried out respectively. Calculating index difference (e _A -e _B) in the <First stage> (1.1) Index subtractor 302. (1.2) The right shift encoder 304 calculates the absolute value of the index difference | e _A −e _B |. (1.3) First index selector 303 based on the index comparison result
Selects the larger of e _A and e _B , and outputs max (e _A , e _B ). (1.4) The mantissa comparator 305 compares the magnitudes of both mantissas m _A and m _B. (1.5) The code generator 301 determines the resulting code s _R based on (Table 2).

[0013]

[Table 2]

(1.6) The index difference 1 scanner 308, the index difference 0 scanner 309, and the index difference −1 scanner 310 detect that the index difference is 1, 0, −1, respectively. (1.7) The exponent difference selector 311 selects whether the exponent difference is 1, 0, −1 or any other. (1.8) The first small mantissa selector 306 selects the mantissa part having the smaller exponent. If the two exponent values are equal, the first small mantissa selector 306 may select which mantissa part. (1.9) The nibble level S-bit generator 307 generates S bits in nibble units. <Second stage> (2.1) The left shift encoder 313 scans the high-order bits of both mantissas m _A and m _B , and predicts the number of digits to be lost after the mantissa part subtraction according to the exponent difference −1, 0, 1. To do. (2.2) The first mantissa left / right shifter 314 shifts the mantissa m _A left or right as follows. If the absolute value of the exponent difference is greater than 1, and the exponent e _A is less than the exponent e _B , the mantissa m _A
Is shifted to the right by the number of bits of the absolute value of the exponent difference (digit matching). If the exponential difference is 1, 0 or -1,
The mantissa m _A is shifted to the left by the predicted number of precision loss bits (pre-normalization). This output is represented by m _A '. (2.3) The second mantissa left / right shifter 315 shifts the mantissa m _B left or right as follows. Mandatory mantissa m _B if exponent e _B is less than exponent e _A when absolute value of exponent difference is greater than 1
Is shifted to the right by the number of bits of the absolute value of the exponent difference (digit matching). If the exponential difference is 1, 0 or -1,
The mantissa m _B is shifted to the left by the predicted number of precision loss bits (pre-operation normalization). This output is represented by m _B '. (2.4) The S bit generator 318 determines the actual S bit from the nibble level S bits. (2.5) The rounding logic 319 adjusts the lower bit of the mantissa adder / subtractor according to the value of the S bit or the like. (2.6) The exponent corrector 312 subtracts the number of precision loss bits from the value max (e _A , e _B ). This output is represented by e _norm . (2.7) Large mantissa selector 316 of the two mantissa parts m _A 'and m _B '
Selects the mantissa with the larger exponent and outputs it as m _l . When the two exponent values e _A and e _B are equal, the larger of the two mantissas is output as m _{l according} to the mantissa comparison result. (2.8) Of the two mantissa parts m _A 'and m _B ', the second mantissa selector 317 selects the mantissa part with the smaller exponent and selects it as m _s
Output as. When the two exponent values e _A and e _B are equal, the smaller of the two mantissas is output as m _{s according} to the mantissa comparison result. <Third stage> (3.1) The first mantissa adder / subtractor 323 rounds by adding m _l and m _s ' for true addition and 1 for rounding when mantissa upper overflow does not occur. , M for true subtraction
At the same time as subtracting m _s ' from _l , rounding is performed by adding 1 for rounding when no loss of 1-bit digits occurs. (3.2) By the second mantissa adder / subtractor 324, in the case of true addition, m _l and m _s ' and 1 for rounding when mantissa upper overflow is assumed to be added at the same time for rounding and true subtraction. Case m _l
When m _s ' is subtracted from 1 and a 1-bit precision loss occurs, 1 is added for rounding and rounding is performed. (3.3) In the addition / subtraction result selector 325, the addition / subtraction result obtained by the first mantissa adder / subtractor 323 or the addition / subtraction obtained by the second mantissa adder / subtractor 324 is determined depending on whether the mantissa higher-order overflow or 1-bit precision loss has occurred. Select the result or one of those values shifted left or right by one bit. (3.4) In the exponent decrementer 320, subtract 1 from e _norm . (3.5) In the exponent incrementer 321, add 1 to e _norm . (3.6) In the second exponent selector 322, a value e _norm +1 or e _norm −1 or e _norm −1 or e _norm −1 or Select e _norm and _call this value e _R. (Second Conventional Example) FIG. 4 is a block diagram of a floating point addition / subtraction device in the second conventional example. In the figure, reference numeral 401 denotes a code generator, which generates a temporary operation result code from the relationship between two floating-point number codes, operation types, and two exponents. Reference numeral 402 denotes an exponent subtractor, which compares the magnitude of two exponents and obtains an exponent difference. A first index selector 403 selects the larger of the two indexes. Reference numeral 404 is an exponent difference absolute value converter, which calculates the absolute value of the exponent difference. A large mantissa selector 405 selects the mantissa part of the larger floating point number. A small mantissa selector 406 selects the mantissa part of the smaller floating point number. A mantissa right shifter 407 aligns the digits of the mantissa part of the smaller floating-point number. 408
Is an S-bit generator that generates S-bits when aligning digits.
A sign inverter 409 determines the sign of the true operation result from the comparison of the magnitudes of two mantissas. An exponent decrementer 410 subtracts 1 from the exponent predicted value for post-computation normalization. 411
Is an exponent incrementer, which is 1 for the exponent prediction value for post-operation normalization
Add. Reference numeral 412 is a second exponent selector which corrects a discrepancy of ± 1 in exponent value prediction related to post-computation normalization.
A rounding logic 413 controls the carry input for rounding according to the value of the S bit or the mantissa lower bit. Reference numerals 414 and 415 denote first and second mantissa adder / subtractors, which substantially add and subtract the mantissa part and round it. Reference numeral 416 denotes an addition / subtraction result selector which selects which of the two addition / subtraction results is added with a rounding 1 at the correct bit position, or selects the absolute value of the mantissa difference in the case of true subtraction. A rounding corrector 417 corrects the least significant 1 bit of the provisionally rounded addition / subtraction result to realize accurate rounding. Reference numeral 418 is an exponent corrector, which subtracts the post-computation normalization correction value from the exponent value. Reference numeral 419 is a leading one detector, which detects the number of bits in which the mantissa difference is missed in the case of true subtraction. 420
Is a mantissa left shifter, which normalizes the mantissa part when a digit loss occurs.

The operation of the conventional example thus constructed will be described below. In this conventional example, floating-point numbers are added and subtracted by three-stage pipeline processing. In this conventional example, input (s
_A floating point number A represented by _A , e _A , m _A ) and a floating point number _B represented by input (s _B , e _B , m _B ) are received, and after addition or subtraction thereof, output ( The sum (A + B) or difference (A−B) of the results represented by s _R , e _R , m _R ) is output. A and B are normalized numbers, and 1 of the hidden MSBs of m _A and m _B has been added in advance. The outline of the three-stage pipeline processing will be described below. <1st stage> -Compare the magnitudes of A and B by the exponent part and align the digit of the smaller mantissa part.

If the subtraction is true and the exponent difference is not 0, the sign of the result is determined. <Second stage> -Substantially adding and subtracting mantissa and rounding. In the case of true subtraction and if the exponent difference is 0, the final sign is determined by the mantissa magnitude judgment. <Third stage> ・ If a digit is lost, the mantissa part and the exponent part are normalized.

In the case where the floating point numbers A and B are added and subtracted according to the conventional example, the specific operation will be briefly described below.
Occurrence of overflow of the mantissa can be determined by setting the V bit of the sum calculated by the first mantissa adder / subtractor 414 to 1. Calculating index difference (e _A -e _B) in the <First stage> (1.1) Index subtractor 402. (1.2) The absolute value of the index difference | e _A −e _B | is calculated in the index difference absolute value converter 404. (1.3) First index selector 403 based on the index comparison result
Selects the larger of e _A and e _B , and outputs max (e _A , e _B ). (1.4) The code generator 401 determines a temporary code based on (Table 2). (1.5) Of the two mantissa parts m _A and m _B , the mantissa part with the larger exponent is selected by the large mantissa selector 405, and this is _designated as m _l . If the two exponent values e _A and e _B are equal, the large mantissa selector 4
05 may select any mantissa part. (1.6) Of the two mantissa parts m _A and m _B , the mantissa part with the smaller exponent is selected by the small mantissa selector 406, and this is designated as m _s . If the two exponent values e _A and e _B are equal, the fractional mantissa selector 4
06 selects a different one from the large mantissa selector 405. (1.7) The mantissa right shifter 407 shifts m _s to the right | e _A −e _B | bit. This is called digit alignment, representing a digit alignment has been m _s in m _s'. (1.8) The S bit generator 408 takes the logical sum of all the bits spilled to the right of the R bits of the mantissa at the time of the above digit alignment and sets this as the S bit. <Second stage> (2.1) The rounding logic 413 adjusts the lower bit of the mantissa adder / subtractor according to the value of the S bit or the like. (2.2) The first mantissa adder / subtractor 414 simultaneously performs mantissa addition / subtraction and rounding. 1 for rounding when true addition and m _l and m _s ' and mantissa upper overflow do not occur
Are added at the same time and rounded. If true subtraction and the exponent difference is not 0, m _s ' is subtracted from m _l, and at the same time, rounding is performed by adding 1 for rounding _assuming that no 1-bit precision loss occurs. If true subtraction and exponent difference is 0, m _l to m _s '
Reduce. (2.3) The second mantissa adder / subtractor 415 simultaneously performs addition and subtraction of the mantissa and rounding. In the case of true addition, m _l and m _s ' and 1 for rounding when mantissa upper overflow is assumed to occur are added together and rounded. When true subtraction and exponent difference are not 0, m _s ' is subtracted from m _l, and at the same time, rounding is performed by adding 1 for rounding when 1-bit precision loss occurs. If true subtraction and exponent difference is 0, then subtract m _l from m _s ′. (2.4) The addition / subtraction result selector 416 selects the correct one of the addition / subtraction results obtained by the first mantissa adder / subtractor 414 and the second mantissa adder / subtractor 415. If true subtraction and exponent difference is 0, choose the one with positive result. Except when true subtraction and exponent difference is 0, the result of the above two additions and subtractions or the value obtained by shifting those values by 1 bit to the left or right is determined according to whether the mantissa upper overflow or 1-bit precision loss occurs. Choose the right one. (2.5) In the exponent decrementer 410, the value max (e _A , e _B ) becomes 1
Reduce. (2.6) In the exponent incrementer 411, 1 is added to the value max (e _A , e _B ). (2.7) In the second exponent selector 412, the value max (e _A , e _B ) +1 for the mantissa upper overflow, the 1-bit precision loss, or neither. Or max (e _A , e _B ) −1 or max
Select (e _A , e _B ). (2.8) The rounding corrector 417 corrects the L bit of the addition / subtraction result for accurate rounding. (2.9) The sign inverter 409 uses the second mantissa adder / subtractor 415
If the difference obtained in step 1 is negative, the sign determined in the first stage is inverted, otherwise the sign determined in the first stage is passed through, and this is designated as s _R. <Third stage> (3.1) The leading 1 detector 419 scans to the right from the M bits of the rounded sum to search for the bit position where bit 1 first appears, and finds the distance between the bit position and the M bit. Two
Encode to a base number. In true addition, this distance is zero. (3.2) The mantissa left shifter 420 adjusts the mantissa part so that the M bits of the result become 1 by shifting the addition / subtraction result to the left by the number of bits obtained by the preceding 1 detector 419. The shifted mantissa is m _R. In true addition, the M bits of the mantissa part are already 1, so they are not shifted. (3.3) In the exponent corrector 418, the difference obtained by subtracting the encoded left shift number from the corrected exponent part is taken as e _R. In true addition, 0 is subtracted from the encoded left shift number. (End) As described above, the conventional floating-point adder / subtractor is provided with the first mantissa adder / subtractor and the second mantissa adder / subtractor in order to perform rounding correction simultaneously with addition / subtraction of the mantissa part. These two mantissa adder / subtractors correspond to the presence or absence of upper digit overflow in the case of true addition, and the presence or absence of digit cancellation in the case of true subtraction where the exponent difference is not 0.
When the difference between the exponents is 0 in true subtraction, it is possible to deal with the positive or negative sign of the subtraction result.

[0018]

However, the conventional floating point adder / subtractor has two mantissa adder / subtractors which generally require a large circuit scale, and therefore has a problem that the amount of hardware becomes very large. In addition, there is a problem that the processing speed becomes slow due to the large circuit scale.

In view of the above problems, it is an object of the present invention to provide a novel floating-point addition / subtraction device which has performance equivalent to that of a conventional floating-point addition / subtraction device but requires less hardware.

[0020]

In order to solve the above-mentioned problems, the floating-point addition / subtraction device of the present invention selects the mantissa part of the two floating-point numbers having the smaller exponent, and if the exponents are the same. The small mantissa selecting means for selecting one mantissa part, the large mantissa selecting means for selecting a mantissa part of the two floating point numbers different from the small mantissa selecting means, and the output of the small mantissa selecting means are two floating point numbers. Digit alignment means that logically shifts to the lower side (hereinafter referred to as right) by the absolute value of the exponential difference of numbers (hereinafter referred to as digit matching) and positive numbers are added to positive numbers, negative numbers are subtracted from positive numbers, or negative numbers are negative numbers. When adding or subtracting a positive number from a negative number (hereinafter referred to as true addition),
When adding the digit-matched mantissa value to the output of the large mantissa selecting means, adding a negative number to a positive number, subtracting a positive number from a positive number, or adding a positive number to a negative number or subtracting a negative number from a negative number (hereinafter, true subtraction And a mantissa adding / subtracting means for subtracting the digit-matched mantissa value from the output of the large mantissa selecting means,
If the sum output from the mantissa adder / subtractor causes upper overflow, the sum is shifted right by 1 bit, and if the difference causes a 1-bit precision loss, the difference is shifted left by 1 bit, and otherwise left and right are passed through. 1-bit shift means, mantissa bit inverting means for inverting the output bit by bit if the output of the left-right 1-bit shift means is negative, and passing through otherwise, digit-aligned mantissa value and left-right 1-bit shift means Rounding correction means for determining the rounding logic based on the output of the above, and if the addend / subtraction result is negative, add 1 for 2's complement to the output of the mantissa bit inverting means, and add 1 for rounding in the rounding correction means. A mantissa increment means for adding 1 to the output of the mantissa bit inverting means if it is determined to do so, and passing it through otherwise.

The mantissa adder / subtracter is digit-matched with first mantissa bit inverting means for passing the digit-matched mantissa value through in the case of true addition and inverting each bit in the case of true subtraction. Carry input generating means for generating a carry input for two's complementation based on the mantissa value, the output of the large mantissa selecting means and the output of the first mantissa bit inverting means in the case of true addition, and In the case of true subtraction, in addition to these, mantissa adding means for adding the carry input may be included.

Further, the mantissa adder / subtractor means passes through the output of the large mantissa selection means in the case of true addition, and inverts bit by bit in the case of true subtraction, and the mantissa selection means. Carry input generating means for generating a carry input for two's complementing based on the output of, and in the case of true addition, the output of the first mantissa bit inverting means and the mantissa value aligned with the digit are added, In the case of true subtraction, in addition to these, mantissa adding means for adding the carry input may be included.

[0023]

The floating point adder / subtractor according to the present invention has the above-described structure, and in the case of true addition or when the exponent difference is not 0 in true subtraction, the floating point having a smaller exponent is selected by the small mantissa selecting means and the digit aligning means. The mantissa part of the decimal point number is aligned, the mantissa part of the floating point number having the larger exponent is selected by the large mantissa selecting means, and the result of addition or subtraction of the mantissa part by the mantissa adding / subtracting means is shifted to the left or right by 1 bit. To normalize the overflow or 1-bit precision loss, and add 1 for rounding if required by the mantissa incrementer according to the rounding correction logic determined by the rounding corrector.

When the subtraction is true and the exponent difference is 0, the small mantissa selecting means and the large mantissa selecting means select different mantissa parts of the floating point numbers, and the mantissa adder / subtracter means select the large mantissa. The output of the small mantissa selecting means is subtracted from the output of the selecting means, the one's complement of the difference is obtained by the mantissa bit inverting means, and the two's complement of the difference is obtained by the mantissa incrementing means. To the one's complement of the difference to find
Add one to allow the sum or difference of correctly rounded floating point numbers to be calculated.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of the floating point addition / subtraction device of this embodiment. In the figure, reference numeral 101 denotes a code generator, which generates a temporary code of a calculation result from the relationship between the codes of two floating point numbers, the type of calculation, and the magnitude of two exponents.

Reference numeral 102 denotes an exponent subtractor, which compares the magnitude of two exponents and obtains the exponent difference. An index selector 103 selects the larger of the two indexes. An exponent difference absolute value conversion unit 104 obtains the absolute value of the exponent difference. A large mantissa selector 105 selects the mantissa part of the larger floating point number. A small mantissa selector 106 selects the mantissa part of the smaller floating point number.

Reference numeral 107 is a mantissa right shifter, which aligns the digits of the mantissa part of the smaller floating point number. Reference numeral 108 denotes an S bit generator, which generates S bits at the time of digit alignment. Reference numeral 109 denotes a first mantissa bit inverter, which takes the 1's complement of the mantissa part of the smaller floating-point number in the case of true subtraction. Reference numeral 110 is a sign inverter, which determines the sign of the true operation result from the magnitude comparison of two mantissas.

Reference numeral 111 is an exponent increase / decrease unit, which adds or subtracts 1 to the exponent value. Reference numeral 112 is a mantissa adder, which substantially adds and subtracts the mantissa part. 113 is a left and right 1-bit shifter,
1 to the left or right of the mantissa part addition / subtraction result based on (Table 3)
Bit shift. Reference numeral 114 denotes a second mantissa bit inverter, which takes the 1's complement of the negative mantissa subtraction result.

A rounding correction unit 115 determines the rounding correction logic of the mantissa addition / subtraction result based on (Table 4). An exponent corrector 116 subtracts the post-computation normalization correction value from the exponent value. Reference numeral 117 denotes a mantissa incrementer, which generates a two's complement of the negative mantissa subtraction result or adds 1 to round the positive mantissa subtraction result.

Reference numeral 118 is a leading one detector, which detects the number of bits in which the mantissa difference is missed in the case of true subtraction. A mantissa left shifter 119 normalizes the mantissa part when a digit loss occurs. The operation of the floating point addition / subtraction device according to the embodiment of the present invention configured as described above will be described below. The floating-point addition / subtraction device of this embodiment performs addition / subtraction of floating-point numbers by a three-stage pipeline process. This example is input
Floating-point number A represented by (s _A , e _A , m _A ) and input (s _B , e _B , m _B )
Receives the floating-point number B represented by and outputs the sum (A + B) or difference (A-B) of the result represented by (s _R , e _R , m _R ) after adding or subtracting these . A and B are normalized numbers, and 1 of the hidden MSBs of m _A and m _B has been added in advance. The outline of the three-stage pipeline processing will be described below. <1st stage> -Compare the magnitudes of A and B by the exponent part and align the digit of the smaller mantissa part.

If the exponent difference is not 0 in true subtraction, the sign of the result is determined. <Second stage> -Substantially adding and subtracting the mantissa part. In the case of true subtraction and if the exponent difference is 0, the final sign is determined by the mantissa magnitude judgment. <Third stage> • Round the mantissa part. If the difference in the mantissa is negative, the two's complement is taken.

When the digit is lost, the mantissa part and the exponent part are normalized. When the floating point numbers A and B are added and subtracted according to the present embodiment, the specific operation will be described below. Occurrence of the mantissa higher overflow occurs in the sum calculated by the mantissa adder 112 in the case of true addition.
It can be determined by setting the V bit to 1. The third stage does not substantially operate in the case of true addition, and the sign, exponent part, and mantissa part pass through the third stage. The series of processing in the third stage of the pipeline is generally called post-operation normalization. Calculating index difference (e _A -e _B) in the <First stage> (1.1) Index subtractor 102. (1.2) The absolute value of the index difference | e _A −e _B | is calculated in the index difference absolute value converter 104. (1.3) Based on the index comparison result, the index selector 103
Write Select larger of e _A and e _B, and outputs the _{max (e A, e B)} . (1.4) The code generator 101 determines a temporary code based on (Table 2). (1.5) Of the two mantissa parts m _A and m _B , the mantissa part with the larger exponent is selected by the large mantissa selector 105, and this is designated as m _s . If the two exponent values e _A and e _B are equal, the large mantissa selector 1
05 may select any mantissa part. (1.6) Of the two mantissa parts m _A and m _B , the mantissa part with the smaller exponent is selected by the small mantissa selector 106, and this is _designated as m _l . If the two exponent values e _A and e _B are equal, the fractional mantissa selector 1
06 selects a different one from the large mantissa selector 105. (1.7) The mantissa right shifter 107 shifts m _s to the right | e _A −e _B | bit. This is called digit alignment, representing a digit alignment has been m _s in m _s'. (1.8) The S-bit generator 108 takes the logical sum of all the bits spilled to the right of the R bits of the mantissa at the time of the digit alignment, and sets this as the S bit. (1.9) In the first mantissa bit inverter 109, m _s ′ is passed through in the case of true addition, and m _s ′ is bit-inverted in the case of true subtraction. <Second stage> (2.1) adds the output and carry input of m _l and first mantissa bit inverter 109 by the mantissa adder 112. This carry input is for making the two's complement of the subtraction in the case of true subtraction, and adds the S bit inversion to the R bit in the case of true subtraction. (2.2) Based on (Table 3), in the left and right 1-bit shifter 113, the sum is shifted to the right by 1 bit when the sum causes the mantissa to overflow, and the difference is set to 1 when the difference causes a 1-bit precision loss.
Shift left by a bit, otherwise pass through. (2.3) Based on (Table 3), the exponent adjuster 111 increases max (e _A , e _B ) by 1 when the sum causes the mantissa to overflow, and max (e _A , e _B ) when the difference causes one-digit loss. Decrease _A , e _B ) by 1, otherwise let go through. (2.4) The rounding corrector 115 determines the increment logic by rounding based on (Table 4). (2.5) If the difference becomes negative in the case of true subtraction, the second mantissa bit inverter 114 bit-inverts the mantissa and otherwise passes it through. (2.6) If the difference becomes negative in the case of true subtraction The sign inverter 110 inverts the sign determined in the first stage, and otherwise passes it through. _Let this be s _R. <Third stage> (3.1) Mantissa incrementer 117 adds 1 for 2's complement to the mantissa addition / subtraction result when the difference becomes negative in the case of true subtraction, and otherwise rounds the mantissa addition / subtraction result Add value. (3.2) The leading one detector 118 scans to the right of the difference M bits to search for the bit position where the bit 1 first appears, and encodes the distance between the bit position and the M bit into a binary number. In true addition, this distance is zero. (3.3) The mantissa left shifter 119 shifts the difference to the left by the number of bits obtained by the preceding 1 detector 118, thereby reducing the difference.
Adjust the mantissa so that the M bit is 1. The shifted mantissa is m _R. In true addition, the M bits of the mantissa part are already 1, so they are not shifted. (3.4) In the exponent corrector 116, the difference obtained by subtracting the encoded left shift number from the corrected exponent part is taken as e _R. In true addition, 0 is subtracted from the encoded left shift number. (the end)

[0033]

[Table 3]

[0034]

[Table 4]

In the above example, the two's complementation of the subtrahend in true subtraction is further considered. The digits of the subtraction m _s are aligned and then bit-inverted by the first mantissa bit inverter 109. Further subtraction and subtraction for subtraction
it is necessary to add the three parties of 1 in the LSB of m _s '1's complement and subtrahend m _s'. That is, in order to take the 2's complement of the subtraction m _s ', 1 must be added to the LSB of its 1's complement. The problem is that some of the lower bits are lost because the divisors have been aligned. For this reason, it is not possible to add one to the LSB of the one's complement of the digit-matched divisor m _s '.

This problem can be solved by using the S bit of the reduction. The mechanism of true subtraction in the mantissa part is shown in FIGS. 5 to 8 and will be described along with it. 5, minuend m _l
Is a normalized positive number, and the subtraction m _s ' is a positive number that has already been aligned and shows a virtual spill bit to the right of its L bit, and these have actually disappeared. Information.

First, the 1's complement of the subtraction m _s 'is taken, and 1 is virtually added to the LSB of the subtraction m _s ' to obtain the 2's complement (FIG. 6).
Although you can't actually add 1 to the virtual LSB,
As a result of performing the virtual addition of 1, it is possible to determine whether or not the carry by it propagates to the actual LSB. This real LSB is assumed to be R bits here. When the carry propagates from the virtual LSB to the R bit, all digits z ₃ z ₄ ... z _r spilled to the right from the L bit of the subtraction m _s ' when digit alignment is 1 inversion of z _r Limited to.

[0038]

[Equation 1]

Therefore, z ₃ z ₄・ ・ ・ z _r ＝ 00 ・ ・ ・ 0 As shown in FIG. 7, the logical sum of all z _i (i = 3,4, ..., r−1, r) is S. Therefore, S = 0, so if 1 is added to the actual LSB only when S is 0, the correct complemented 2's complement of the divisor can be obtained. This condition is equivalent to adding the logical NOT of S to the actual LSB (Fig. 7). After all, it can be seen that the logical NOT of S should be added to the R bit (Fig. 8).

In this embodiment, since processing is carried out by a three-stage pipeline, the processing proceeds while synchronizing the sign / exponent part / mantissa part of the floating point number for each pipeline stage as described in the above operation. . Several combinations of timings for processing the three parts of the sign, exponent part, and mantissa part in each stage of the pipeline processing are conceivable in addition to the above. However, regarding the present invention, the processing timings in this embodiment and each stage thereof will be described. There is essentially no difference from the modified version of this embodiment. In this embodiment, the structure was designed with the intention that the circuit delays of the respective stages of the pipeline are as uniform as possible, but there may be different stage divisions according to other circuit configuration methods. The number of pipeline stages does not necessarily have to be 3, and the pipeline configuration of this embodiment is merely one implementation example of the algorithm of the present invention.

Several other modified embodiments having the same function as this embodiment can be considered. Next, a description of some of the changes will be added. There are several options for the circuit configuration of the index adjuster 111, as shown in FIG. In the present embodiment, the index adjuster 111 shown in FIG. 9 (a) is configured in detail as shown in FIGS. 9 (b) to 9 (d).

The index adjuster of FIG. 9 (b) has a simple structure in which an incrementer 602 and a decrementer 603 are connected in series. Figure 9
The exponent adjuster of (c) has a configuration in which bit inverters 604 and 606 are connected in series before and after the incrementer 605. Exponentially
When adding 1, the bit inverters 604 and 606 are passed through and the incrementer 605 adds 1. When subtracting 1 from the exponent, the bit inverters 604 and 606 invert the bits and the incrementer 605 adds 1. When the exponent value is not changed, the bit inverters 604 and 606 and the incrementer 605 are passed through. The fact that the index value can be decremented by this configuration can be explained as follows.

[0043]

[Equation 2]

Therefore

[0045]

[Equation 3]

From

[0047]

[Equation 4]

The index adjuster of FIG. 9 (d) has the same structure as the index adjusters 320, 321, 322 of the first conventional example. For the circuit configuration of the mantissa adder 112 and the mantissa bit inverters 109 and 114 before and after the mantissa adder 112, see FIG.
There are several options as shown in. The configuration shown in FIG. 10A is the one shown in this embodiment. The operation of these mantissa bit inverters described above is summarized in Table 5.

In FIG. 10B, the mantissa bit inverter 702 is moved to the input on the opposite side of the mantissa bit inverter 701 with respect to the mantissa adder 705. The operation of the mantissa bit inverter in this mantissa adder / subtractor configuration is listed in (Table 6).

[0050]

[Table 5]

[0051]

[Table 6]

The fact that the mantissa subtraction can be executed by the configuration of FIG. 10B can be explained as follows.

[0053]

[Equation 5]

In the present embodiment, the description has been made only on the situation of adding or subtracting normalized numbers to obtain the sum or difference of the normalized numbers.
Even if one of the operands is a denormalized number or 0, or if the operation result is a denormalized number or 0, it is clear that the calculation can be performed correctly without changing the above-mentioned arithmetic method. However, it is necessary to add some circuits such as the exponent lower overflow detection mechanism.

[0055]

As described above, according to the floating point adder / subtractor of the present invention, two mantissa adders / subtractors are required to process addition / subtraction of the mantissa part and rounding in one pipeline stage. On the other hand, in the case of true addition or true subtraction in which the exponent difference is not 0, the addition result of the mantissa adder / subtractor is normalized by the left and right 1-bit shifters according to the presence or absence of upper digit overflow or upper digit loss, and then the mantissa incrementer is used. In the case of accurate rounding and true subtraction when the exponent difference is 0, the negative subtraction result is converted into an absolute value (two's complement) by the inverter and the mantissa incrementer. As a result, the performance equivalent to that of the related art can be exhibited by one mantissa adder / subtractor. Therefore, there is an effect that the circuit scale can be made extremely small as compared with the conventional floating point addition / subtraction processing. In addition, since the circuit size is reduced, the critical path of the circuit is mitigated, so that the circuit can be sped up. As a result, the floating-point adder / subtractor can be realized at a lower cost, and its practical effect is great.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a floating-point addition / subtraction device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram illustrating names of bit positions of a mantissa part.

FIG. 3 is a configuration diagram of a first conventional floating-point addition / subtraction device.

FIG. 4 is a block diagram of a second conventional floating-point addition / subtraction device.

FIG. 5 is a schematic diagram (No. 1) for explaining a nearest value rounding method in true subtraction.

FIG. 6 is a schematic diagram (No. 2) for explaining a nearest-value rounding method in true subtraction.

FIG. 7 is a schematic diagram (No. 3) explaining the nearest-value rounding method in true subtraction.

FIG. 8 is a schematic diagram (No. 4) for explaining a nearest-value rounding method in true subtraction.

FIG. 9 is a configuration diagram illustrating a method of realizing an exponent adjuster.

FIG. 10 is a configuration diagram illustrating a method of implementing a mantissa adder / subtractor and a one's complementer.

[Explanation of symbols]

 101 Code Generator 102 Exponent Subtractor 103 Exponent Selector 104 Exponential Difference Absolute Quantizer 105 Mantissa Selector 106 Mantissa Selector 107 Mantissa Right Shifter 108 S-bit Generator 109 Mantissa Bit Inverter 110 Sign Inverter 111 Exponent Increase / Decrease 112 Mantissa adder 113 Left and right 1-bit shifter 114 Mantissa bit inverter 115 Rounding corrector 116 Exponent corrector 117 Mantissa incrementer 118 Leading 1 detector 119 Mantissa left shifter

Claims (3)

[Claims] 1. A floating-point adder / subtractor for calculating the sum or difference of two floating-point numbers represented by a sign, an exponent part, and a mantissa part, and the mantissa of the smaller of the two exponents. A small mantissa selecting means for selecting a part and, if the exponents are the same, one of the mantissa parts, and a large mantissa selecting means for selecting a mantissa part of the two floating point numbers different from the small mantissa part. , The digit of the mantissa selection means is logically shifted to the lower side (hereinafter referred to as right) by the absolute value of the exponent difference between the two floating point numbers (hereinafter referred to as digit matching), and the positive number is converted to a positive number. When adding or subtracting a negative number from a positive number or adding a negative number to a negative number or subtracting a positive number from a negative number (hereinafter referred to as the case of true addition), the digit-matched mantissa value is added to the output of the large mantissa selection means, Add a negative number to a positive number or from a positive number When subtracting a number or adding a positive number to a negative number or subtracting a negative number from a negative number (hereinafter referred to as a true subtraction), a mantissa adder / subtractor that subtracts the digit-matched mantissa from the output of the large mantissa selector, and a mantissa If the sum output from the adder / subtractor causes an upper overflow, the sum is shifted to the right by 1 bit, and if the difference causes a loss of 1 bit, the difference is shifted to the left by 1 bit. The bit shift means and the mantissa bit inverting means for inverting the output of each bit when the output of the left and right 1-bit shift means is negative and passing through otherwise, and the digit-matched mantissa value and the left and right 1-bit shift means. Rounding correction means for determining rounding logic based on the output, and 1 for 2's complement addition to the output of the mantissa bit inverting means when the addend / subtraction result is negative, and the rounding correction means Floating point addition and subtraction device characterized by comprising when it is determined 1 and to be added to 1 is added to the output of the mantissa bit inversion means, otherwise the mantissa increment means for plain it for rounding. 2. The mantissa adder / subtracter means is adapted to pass the digit-matched mantissa value through in the case of true addition, and to invert bit by bit in the case of true subtraction. Carry input generating means for generating a carry input for two's complementing based on the mantissa value, the output of the large mantissa selecting means and the output of the first mantissa bit inverting means in the case of true addition, The floating point addition / subtraction device according to claim 1, further comprising mantissa adding means for adding the carry input in the case of true subtraction. 3. The mantissa adder / subtractor causes the output of the large mantissa selector to pass through in the case of true addition,
In the case of true subtraction, first mantissa bit inverting means for inverting every bit, carry input generating means for generating a carry input for two's complement conversion based on the output of the big mantissa selecting means, and true add bit A mantissa adding means for adding the output of the first mantissa bit inverting means and the digit-matched mantissa value, and adding the carry input in addition to these for true subtraction;
The floating point addition / subtraction apparatus according to claim 1, further comprising: