JPS61131122A - Parallel pipeline processing device - Google Patents

Abstract

PURPOSE:To eliminate the need for a synchronizing control circuit and to attain high data processing speed by inserting a dummy delay means giving a delay corresponding to a delay time produced at the processing section in one pipeline to a timewise corresponding section of the other pipeline. CONSTITUTION:In applying edge emphasis operation in the operation processing between pictures, the synchronization between pictures is not matched. A spatial filter 5 of the processing system applies processing to lots of succeeding data while causing pipeline delay for several hundreds of pictures' delay in its operation, then the synchronization between two continuous picture images is not taken. Then the input is given to an interframe operating section 6 via a dummy delay section 7. The delay section 7 gives a delay corresponding to the operation delay of the filter 5 to the input data. Thus, the overhead for synchronizing the entire pipeline, that is, synchronizing control is not required at all and sophisticated and complicated data are processed in a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a parallel pipeline processing device that uses dummy delays to eliminate overhead in parallel pipeline processing.

Digital processing equipment has the ability to process complex processing at high speed.
A pipeline processing circuit is incorporated as one means. This pipeline processing circuit basically distributes the processing of the data to be processed in a chronological order and performs the processing sequentially, but as the complexity of the processing increases, the pipeline processing Since people are no longer able to achieve their intended goals to the fullest, there is a growing demand for improvement.

[Conventional technology]

The conventional pipeline processing format includes (7-1) in Figure 7.
As shown in Figure 7, single pipeline processing using a single pipeline, and as shown in (7-2) in Figure 7, multiple pipelines are used and processing is switched between pipelines, and the required processing is performed. There is parallel pipeline processing that performs data processing. ↑ or ↓ in the figure means synchronization control in mutual pipeline processing.

[Problem that the invention seeks to solve]

When performing more advanced and complicated processing in the former of these pipeline processes, there is a drawback that the throughput time becomes longer due to the uniqueness of the pipeline. On the other hand, in the latter case, the throughput time is reduced due to the plurality of pipelines, but it is essential to proceed with processing while synchronizing the pipelines, so synchronization is required in the management (monitoring) circuit, etc. There is a problem in that the operation of the circuit for taking the data intervenes in the processing, and this creates a bottleneck in the processing circuit when performing sophisticated and complicated processing.

[Means for solving problems]

The present invention provides a parallel pipeline processing device that solves the above-mentioned problems. A dummy delay means that provides a delay corresponding to the processing delay occurring in one pipeline processing section is inserted into the temporally corresponding section of the other pipeline to perform parallel pipeline processing.

[Effect]

According to the device of the present invention, when one pipeline process is progressing between parallel pipeline processes, the delay corresponding to the time until the end time of the pipeline process part of the other pipeline process is The time alignment, ie, synchronization, of both parallel processes is achieved at the end time given to the temporal correspondence section.

Therefore, pipeline processing that develops sophisticated and complex mutual relationships can be performed at high speed without requiring a conventional synchronous control circuit.

〔Example〕

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows an image processing apparatus embodying the present invention, in which digital image data from a device (not shown) for reading an input image 1 is sent to a predetermined network circuit 2 constituting a digital image processing section. The connection mode of this network circuit 2 can be defined in various ways, and by that definition, an arbitrary combination of a plurality of high-speed arithmetic processing units 31 to 311 is generated, and a series of The image processing system is constructed so as to be able to perform complex image processing at high speed by constructing a pipeline processing system.

In such an apparatus, if a digital image processing section having a configuration as shown in FIG. 4 is the subtraction part.)
Only the parts that have changes between the two images are extracted. The construction of this processing system is advantageous for extracting high-speed change points in moving images. And no synchronization problem occurs in that system. This is because the two images match.

Among such arithmetic operations between images, when an "edge enhancement" operation as shown in FIG. 3 is performed, synchronization between images becomes impossible. The spatial filter 5 in this processing system uses neighborhood data such as 3×3 to determine the central pixel from the relationship with its surroundings, and the interframe calculation unit 6 performs addition between two images. However, since the spatial filter 5 processes a large amount of subsequent data while causing a pipeline delay of several hundred images in its calculations, even if inter-frame calculations are not performed, two Correspondence (synchronization) between the images cannot be achieved, in other words, an overhead for synchronization control as shown in (4-1) in FIG. 4 occurs.

Therefore, as shown in FIG. 5, the input is connected to the interframe calculation section 6 via the dummy delay section 7. The dummy delay unit 7 provides input data with a delay corresponding to the calculation (processing) delay in the spatial filter 5. By doing this, the overhead for the entire pipeline processing system, that is, the synchronization control, is completely eliminated ((4-2 in Figure 4)).
), and it is possible to achieve a smooth implementation of sophisticated and complex data processing. In this way, although there is no phase shift in pipeline processing, the above-mentioned " Various operations such as "edge emphasis" can be easily implemented in the pipeline processing of the present invention described above.

FIG. 6 shows an example of a dummy delay circuit that can be used as a dummy delay section that enables such pipeline processing. In this figure, 20 is a delay memory, and the number of data to be written to and read from this memory 20 is set in a register 21. 22 is a counter, and when the first data is to be written to the delay memory 20, the first data is written to the starting address of the counter 22. At the time when the subsequent data reaches the delay memory 20, the counter 22 is updated by the clock to the address at which the data is written. This update is generated for each piece of data. Each of the updated addresses is compared with the value of the register 21, ie, the final write address, by a comparator 23. When these two addresses match, the comparator 23 generates an output signal, that is, a signal for resetting the counter 22, and the counter 22 is reset by the cough signal. In this way, the address supplied to the delay memory 20 is returned to its first address. With such address control, the delay memory 20 can be configured as a first-in, first-out FI
It operates as a FO (FO) type memory and provides the required delay to input data.

Note that this dummy delay circuit is only an example.

〔Effect of the invention〕

As explained above, according to the present invention, ■ it is possible to completely synchronize between pipelines in parallel pipeline processing, ■ slave 7, advanced'''L7L7 complex f-5' processing, high speed 9, j processing. It is possible to obtain the following effects.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of an image processing device implementing the present invention, and FIGS. 2, 3, and 5 are diagrams showing a part of the pipeline processing system provided in the device shown in FIG. (4-1) in FIG. 4 is a diagram for explaining the occurrence of overhead for synchronization control, and (4-2) in FIG. 4 is a diagram for explaining the present invention. ), FIG. 6 is a diagram showing an example of a dummy delay circuit used in the present invention, and FIG. 7 is a diagram showing a conventional pipeline processing system. In the figure, 2 is a network circuit; 3. Reference numerals 36 to 36 are high-speed calculation processing units, 5 is a spatial filter, 6 is an inter-frame calculation unit, and 7 is a dummy delay unit. Figure 1 Figure 2 Figure 3 Figure 5 Figure 4 Figure 6 Figure 7

Claims (2)

[Claims] (1) In a parallel pipeline processing device, a dummy delay means for providing a delay corresponding to a processing delay occurring in an arbitrary pipeline processing section in one pipeline between the pipelines used for processing is installed in the other pipeline. A parallel pipeline processing device characterized in that it is inserted into a temporally corresponding section of a pipeline to perform parallel pipeline processing. (2) The parallel pipeline processing device according to claim 1, wherein the pipeline subjected to the parallel processing is an image processing pipeline of an image processing device.