JPS63274279A - Moving picture processor - Google Patents

Abstract

PURPOSE:To scale down a device by providing a control circuit which controls a picture memory and an input-output bus and composing multistage processing of one stage parallel multi-processor when the multistage processing such as pre-filtering processing, encoding processing 1, information volume estimating processing and encoding processing 2 is executed. CONSTITUTION:When a control signal 107 from the control circuit 6 is '1', an input picture signal stored in the memory 5 is outputted to the moving picture input bus 100 and a picture sampled value is outputted to a sequential. A fetching command and a processing beginning instruction 104 are outputted to each unit processor from the control circuit 6. A moving picture signal after the pre-filtering processing outputted to a moving picture output bus 102 is written in the picture memory 5 again. After the processing is finished, each unit processor makes a processing finishing signal 105 (flag signal) to '1' from zero for the control circuit 6 and informs the processing is finished. The control circuit 6 receiving the processing finishing signal makes the control signal 107 to '1' from zero again for the picture memory 5 in a next scanning section and controls to transfer the picture signal of the next scanning line to each unit processor through a form bus 100. Thus the multistage processing can be effectively executed by one stage parallel multi-processor.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a high-efficiency video processing device for moving images that can be used in video conference systems and the like.

(Prior Art) Systems for compressing television signals using digital signal processing and conducting video conferences are being actively developed.

However, all of these encoding and decoding devices are made of large-scale dedicated hardware, and when the encoding algorithm is changed, some of the hardware must be rebuilt.

Therefore, as described on pages 5.5-69 (Reference 1) of the 1985 IEICE Comprehensive National Conference Proceedings (published in March 1985), one screen can be divided into multiple partial screens. Divide the screen, assign a signal processor to each, and divide the allocated partial screen into one screen sampling period (1
There is a multiprocessor-type video processing processor that processes images in 730 seconds).

The video processing processor of Document 1 can realize real-time processing and digital signal processing under software control, and therefore can be used in video processing devices used in video conferences and the like.

Generally, in a video processing device, as shown in FIG. It is composed of a prefilter 20, an encoding section 21, and a buffer section 22. The prefilter 20 performs spatial and temporal filtering in order to increase the coding gain in interframe coding. As an example of the encoding unit 21, orthogonal transform encoding is used for the motion-compensated interframe prediction error signal, as described in Proceedings of the 1986 IEICE Telecommunications Division National Conference Proceedings 527 (Reference 2). Hybrid coding has been reported as an efficient coding method. The post-R buffer unit 22 is a first-in, first-out storage circuit for outputting data to the transmission path at a constant speed, and the storage circuit controls the encoding unit so that the stored data is constant. When the encoding method shown in Fig. 2 is implemented using the video processing processor described above, multiple unit processors connected to the input bus must process all the data necessary for their respective areas. In order to capture and process within 1/30 seconds, the delay from input to output is always 1/30 second, and to duplicate capture between each processor, the input and output memory is the same for all processors. This requires more than four times the frame memory for one screen. Especially spacious! High-efficiency interframe coding that requires motion compensation for the I area requires a search range that is about four times the area in question, and the entire system requires more than ten times the frame memory for one screen.

Therefore, in order to solve this problem, each unit processor did not process within 1730 seconds, but processed the input range within one scan line or failed scan line. Volume 5.5-1 of the collection of lecture papers at the general national conference of academic societies (published in March 1986)
It is reported on page 51.

(Reference 3) Furthermore, according to this method, each processor only needs to hold input data up to several lines before, and neighborhood calculations such as filtering can be performed. Further, at this time, each unit processor has two systems of input and output, and a parallel multiprocessor in which one of the input and output is connected by a frame delay circuit enables inter-frame computation of the frame difference portion. Further, even if the processing does not end within the time of the - scanning line, if the area in charge can be processed within the losing scanning line, more complex processing can be realized.

However, as shown in Figure 2, in order to increase interframe correlation, spatial and temporal filtering is performed before encoding, and even such pre-filtering was performed using the parallel multiprocessor configuration described above. In this case, each unit processor must perform pre-filtering on a wide range of inputs required for motion compensation, and considering that each unit processor receives duplicate inputs, it is necessary to perform redundant pre-filtering processing. Each part is processed independently by separate processors, resulting in waste. This waste results in an increase in the number of processors, leading to an increase in the scale of the entire system. Therefore, in order to solve this problem, the output of the multiprocessor system that performs prefiltering is input to the multiprocessor system that performs hybrid encoding. Additionally, by connecting systems in multiple stages, duplicate processing can be eliminated. (Refer to Japanese Patent Publication No. 61-135316) According to this method, the delay in processing at each stage is within the time of one scanning line or multiple scanning lines, so even in this multi-stage configuration, the overall delay amount is In addition, it is possible to use the same processor for each unit processor in the first stage and the processor in the second stage, and the amount of memory or number of processors required for processing in each stage is small. By optimizing , it is also possible to reduce the size of the entire system.

(Problem to be solved by the invention) However, in the conventional technology that physically has a multi-stage configuration,
Since the number of connected stages and the number of unit processors in each stage are fixed by hardware, there is a problem that it cannot be handled flexibly when changing the encoding method.
As described in Proceedings 522 of IEICE Communications Division National Conference 1iFlff4, a method for controlling the amount of information generation by estimating the amount of information has been reported as an efficient encoding method.

This method includes the buttofilter 20, the encoder 21, and
and the backup unit 22, but as shown in FIG. 3, the encoding unit 21 is divided into 31 encoding processes 1, 32 information i estimation processes, and 33 encoding processes 2. This method performs information amount estimation processing in which the results 302 of encoding process 1 are totaled for one screen, and the encoding parameters 303 of encoding process 2 are determined based on the total results. The encoding process 1 at 31 performs orthogonal transform encoding of the motion compensated interframe prediction error signal, and the encoding process 2 at 33 performs quantization processing. When this method is introduced into the conventional technology, pre-filtering processing, encoding processing 1, information amount estimation processing, and encoding processing 2 are executed, so the number of connection stages needs to be changed to 4, and some hardware In addition, if this method were to be implemented using conventional technology, there would be a problem in that the device would be complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a video processing device that can simplify the device and flexibly respond to changes in software by using a single-stage parallel multiprocessor that effectively utilizes the input/output bus between each unit processor.

(Means for Solving the Problems) In order to solve these problems, the present invention provides a video processing device that includes a plurality of input buses and two output buses connected in parallel to each other. a unit processor of the same type; two sets of image memories each connected to one each of the input bus and output bus, each receiving one of the output buses as input and outputting to one of the input buses;
It is comprised of a control circuit that controls the output of the image memory and the input to the unit processor based on signals from the unit processor.

(Function) In the present invention, when performing multi-stage processing such as the above-mentioned pre-filtering processing, encoding processing 1, information amount estimation processing, and encoding processing 2, instead of connecting parallel multiprocessors in multiple stages, image memory By providing a control circuit to control the input/output bus and the input/output bus, multi-stage processing is configured with a single-stage parallel multiprocessor.

The results of the first stage pre-filtering process can be stored in the image memory via the output bus. In the motion compensated interframe encoding of the next encoding process 1, which requires input of a wide range overlappingly, the pre-filtering processing results are input via the input bus from the image memory that is fully stored.
Duplicate processing can also be avoided. The result of the encoding process 1 is stored again in the image memory via the output bus, and the information amount estimation process and the encoding process 2 are similarly performed. In this way, by effectively utilizing the input/output bus and image memory, it is possible to perform multi-stage processing even though it is configured with a single-stage parallel multiprocessor.
It is possible to do this efficiently.

With this configuration, it is possible to simplify the device, and it is also possible to flexibly respond to changes in software and the like. Furthermore, even when several lines of image data are supplied to the input/output bus, each unit processor takes in its own processing area and completes the processing, so the processing delay at each stage is within the lost scanning line time. Even in this configuration in which the circuits are logically connected in multiple stages, the overall amount of delay does not increase.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention that performs the pre-filtering process and the encoding process shown in FIG. It is a control circuit.

As will be explained in detail later, each unit processor 1, 2.3 divides and takes in areas necessary for pre-filtering processing, etc., and executes signal processing contents written in software one instruction at a time in one clock cycle. , and outputs the processing results.

The image memory 4.5 is a first-in first-out storage circuit,
Under the control of the control signal 106, 1<17 from the control circuit 6, image data is sequentially supplied to the video input buses 1oo and tot for lost scanning lines, while the video output bus 102 is supplied from each unit processor 1.2.3 to the video output bus 102. 103 is sequentially written for lost scanning lines.

Although the control circuit 6 will be described in detail later, each unit processor 1
, 2.3, with reference to the flag signal 105 output from
Control signal 106 for the aforementioned image memory 4.5,
107 and a capture start signal 104 to each unit processor 1, 2.3.

The operation of the circuit configured in this way will be explained in detail.

For the input image signal stored in the image memory 5, when the control signal 107 from the control circuit 6 is '1'', image sample values are sequentially output to the bus 100.Control signal 1
07 is a signal that becomes "1"' in a plurality of scanning line sections necessary for pre-filtering processing, and becomes "0" otherwise. An image signal is output from the image memory 5 to the bus 100 by the above-described control. At the same time, the control circuit 6 sends a fetch command and a processing start command 10 to each unit processor.
4 can be output. In accordance with the signal 104, each unit processor takes in a predetermined area and an area necessary for spatial filtering, etc. in duplicate with other processors, and performs preprogrammed spatial filtering processing and a process for increasing interframe correlation. Temporal filtering processing is started, and a video signal suitable for encoding is output to the video output bus 102. The pre-filtered video signal output to the video output bus 102 is written to the image memory 5 again. Furthermore, after completing the processing, each unit processor sends a processing end signal 105 to the control circuit 6 from "0" to '1'.
to notify the end of processing. The processing end signal 105 is a logical sum from each unit processor, and it is possible to know the end of processing of each unit processor. Upon receiving the processing end signal, the control circuit 6 changes the control signal 107 to the image memory 5 from "0" to "1" again for the next scanning period, and transmits the image signal of the next scanning line via the pattern bus 100. control the transfer to each unit processor.

By performing the above scanning for all scanning lines, the image memory 5 can store the image signal subjected to the pre-filtering process, and the pre-filtering process shown in FIG. 3 can be realized.

Next, in the case of an encoding process that performs orthogonal transform encoding of a motion-compensated inter-frame prem error signal, in order to perform motion compensation,
Each unit processor must take in a wide range of image signals, but in this case as well, the image signals of the scanning line section necessary for motion compensation are output from the image memory 5 to the bus 100, similar to the pre-filtering process described above. , each unit processor takes in a predetermined area and an area necessary for performing motion compensation overlappingly with other processors, and performs orthogonal transform encoding of a motion compensated interframe prediction error signal,
This can be realized by storing the processing results in the image memory 5 again via the bus 102.

Next, in the information amount estimation processing section, similarly to the pre-filtering processing described above, each unit processor takes in the area in charge of the processing result of the orthogonal transform encoding of the motion compensated interframe prediction error signal from the image memory 5, and Encoding processing 2 that calculates statistics for the region, writes the final result to the image memory 4 via the output bus 103, performs quantization processing, etc.
Then, each unit processor transfers the image signal of the scanning line section from the image memory 5 in which the processing result of the encoding process 1 has been stored to the bus 100 in the same manner as in the pre-filtering process described above.
At the same time, from the image memory 4 in which the statistics of each divided area are stored, all the results aggregated by each unit processor are fetched via the input bus 101, and the statistics of the entire screen are calculated. A quantization parameter is determined based on the statistics of the entire screen, and the final encoding result is stored in the image memory 4 via the output bus 103.

As explained above, the pre-filtering process, encoding process 1, information amount estimation process, and encoding process 2 shown in FIG. 3 are realized by the one-stage parallel multiprocessor shown in FIG.

The fourth (!I is the unit processor 1, 2, 3 (
7) - A specific example is shown, where 40 is the intake part, 41
42 is a processing section, 42 is an output section, and 43 is a control section. The input 'N40 is two sets of memory circuits capable of sequential writing and random reading, and receives the input signal 40.
Sequential writing of 0 and 401 is performed by the control unit 4.
3, the signal 402 was randomly read out.
, 403 are controlled by a processing unit 41 written in software. The output unit 42 is a first-in, first-out storage circuit, and a processing result 404 of the processing unit 42 is written therein. The control unit 43 outputs a capture command signal 407 to the capture unit 40 when data necessary for its own processing is present on the input bus based on a system clock that can be separately supplied to the entire system and a control signal 410 input from the outside. do. Also, when the imported data is ready and processing can begin,
A processing start command signal 408 is output to the processing section 41 . Then, it identifies the point in time when it must output to the output bus, and transmits an output command signal 409 to the output unit 42. Furthermore, at the time of the end of the process, a process end flag 411 is output. The processing unit 41 is a signal processing processor that can execute one instruction in one clock cycle for signal processing contents written in software, and is a signal processing processor that can execute one instruction in one clock cycle.
It is composed of PD7720 etc.

FIG. 5 shows a specific example of the control circuit 6 in FIG. 1, in which 50 is a processing circuit, 51, 52 are comparison circuits, 53,
54 is a counter, and 55 is an OR circuit. The processing circuit 50 receives the processing end signal 500 outputted from each unit processor shown in FIG. 1 from the system clock, vertical synchronization signal, and horizontal synchronization signal separately supplied to the entire system according to a predetermined sequence. image memory 4
, 5 to control the number of output scanning lines. Comparison circuits 51, 52
are the output scanning line number setting values 510 and 5 from the processing circuit 50.
This is a circuit that compares outputs 502 and 505 of counters 53 and 54 with 04 and sets 507 and 508 to "1" if 501 and 504 are dogs, and sets them to 'O' otherwise.Counters 53 and 54 is a circuit that counts up by a system clock and a vertical synchronization signal that are separately supplied to the entire system when the clear signals 503 and 506 from the processing circuit 50 are "1". Output of 52 When either one of 507 and 508 is “1”, “1” is output, otherwise “1” is output.
0''.

The present invention can be implemented as described above.

(Effects of the Invention) As explained above, according to the present invention, pre-filtering processing, encoding processing 1, information amount estimation processing, encoding processing 2
Such multi-stage processing can be efficiently realized with a single-stage parallel multiprocessor.

In addition, the image signals to be transferred to each processor are not determined on a -1 basis, but are controlled to be transferred for each multiple scanning line according to the processing time of each processor. Transfer intervals are different, efficiency does not deteriorate due to processing division in each stage, and software can be changed flexibly.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 and 3 are block diagrams showing the configuration of a general video processing device, and FIG. Block Diagram Showing a Specific Example FIG. 5 is a block diagram showing a specific example of the control circuit in the embodiment of FIG. 1.2.3... Unit processor, 4.5... Image memory, 6... Control circuit.

Claims (1)

[Scope of Claims] A plurality of unit processors of the same type connected in parallel to each of two input buses and two output buses; two sets of image memories that take one of the output buses as an input and output to one of the input buses; and a control circuit that controls the output of the image memory and the input to the unit processor based on a signal from the unit processor. A video processing device consisting of.